2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
26 #include <subdev/fb.h>
27 #include <subdev/mc.h>
29 /*******************************************************************************
30 * PGRAPH context register lists
31 ******************************************************************************/
33 static const struct gf100_gr_init
34 gf117_grctx_init_ds_0[] = {
35 { 0x405800, 1, 0x04, 0x0f8000bf },
36 { 0x405830, 1, 0x04, 0x02180324 },
37 { 0x405834, 1, 0x04, 0x08000000 },
38 { 0x405838, 1, 0x04, 0x00000000 },
39 { 0x405854, 1, 0x04, 0x00000000 },
40 { 0x405870, 4, 0x04, 0x00000001 },
41 { 0x405a00, 2, 0x04, 0x00000000 },
42 { 0x405a18, 1, 0x04, 0x00000000 },
46 static const struct gf100_gr_init
47 gf117_grctx_init_pd_0[] = {
48 { 0x406020, 1, 0x04, 0x000103c1 },
49 { 0x406028, 4, 0x04, 0x00000001 },
50 { 0x4064a8, 1, 0x04, 0x00000000 },
51 { 0x4064ac, 1, 0x04, 0x00003fff },
52 { 0x4064b4, 3, 0x04, 0x00000000 },
53 { 0x4064c0, 1, 0x04, 0x801a0078 },
54 { 0x4064c4, 1, 0x04, 0x00c9ffff },
55 { 0x4064d0, 8, 0x04, 0x00000000 },
59 static const struct gf100_gr_pack
60 gf117_grctx_pack_hub[] = {
61 { gf100_grctx_init_main_0 },
62 { gf119_grctx_init_fe_0 },
63 { gf100_grctx_init_pri_0 },
64 { gf100_grctx_init_memfmt_0 },
65 { gf117_grctx_init_ds_0 },
66 { gf117_grctx_init_pd_0 },
67 { gf100_grctx_init_rstr2d_0 },
68 { gf100_grctx_init_scc_0 },
69 { gf119_grctx_init_be_0 },
73 static const struct gf100_gr_init
74 gf117_grctx_init_setup_0[] = {
75 { 0x418800, 1, 0x04, 0x7006860a },
76 { 0x418808, 3, 0x04, 0x00000000 },
77 { 0x418828, 1, 0x04, 0x00008442 },
78 { 0x418830, 1, 0x04, 0x10000001 },
79 { 0x4188d8, 1, 0x04, 0x00000008 },
80 { 0x4188e0, 1, 0x04, 0x01000000 },
81 { 0x4188e8, 5, 0x04, 0x00000000 },
82 { 0x4188fc, 1, 0x04, 0x20100018 },
86 static const struct gf100_gr_pack
87 gf117_grctx_pack_gpc[] = {
88 { gf100_grctx_init_gpc_unk_0 },
89 { gf119_grctx_init_prop_0 },
90 { gf119_grctx_init_gpc_unk_1 },
91 { gf117_grctx_init_setup_0 },
92 { gf100_grctx_init_zcull_0 },
93 { gf119_grctx_init_crstr_0 },
94 { gf108_grctx_init_gpm_0 },
95 { gf100_grctx_init_gcc_0 },
99 const struct gf100_gr_init
100 gf117_grctx_init_pe_0[] = {
101 { 0x419848, 1, 0x04, 0x00000000 },
102 { 0x419864, 1, 0x04, 0x00000129 },
103 { 0x419888, 1, 0x04, 0x00000000 },
107 static const struct gf100_gr_init
108 gf117_grctx_init_tex_0[] = {
109 { 0x419a00, 1, 0x04, 0x000001f0 },
110 { 0x419a04, 1, 0x04, 0x00000001 },
111 { 0x419a08, 1, 0x04, 0x00000023 },
112 { 0x419a0c, 1, 0x04, 0x00020000 },
113 { 0x419a10, 1, 0x04, 0x00000000 },
114 { 0x419a14, 1, 0x04, 0x00000200 },
115 { 0x419a1c, 1, 0x04, 0x00008000 },
116 { 0x419a20, 1, 0x04, 0x00000800 },
117 { 0x419ac4, 1, 0x04, 0x0017f440 },
121 static const struct gf100_gr_init
122 gf117_grctx_init_mpc_0[] = {
123 { 0x419c00, 1, 0x04, 0x0000000a },
124 { 0x419c04, 1, 0x04, 0x00000006 },
125 { 0x419c08, 1, 0x04, 0x00000002 },
126 { 0x419c20, 1, 0x04, 0x00000000 },
127 { 0x419c24, 1, 0x04, 0x00084210 },
128 { 0x419c28, 1, 0x04, 0x3efbefbe },
132 static const struct gf100_gr_pack
133 gf117_grctx_pack_tpc[] = {
134 { gf117_grctx_init_pe_0 },
135 { gf117_grctx_init_tex_0 },
136 { gf117_grctx_init_mpc_0 },
137 { gf104_grctx_init_l1c_0 },
138 { gf119_grctx_init_sm_0 },
142 static const struct gf100_gr_init
143 gf117_grctx_init_pes_0[] = {
144 { 0x41be24, 1, 0x04, 0x00000002 },
148 static const struct gf100_gr_init
149 gf117_grctx_init_cbm_0[] = {
150 { 0x41bec0, 1, 0x04, 0x12180000 },
151 { 0x41bec4, 1, 0x04, 0x00003fff },
152 { 0x41bee4, 1, 0x04, 0x03240218 },
156 const struct gf100_gr_init
157 gf117_grctx_init_wwdx_0[] = {
158 { 0x41bf00, 1, 0x04, 0x0a418820 },
159 { 0x41bf04, 1, 0x04, 0x062080e6 },
160 { 0x41bf08, 1, 0x04, 0x020398a4 },
161 { 0x41bf0c, 1, 0x04, 0x0e629062 },
162 { 0x41bf10, 1, 0x04, 0x0a418820 },
163 { 0x41bf14, 1, 0x04, 0x000000e6 },
164 { 0x41bfd0, 1, 0x04, 0x00900103 },
165 { 0x41bfe0, 1, 0x04, 0x00400001 },
166 { 0x41bfe4, 1, 0x04, 0x00000000 },
170 static const struct gf100_gr_pack
171 gf117_grctx_pack_ppc[] = {
172 { gf117_grctx_init_pes_0 },
173 { gf117_grctx_init_cbm_0 },
174 { gf117_grctx_init_wwdx_0 },
178 /*******************************************************************************
179 * PGRAPH context implementation
180 ******************************************************************************/
183 gf117_grctx_generate_dist_skip_table(struct gf100_gr *gr)
185 struct nvkm_device *device = gr->base.engine.subdev.device;
188 for (i = 0; i < 8; i++)
189 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
193 gf117_grctx_generate_rop_mapping(struct gf100_gr *gr)
195 struct nvkm_device *device = gr->base.engine.subdev.device;
196 u32 data[6] = {}, data2[2] = {};
201 /* calculate first set of magics */
202 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
205 for (tpc = 0; tpc < gr->tpc_total; tpc++) {
207 gpc = (gpc + 1) % gr->gpc_nr;
208 } while (!tpcnr[gpc]);
211 data[tpc / 6] |= gpc << ((tpc % 6) * 5);
214 for (; tpc < 32; tpc++)
215 data[tpc / 6] |= 7 << ((tpc % 6) * 5);
217 /* and the second... */
219 ntpcv = gr->tpc_total;
220 while (!(ntpcv & (1 << 4))) {
225 data2[0] = (ntpcv << 16);
226 data2[0] |= (shift << 21);
227 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
228 for (i = 1; i < 7; i++)
229 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
232 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
233 gr->screen_tile_row_offset);
234 for (i = 0; i < 6; i++)
235 nvkm_wr32(device, 0x418b08 + (i * 4), data[i]);
237 /* GPC_BROADCAST.TP_BROADCAST */
238 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
239 gr->screen_tile_row_offset | data2[0]);
240 nvkm_wr32(device, 0x41bfe4, data2[1]);
241 for (i = 0; i < 6; i++)
242 nvkm_wr32(device, 0x41bf00 + (i * 4), data[i]);
245 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
246 gr->screen_tile_row_offset);
247 for (i = 0; i < 6; i++)
248 nvkm_wr32(device, 0x40780c + (i * 4), data[i]);
252 gf117_grctx_generate_attrib(struct gf100_grctx *info)
254 struct gf100_gr *gr = info->gr;
255 const struct gf100_grctx_func *grctx = gr->func->grctx;
256 const u32 alpha = grctx->alpha_nr;
257 const u32 beta = grctx->attrib_nr;
258 const u32 size = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max);
260 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false);
261 const int timeslice_mode = 1;
262 const int max_batches = 0xffff;
264 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total;
267 mmio_refn(info, 0x418810, 0x80000000, s, b);
268 mmio_refn(info, 0x419848, 0x10000000, s, b);
269 mmio_wr32(info, 0x405830, (beta << 16) | alpha);
270 mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
272 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
273 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
274 const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc];
275 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc];
276 const u32 t = timeslice_mode;
277 const u32 o = PPC_UNIT(gpc, ppc, 0);
278 if (!(gr->ppc_mask[gpc] & (1 << ppc)))
280 mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo);
281 mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo);
282 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
283 mmio_wr32(info, o + 0xe4, (a << 16) | ao);
284 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
290 gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
292 struct nvkm_device *device = gr->base.engine.subdev.device;
293 const struct gf100_grctx_func *grctx = gr->func->grctx;
296 nvkm_mc_unk260(device, 0);
298 gf100_gr_mmio(gr, grctx->hub);
299 gf100_gr_mmio(gr, grctx->gpc);
300 gf100_gr_mmio(gr, grctx->zcull);
301 gf100_gr_mmio(gr, grctx->tpc);
302 gf100_gr_mmio(gr, grctx->ppc);
304 idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);
307 grctx->pagepool(info);
311 gf100_grctx_generate_floorsweep(gr);
313 gf100_gr_icmd(gr, grctx->icmd);
314 nvkm_wr32(device, 0x404154, idle_timeout);
315 gf100_gr_mthd(gr, grctx->mthd);
316 nvkm_mc_unk260(device, 1);
319 const struct gf100_grctx_func
321 .main = gf117_grctx_generate_main,
322 .unkn = gk104_grctx_generate_unkn,
323 .hub = gf117_grctx_pack_hub,
324 .gpc = gf117_grctx_pack_gpc,
325 .zcull = gf100_grctx_pack_zcull,
326 .tpc = gf117_grctx_pack_tpc,
327 .ppc = gf117_grctx_pack_ppc,
328 .icmd = gf119_grctx_pack_icmd,
329 .mthd = gf119_grctx_pack_mthd,
330 .bundle = gf100_grctx_generate_bundle,
331 .bundle_size = 0x1800,
332 .pagepool = gf100_grctx_generate_pagepool,
333 .pagepool_size = 0x8000,
334 .attrib = gf117_grctx_generate_attrib,
335 .attrib_nr_max = 0x324,
337 .alpha_nr_max = 0x7ff,
339 .sm_id = gf100_grctx_generate_sm_id,
340 .tpc_nr = gf100_grctx_generate_tpc_nr,
341 .r4060a8 = gf100_grctx_generate_r4060a8,
342 .rop_mapping = gf117_grctx_generate_rop_mapping,
343 .alpha_beta_tables = gf100_grctx_generate_alpha_beta_tables,
344 .max_ways_evict = gf100_grctx_generate_max_ways_evict,
345 .dist_skip_table = gf117_grctx_generate_dist_skip_table,
346 .r419cb8 = gf100_grctx_generate_r419cb8,