drivers/gpu/drm/nouveau/nvc0_fifo.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26
  27 #include "nouveau_drv.h"
  28 #include "nouveau_mm.h"
  29
  30 static void nvc0_fifo_isr(struct drm_device *);
  31
  32 struct nvc0_fifo_priv {
  33         struct nouveau_gpuobj *playlist[2];
  34         int cur_playlist;
  35         struct nouveau_vma user_vma;
  36         int spoon_nr;
  37 };
  38
  39 struct nvc0_fifo_chan {
  40         struct nouveau_gpuobj *user;
  41         struct nouveau_gpuobj *ramfc;
  42 };
  43
  44 static void
  45 nvc0_fifo_playlist_update(struct drm_device *dev)
  46 {
  47         struct drm_nouveau_private *dev_priv = dev->dev_private;
  48         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
  49         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  50         struct nvc0_fifo_priv *priv = pfifo->priv;
  51         struct nouveau_gpuobj *cur;
  52         int i, p;
  53
  54         cur = priv->playlist[priv->cur_playlist];
  55         priv->cur_playlist = !priv->cur_playlist;
  56
  57         for (i = 0, p = 0; i < 128; i++) {
  58                 if (!(nv_rd32(dev, 0x3004 + (i * 8)) & 1))
  59                         continue;
  60                 nv_wo32(cur, p + 0, i);
  61                 nv_wo32(cur, p + 4, 0x00000004);
  62                 p += 8;
  63         }
  64         pinstmem->flush(dev);
  65
  66         nv_wr32(dev, 0x002270, cur->vinst >> 12);
  67         nv_wr32(dev, 0x002274, 0x01f00000 | (p >> 3));
  68         if (!nv_wait(dev, 0x00227c, 0x00100000, 0x00000000))
  69                 NV_ERROR(dev, "PFIFO - playlist update failed\n");
  70 }
  71
  72 void
  73 nvc0_fifo_disable(struct drm_device *dev)
  74 {
  75 }
  76
  77 void
  78 nvc0_fifo_enable(struct drm_device *dev)
  79 {
  80 }
  81
  82 bool
  83 nvc0_fifo_reassign(struct drm_device *dev, bool enable)
  84 {
  85         return false;
  86 }
  87
  88 bool
  89 nvc0_fifo_cache_pull(struct drm_device *dev, bool enable)
  90 {
  91         return false;
  92 }
  93
  94 int
  95 nvc0_fifo_channel_id(struct drm_device *dev)
  96 {
  97         return 127;
  98 }
  99
 100 int
 101 nvc0_fifo_create_context(struct nouveau_channel *chan)
 102 {
 103         struct drm_device *dev = chan->dev;
 104         struct drm_nouveau_private *dev_priv = dev->dev_private;
 105         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 106         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 107         struct nvc0_fifo_priv *priv = pfifo->priv;
 108         struct nvc0_fifo_chan *fifoch;
 109         u64 ib_virt = chan->pushbuf_base + chan->dma.ib_base * 4;
 110         int ret;
 111
 112         chan->fifo_priv = kzalloc(sizeof(*fifoch), GFP_KERNEL);
 113         if (!chan->fifo_priv)
 114                 return -ENOMEM;
 115         fifoch = chan->fifo_priv;
 116
 117         /* allocate vram for control regs, map into polling area */
 118         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000,
 119                                  NVOBJ_FLAG_ZERO_ALLOC, &fifoch->user);
 120         if (ret)
 121                 goto error;
 122
 123         nouveau_vm_map_at(&priv->user_vma, chan->id * 0x1000,
 124                           *(struct nouveau_mem **)fifoch->user->node);
 125
 126         chan->user = ioremap_wc(pci_resource_start(dev->pdev, 1) +
 127                                 priv->user_vma.offset + (chan->id * 0x1000),
 128                                 PAGE_SIZE);
 129         if (!chan->user) {
 130                 ret = -ENOMEM;
 131                 goto error;
 132         }
 133
 134         /* ramfc */
 135         ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst,
 136                                       chan->ramin->vinst, 0x100,
 137                                       NVOBJ_FLAG_ZERO_ALLOC, &fifoch->ramfc);
 138         if (ret)
 139                 goto error;
 140
 141         nv_wo32(fifoch->ramfc, 0x08, lower_32_bits(fifoch->user->vinst));
 142         nv_wo32(fifoch->ramfc, 0x0c, upper_32_bits(fifoch->user->vinst));
 143         nv_wo32(fifoch->ramfc, 0x10, 0x0000face);
 144         nv_wo32(fifoch->ramfc, 0x30, 0xfffff902);
 145         nv_wo32(fifoch->ramfc, 0x48, lower_32_bits(ib_virt));
 146         nv_wo32(fifoch->ramfc, 0x4c, drm_order(chan->dma.ib_max + 1) << 16 |
 147                                    upper_32_bits(ib_virt));
 148         nv_wo32(fifoch->ramfc, 0x54, 0x00000002);
 149         nv_wo32(fifoch->ramfc, 0x84, 0x20400000);
 150         nv_wo32(fifoch->ramfc, 0x94, 0x30000001);
 151         nv_wo32(fifoch->ramfc, 0x9c, 0x00000100);
 152         nv_wo32(fifoch->ramfc, 0xa4, 0x1f1f1f1f);
 153         nv_wo32(fifoch->ramfc, 0xa8, 0x1f1f1f1f);
 154         nv_wo32(fifoch->ramfc, 0xac, 0x0000001f);
 155         nv_wo32(fifoch->ramfc, 0xb8, 0xf8000000);
 156         nv_wo32(fifoch->ramfc, 0xf8, 0x10003080); /* 0x002310 */
 157         nv_wo32(fifoch->ramfc, 0xfc, 0x10000010); /* 0x002350 */
 158         pinstmem->flush(dev);
 159
 160         nv_wr32(dev, 0x003000 + (chan->id * 8), 0xc0000000 |
 161                                                 (chan->ramin->vinst >> 12));
 162         nv_wr32(dev, 0x003004 + (chan->id * 8), 0x001f0001);
 163         nvc0_fifo_playlist_update(dev);
 164         return 0;
 165
 166 error:
 167         pfifo->destroy_context(chan);
 168         return ret;
 169 }
 170
 171 void
 172 nvc0_fifo_destroy_context(struct nouveau_channel *chan)
 173 {
 174         struct drm_device *dev = chan->dev;
 175         struct nvc0_fifo_chan *fifoch;
 176
 177         nv_mask(dev, 0x003004 + (chan->id * 8), 0x00000001, 0x00000000);
 178         nv_wr32(dev, 0x002634, chan->id);
 179         if (!nv_wait(dev, 0x0002634, 0xffffffff, chan->id))
 180                 NV_WARN(dev, "0x2634 != chid: 0x%08x\n", nv_rd32(dev, 0x2634));
 181
 182         nvc0_fifo_playlist_update(dev);
 183
 184         nv_wr32(dev, 0x003000 + (chan->id * 8), 0x00000000);
 185
 186         if (chan->user) {
 187                 iounmap(chan->user);
 188                 chan->user = NULL;
 189         }
 190
 191         fifoch = chan->fifo_priv;
 192         chan->fifo_priv = NULL;
 193         if (!fifoch)
 194                 return;
 195
 196         nouveau_gpuobj_ref(NULL, &fifoch->ramfc);
 197         nouveau_gpuobj_ref(NULL, &fifoch->user);
 198         kfree(fifoch);
 199 }
 200
 201 int
 202 nvc0_fifo_load_context(struct nouveau_channel *chan)
 203 {
 204         return 0;
 205 }
 206
 207 int
 208 nvc0_fifo_unload_context(struct drm_device *dev)
 209 {
 210         int i;
 211
 212         for (i = 0; i < 128; i++) {
 213                 if (!(nv_rd32(dev, 0x003004 + (i * 8)) & 1))
 214                         continue;
 215
 216                 nv_mask(dev, 0x003004 + (i * 8), 0x00000001, 0x00000000);
 217                 nv_wr32(dev, 0x002634, i);
 218                 if (!nv_wait(dev, 0x002634, 0xffffffff, i)) {
 219                         NV_INFO(dev, "PFIFO: kick ch %d failed: 0x%08x\n",
 220                                 i, nv_rd32(dev, 0x002634));
 221                         return -EBUSY;
 222                 }
 223         }
 224
 225         return 0;
 226 }
 227
 228 static void
 229 nvc0_fifo_destroy(struct drm_device *dev)
 230 {
 231         struct drm_nouveau_private *dev_priv = dev->dev_private;
 232         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 233         struct nvc0_fifo_priv *priv;
 234
 235         priv = pfifo->priv;
 236         if (!priv)
 237                 return;
 238
 239         nouveau_vm_put(&priv->user_vma);
 240         nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
 241         nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
 242         kfree(priv);
 243 }
 244
 245 void
 246 nvc0_fifo_takedown(struct drm_device *dev)
 247 {
 248         nv_wr32(dev, 0x002140, 0x00000000);
 249         nvc0_fifo_destroy(dev);
 250 }
 251
 252 static int
 253 nvc0_fifo_create(struct drm_device *dev)
 254 {
 255         struct drm_nouveau_private *dev_priv = dev->dev_private;
 256         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 257         struct nvc0_fifo_priv *priv;
 258         int ret;
 259
 260         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 261         if (!priv)
 262                 return -ENOMEM;
 263         pfifo->priv = priv;
 264
 265         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, 0,
 266                                  &priv->playlist[0]);
 267         if (ret)
 268                 goto error;
 269
 270         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, 0,
 271                                  &priv->playlist[1]);
 272         if (ret)
 273                 goto error;
 274
 275         ret = nouveau_vm_get(dev_priv->bar1_vm, pfifo->channels * 0x1000,
 276                              12, NV_MEM_ACCESS_RW, &priv->user_vma);
 277         if (ret)
 278                 goto error;
 279
 280         nouveau_irq_register(dev, 8, nvc0_fifo_isr);
 281         return 0;
 282
 283 error:
 284         nvc0_fifo_destroy(dev);
 285         return ret;
 286 }
 287
 288 int
 289 nvc0_fifo_init(struct drm_device *dev)
 290 {
 291         struct drm_nouveau_private *dev_priv = dev->dev_private;
 292         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 293         struct nouveau_channel *chan;
 294         struct nvc0_fifo_priv *priv;
 295         int ret, i;
 296
 297         if (!pfifo->priv) {
 298                 ret = nvc0_fifo_create(dev);
 299                 if (ret)
 300                         return ret;
 301         }
 302         priv = pfifo->priv;
 303
 304         /* reset PFIFO, enable all available PSUBFIFO areas */
 305         nv_mask(dev, 0x000200, 0x00000100, 0x00000000);
 306         nv_mask(dev, 0x000200, 0x00000100, 0x00000100);
 307         nv_wr32(dev, 0x000204, 0xffffffff);
 308         nv_wr32(dev, 0x002204, 0xffffffff);
 309
 310         priv->spoon_nr = hweight32(nv_rd32(dev, 0x002204));
 311         NV_DEBUG(dev, "PFIFO: %d subfifo(s)\n", priv->spoon_nr);
 312
 313         /* assign engines to subfifos */
 314         if (priv->spoon_nr >= 3) {
 315                 nv_wr32(dev, 0x002208, ~(1 << 0)); /* PGRAPH */
 316                 nv_wr32(dev, 0x00220c, ~(1 << 1)); /* PVP */
 317                 nv_wr32(dev, 0x002210, ~(1 << 1)); /* PPP */
 318                 nv_wr32(dev, 0x002214, ~(1 << 1)); /* PBSP */
 319                 nv_wr32(dev, 0x002218, ~(1 << 2)); /* PCE0 */
 320                 nv_wr32(dev, 0x00221c, ~(1 << 1)); /* PCE1 */
 321         }
 322
 323         /* PSUBFIFO[n] */
 324         for (i = 0; i < priv->spoon_nr; i++) {
 325                 nv_mask(dev, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 326                 nv_wr32(dev, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 327                 nv_wr32(dev, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTR_EN */
 328         }
 329
 330         nv_mask(dev, 0x002200, 0x00000001, 0x00000001);
 331         nv_wr32(dev, 0x002254, 0x10000000 | priv->user_vma.offset >> 12);
 332
 333         nv_wr32(dev, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */
 334         nv_wr32(dev, 0x002100, 0xffffffff);
 335         nv_wr32(dev, 0x002140, 0xbfffffff);
 336
 337         /* restore PFIFO context table */
 338         for (i = 0; i < 128; i++) {
 339                 chan = dev_priv->channels.ptr[i];
 340                 if (!chan || !chan->fifo_priv)
 341                         continue;
 342
 343                 nv_wr32(dev, 0x003000 + (i * 8), 0xc0000000 |
 344                                                  (chan->ramin->vinst >> 12));
 345                 nv_wr32(dev, 0x003004 + (i * 8), 0x001f0001);
 346         }
 347         nvc0_fifo_playlist_update(dev);
 348
 349         return 0;
 350 }
 351
 352 struct nouveau_enum nvc0_fifo_fault_unit[] = {
 353         { 0x00, "PGRAPH" },
 354         { 0x03, "PEEPHOLE" },
 355         { 0x04, "BAR1" },
 356         { 0x05, "BAR3" },
 357         { 0x07, "PFIFO" },
 358         { 0x10, "PBSP" },
 359         { 0x11, "PPPP" },
 360         { 0x13, "PCOUNTER" },
 361         { 0x14, "PVP" },
 362         { 0x15, "PCOPY0" },
 363         { 0x16, "PCOPY1" },
 364         { 0x17, "PDAEMON" },
 365         {}
 366 };
 367
 368 struct nouveau_enum nvc0_fifo_fault_reason[] = {
 369         { 0x00, "PT_NOT_PRESENT" },
 370         { 0x01, "PT_TOO_SHORT" },
 371         { 0x02, "PAGE_NOT_PRESENT" },
 372         { 0x03, "VM_LIMIT_EXCEEDED" },
 373         { 0x04, "NO_CHANNEL" },
 374         { 0x05, "PAGE_SYSTEM_ONLY" },
 375         { 0x06, "PAGE_READ_ONLY" },
 376         { 0x0a, "COMPRESSED_SYSRAM" },
 377         { 0x0c, "INVALID_STORAGE_TYPE" },
 378         {}
 379 };
 380
 381 struct nouveau_enum nvc0_fifo_fault_hubclient[] = {
 382         { 0x01, "PCOPY0" },
 383         { 0x02, "PCOPY1" },
 384         { 0x04, "DISPATCH" },
 385         { 0x05, "CTXCTL" },
 386         { 0x06, "PFIFO" },
 387         { 0x07, "BAR_READ" },
 388         { 0x08, "BAR_WRITE" },
 389         { 0x0b, "PVP" },
 390         { 0x0c, "PPPP" },
 391         { 0x0d, "PBSP" },
 392         { 0x11, "PCOUNTER" },
 393         { 0x12, "PDAEMON" },
 394         { 0x14, "CCACHE" },
 395         { 0x15, "CCACHE_POST" },
 396         {}
 397 };
 398
 399 struct nouveau_enum nvc0_fifo_fault_gpcclient[] = {
 400         { 0x01, "TEX" },
 401         { 0x0c, "ESETUP" },
 402         { 0x0e, "CTXCTL" },
 403         { 0x0f, "PROP" },
 404         {}
 405 };
 406
 407 struct nouveau_bitfield nvc0_fifo_subfifo_intr[] = {
 408 /*      { 0x00008000, "" }      seen with null ib push */
 409         { 0x00200000, "ILLEGAL_MTHD" },
 410         { 0x00800000, "EMPTY_SUBC" },
 411         {}
 412 };
 413
 414 static void
 415 nvc0_fifo_isr_vm_fault(struct drm_device *dev, int unit)
 416 {
 417         u32 inst = nv_rd32(dev, 0x2800 + (unit * 0x10));
 418         u32 valo = nv_rd32(dev, 0x2804 + (unit * 0x10));
 419         u32 vahi = nv_rd32(dev, 0x2808 + (unit * 0x10));
 420         u32 stat = nv_rd32(dev, 0x280c + (unit * 0x10));
 421         u32 client = (stat & 0x00001f00) >> 8;
 422
 423         NV_INFO(dev, "PFIFO: %s fault at 0x%010llx [",
 424                 (stat & 0x00000080) ? "write" : "read", (u64)vahi << 32 | valo);
 425         nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);
 426         printk("] from ");
 427         nouveau_enum_print(nvc0_fifo_fault_unit, unit);
 428         if (stat & 0x00000040) {
 429                 printk("/");
 430                 nouveau_enum_print(nvc0_fifo_fault_hubclient, client);
 431         } else {
 432                 printk("/GPC%d/", (stat & 0x1f000000) >> 24);
 433                 nouveau_enum_print(nvc0_fifo_fault_gpcclient, client);
 434         }
 435         printk(" on channel 0x%010llx\n", (u64)inst << 12);
 436 }
 437
 438 static int
 439 nvc0_fifo_page_flip(struct drm_device *dev, u32 chid)
 440 {
 441         struct drm_nouveau_private *dev_priv = dev->dev_private;
 442         struct nouveau_channel *chan = NULL;
 443         unsigned long flags;
 444         int ret = -EINVAL;
 445
 446         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 447         if (likely(chid >= 0 && chid < dev_priv->engine.fifo.channels)) {
 448                 chan = dev_priv->channels.ptr[chid];
 449                 if (likely(chan))
 450                         ret = nouveau_finish_page_flip(chan, NULL);
 451         }
 452         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 453         return ret;
 454 }
 455
 456 static void
 457 nvc0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
 458 {
 459         u32 stat = nv_rd32(dev, 0x040108 + (unit * 0x2000));
 460         u32 addr = nv_rd32(dev, 0x0400c0 + (unit * 0x2000));
 461         u32 data = nv_rd32(dev, 0x0400c4 + (unit * 0x2000));
 462         u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f;
 463         u32 subc = (addr & 0x00070000);
 464         u32 mthd = (addr & 0x00003ffc);
 465         u32 show = stat;
 466
 467         if (stat & 0x00200000) {
 468                 if (mthd == 0x0054) {
 469                         if (!nvc0_fifo_page_flip(dev, chid))
 470                                 show &= ~0x00200000;
 471                 }
 472         }
 473
 474         if (show) {
 475                 NV_INFO(dev, "PFIFO%d:", unit);
 476                 nouveau_bitfield_print(nvc0_fifo_subfifo_intr, show);
 477                 NV_INFO(dev, "PFIFO%d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
 478                              unit, chid, subc, mthd, data);
 479         }
 480
 481         nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008);
 482         nv_wr32(dev, 0x040108 + (unit * 0x2000), stat);
 483 }
 484
 485 static void
 486 nvc0_fifo_isr(struct drm_device *dev)
 487 {
 488         u32 stat = nv_rd32(dev, 0x002100);
 489
 490         if (stat & 0x00000100) {
 491                 NV_INFO(dev, "PFIFO: unknown status 0x00000100\n");
 492                 nv_wr32(dev, 0x002100, 0x00000100);
 493                 stat &= ~0x00000100;
 494         }
 495
 496         if (stat & 0x10000000) {
 497                 u32 units = nv_rd32(dev, 0x00259c);
 498                 u32 u = units;
 499
 500                 while (u) {
 501                         int i = ffs(u) - 1;
 502                         nvc0_fifo_isr_vm_fault(dev, i);
 503                         u &= ~(1 << i);
 504                 }
 505
 506                 nv_wr32(dev, 0x00259c, units);
 507                 stat &= ~0x10000000;
 508         }
 509
 510         if (stat & 0x20000000) {
 511                 u32 units = nv_rd32(dev, 0x0025a0);
 512                 u32 u = units;
 513
 514                 while (u) {
 515                         int i = ffs(u) - 1;
 516                         nvc0_fifo_isr_subfifo_intr(dev, i);
 517                         u &= ~(1 << i);
 518                 }
 519
 520                 nv_wr32(dev, 0x0025a0, units);
 521                 stat &= ~0x20000000;
 522         }
 523
 524         if (stat & 0x40000000) {
 525                 NV_INFO(dev, "PFIFO: unknown status 0x40000000\n");
 526                 nv_mask(dev, 0x002a00, 0x00000000, 0x00000000);
 527                 stat &= ~0x40000000;
 528         }
 529
 530         if (stat) {
 531                 NV_INFO(dev, "PFIFO: unhandled status 0x%08x\n", stat);
 532                 nv_wr32(dev, 0x002100, stat);
 533                 nv_wr32(dev, 0x002140, 0);
 534         }
 535 }