drivers/gpu/drm/nouveau/nv50_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_ramht.h"
  31 #include "nouveau_grctx.h"
  32 #include "nouveau_dma.h"
  33 #include "nouveau_vm.h"
  34 #include "nouveau_ramht.h"
  35 #include "nv50_evo.h"
  36
  37 struct nv50_graph_engine {
  38         struct nouveau_exec_engine base;
  39         u32 ctxprog[512];
  40         u32 ctxprog_size;
  41         u32 grctx_size;
  42 };
  43
  44 static void
  45 nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
  46 {
  47         const uint32_t mask = 0x00010001;
  48
  49         if (enabled)
  50                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
  51         else
  52                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
  53 }
  54
  55 static struct nouveau_channel *
  56 nv50_graph_channel(struct drm_device *dev)
  57 {
  58         struct drm_nouveau_private *dev_priv = dev->dev_private;
  59         uint32_t inst;
  60         int i;
  61
  62         /* Be sure we're not in the middle of a context switch or bad things
  63          * will happen, such as unloading the wrong pgraph context.
  64          */
  65         if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
  66                 NV_ERROR(dev, "Ctxprog is still running\n");
  67
  68         inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
  69         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
  70                 return NULL;
  71         inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
  72
  73         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
  74                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
  75
  76                 if (chan && chan->ramin && chan->ramin->vinst == inst)
  77                         return chan;
  78         }
  79
  80         return NULL;
  81 }
  82
  83 static int
  84 nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
  85 {
  86         uint32_t fifo = nv_rd32(dev, 0x400500);
  87
  88         nv_wr32(dev, 0x400500, fifo & ~1);
  89         nv_wr32(dev, 0x400784, inst);
  90         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
  91         nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
  92         nv_wr32(dev, 0x400040, 0xffffffff);
  93         (void)nv_rd32(dev, 0x400040);
  94         nv_wr32(dev, 0x400040, 0x00000000);
  95         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
  96
  97         if (nouveau_wait_for_idle(dev))
  98                 nv_wr32(dev, 0x40032c, inst | (1<<31));
  99         nv_wr32(dev, 0x400500, fifo);
 100
 101         return 0;
 102 }
 103
 104 static int
 105 nv50_graph_unload_context(struct drm_device *dev)
 106 {
 107         uint32_t inst;
 108
 109         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
 110         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
 111                 return 0;
 112         inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
 113
 114         nouveau_wait_for_idle(dev);
 115         nv_wr32(dev, 0x400784, inst);
 116         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
 117         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
 118         nouveau_wait_for_idle(dev);
 119
 120         nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
 121         return 0;
 122 }
 123
 124 static void
 125 nv50_graph_init_reset(struct drm_device *dev)
 126 {
 127         uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
 128         NV_DEBUG(dev, "\n");
 129
 130         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
 131         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |  pmc_e);
 132 }
 133
 134 static void
 135 nv50_graph_init_intr(struct drm_device *dev)
 136 {
 137         NV_DEBUG(dev, "\n");
 138
 139         nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
 140         nv_wr32(dev, 0x400138, 0xffffffff);
 141         nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
 142 }
 143
 144 static void
 145 nv50_graph_init_regs__nv(struct drm_device *dev)
 146 {
 147         struct drm_nouveau_private *dev_priv = dev->dev_private;
 148         uint32_t units = nv_rd32(dev, 0x1540);
 149         int i;
 150
 151         NV_DEBUG(dev, "\n");
 152
 153         nv_wr32(dev, 0x400804, 0xc0000000);
 154         nv_wr32(dev, 0x406800, 0xc0000000);
 155         nv_wr32(dev, 0x400c04, 0xc0000000);
 156         nv_wr32(dev, 0x401800, 0xc0000000);
 157         nv_wr32(dev, 0x405018, 0xc0000000);
 158         nv_wr32(dev, 0x402000, 0xc0000000);
 159
 160         for (i = 0; i < 16; i++) {
 161                 if (units & 1 << i) {
 162                         if (dev_priv->chipset < 0xa0) {
 163                                 nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
 164                                 nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
 165                                 nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
 166                         } else {
 167                                 nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
 168                                 nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
 169                                 nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
 170                         }
 171                 }
 172         }
 173
 174         nv_wr32(dev, 0x400108, 0xffffffff);
 175
 176         nv_wr32(dev, 0x400824, 0x00004000);
 177         nv_wr32(dev, 0x400500, 0x00010001);
 178 }
 179
 180 static void
 181 nv50_graph_init_zcull(struct drm_device *dev)
 182 {
 183         struct drm_nouveau_private *dev_priv = dev->dev_private;
 184         int i;
 185
 186         NV_DEBUG(dev, "\n");
 187
 188         switch (dev_priv->chipset & 0xf0) {
 189         case 0x50:
 190         case 0x80:
 191         case 0x90:
 192                 nv_wr32(dev, 0x402ca8, 0x00000800);
 193                 break;
 194         case 0xa0:
 195         default:
 196                 nv_wr32(dev, 0x402cc0, 0x00000000);
 197                 if (dev_priv->chipset == 0xa0 ||
 198                     dev_priv->chipset == 0xaa ||
 199                     dev_priv->chipset == 0xac) {
 200                         nv_wr32(dev, 0x402ca8, 0x00000802);
 201                 } else {
 202                         nv_wr32(dev, 0x402cc0, 0x00000000);
 203                         nv_wr32(dev, 0x402ca8, 0x00000002);
 204                 }
 205
 206                 break;
 207         }
 208
 209         /* zero out zcull regions */
 210         for (i = 0; i < 8; i++) {
 211                 nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000);
 212                 nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000);
 213                 nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000);
 214                 nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000);
 215         }
 216 }
 217
 218 static int
 219 nv50_graph_init_ctxctl(struct drm_device *dev)
 220 {
 221         struct nv50_graph_engine *pgraph = nv_engine(dev, NVOBJ_ENGINE_GR);
 222         int i;
 223
 224         NV_DEBUG(dev, "\n");
 225
 226         nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
 227         for (i = 0; i < pgraph->ctxprog_size; i++)
 228                 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, pgraph->ctxprog[i]);
 229
 230         nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
 231         nv_wr32(dev, 0x400320, 4);
 232         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
 233         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
 234         return 0;
 235 }
 236
 237 static int
 238 nv50_graph_init(struct drm_device *dev, int engine)
 239 {
 240         int ret;
 241
 242         NV_DEBUG(dev, "\n");
 243
 244         nv50_graph_init_reset(dev);
 245         nv50_graph_init_regs__nv(dev);
 246         nv50_graph_init_zcull(dev);
 247
 248         ret = nv50_graph_init_ctxctl(dev);
 249         if (ret)
 250                 return ret;
 251
 252         nv50_graph_init_intr(dev);
 253         return 0;
 254 }
 255
 256 static int
 257 nv50_graph_fini(struct drm_device *dev, int engine, bool suspend)
 258 {
 259         nv50_graph_unload_context(dev);
 260         nv_wr32(dev, 0x40013c, 0x00000000);
 261         return 0;
 262 }
 263
 264 static int
 265 nv50_graph_context_new(struct nouveau_channel *chan, int engine)
 266 {
 267         struct drm_device *dev = chan->dev;
 268         struct drm_nouveau_private *dev_priv = dev->dev_private;
 269         struct nouveau_gpuobj *ramin = chan->ramin;
 270         struct nouveau_gpuobj *grctx = NULL;
 271         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
 272         struct nouveau_grctx ctx = {};
 273         int hdr, ret;
 274
 275         NV_DEBUG(dev, "ch%d\n", chan->id);
 276
 277         ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 0,
 278                                  NVOBJ_FLAG_ZERO_ALLOC |
 279                                  NVOBJ_FLAG_ZERO_FREE, &grctx);
 280         if (ret)
 281                 return ret;
 282
 283         hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 284         nv_wo32(ramin, hdr + 0x00, 0x00190002);
 285         nv_wo32(ramin, hdr + 0x04, grctx->vinst + grctx->size - 1);
 286         nv_wo32(ramin, hdr + 0x08, grctx->vinst);
 287         nv_wo32(ramin, hdr + 0x0c, 0);
 288         nv_wo32(ramin, hdr + 0x10, 0);
 289         nv_wo32(ramin, hdr + 0x14, 0x00010000);
 290
 291         ctx.dev = chan->dev;
 292         ctx.mode = NOUVEAU_GRCTX_VALS;
 293         ctx.data = grctx;
 294         nv50_grctx_init(&ctx);
 295
 296         nv_wo32(grctx, 0x00000, chan->ramin->vinst >> 12);
 297
 298         dev_priv->engine.instmem.flush(dev);
 299
 300         atomic_inc(&chan->vm->engref[NVOBJ_ENGINE_GR]);
 301         chan->engctx[NVOBJ_ENGINE_GR] = grctx;
 302         return 0;
 303 }
 304
 305 static void
 306 nv50_graph_context_del(struct nouveau_channel *chan, int engine)
 307 {
 308         struct nouveau_gpuobj *grctx = chan->engctx[engine];
 309         struct drm_device *dev = chan->dev;
 310         struct drm_nouveau_private *dev_priv = dev->dev_private;
 311         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 312         int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 313         unsigned long flags;
 314
 315         NV_DEBUG(dev, "ch%d\n", chan->id);
 316
 317         if (!chan->ramin)
 318                 return;
 319
 320         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 321         pfifo->reassign(dev, false);
 322         nv50_graph_fifo_access(dev, false);
 323
 324         if (nv50_graph_channel(dev) == chan)
 325                 nv50_graph_unload_context(dev);
 326
 327         for (i = hdr; i < hdr + 24; i += 4)
 328                 nv_wo32(chan->ramin, i, 0);
 329         dev_priv->engine.instmem.flush(dev);
 330
 331         nv50_graph_fifo_access(dev, true);
 332         pfifo->reassign(dev, true);
 333         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 334
 335         nouveau_gpuobj_ref(NULL, &grctx);
 336
 337         atomic_dec(&chan->vm->engref[engine]);
 338         chan->engctx[engine] = NULL;
 339 }
 340
 341 static int
 342 nv50_graph_object_new(struct nouveau_channel *chan, int engine,
 343                       u32 handle, u16 class)
 344 {
 345         struct drm_device *dev = chan->dev;
 346         struct drm_nouveau_private *dev_priv = dev->dev_private;
 347         struct nouveau_gpuobj *obj = NULL;
 348         int ret;
 349
 350         ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
 351         if (ret)
 352                 return ret;
 353         obj->engine = 1;
 354         obj->class  = class;
 355
 356         nv_wo32(obj, 0x00, class);
 357         nv_wo32(obj, 0x04, 0x00000000);
 358         nv_wo32(obj, 0x08, 0x00000000);
 359         nv_wo32(obj, 0x0c, 0x00000000);
 360         dev_priv->engine.instmem.flush(dev);
 361
 362         ret = nouveau_ramht_insert(chan, handle, obj);
 363         nouveau_gpuobj_ref(NULL, &obj);
 364         return ret;
 365 }
 366
 367 static void
 368 nv50_graph_context_switch(struct drm_device *dev)
 369 {
 370         uint32_t inst;
 371
 372         nv50_graph_unload_context(dev);
 373
 374         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
 375         inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
 376         nv50_graph_do_load_context(dev, inst);
 377
 378         nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
 379                 NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
 380 }
 381
 382 static int
 383 nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan,
 384                            u32 class, u32 mthd, u32 data)
 385 {
 386         struct nouveau_gpuobj *gpuobj;
 387
 388         gpuobj = nouveau_ramht_find(chan, data);
 389         if (!gpuobj)
 390                 return -ENOENT;
 391
 392         if (nouveau_notifier_offset(gpuobj, NULL))
 393                 return -EINVAL;
 394
 395         chan->nvsw.vblsem = gpuobj;
 396         chan->nvsw.vblsem_offset = ~0;
 397         return 0;
 398 }
 399
 400 static int
 401 nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan,
 402                               u32 class, u32 mthd, u32 data)
 403 {
 404         if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
 405                 return -ERANGE;
 406
 407         chan->nvsw.vblsem_offset = data >> 2;
 408         return 0;
 409 }
 410
 411 static int
 412 nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan,
 413                                    u32 class, u32 mthd, u32 data)
 414 {
 415         chan->nvsw.vblsem_rval = data;
 416         return 0;
 417 }
 418
 419 static int
 420 nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan,
 421                                u32 class, u32 mthd, u32 data)
 422 {
 423         struct drm_device *dev = chan->dev;
 424         struct drm_nouveau_private *dev_priv = dev->dev_private;
 425
 426         if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
 427                 return -EINVAL;
 428
 429         drm_vblank_get(dev, data);
 430
 431         chan->nvsw.vblsem_head = data;
 432         list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
 433
 434         return 0;
 435 }
 436
 437 static int
 438 nv50_graph_nvsw_mthd_page_flip(struct nouveau_channel *chan,
 439                                u32 class, u32 mthd, u32 data)
 440 {
 441         nouveau_finish_page_flip(chan, NULL);
 442         return 0;
 443 }
 444
 445
 446 static void
 447 nv50_graph_tlb_flush(struct drm_device *dev, int engine)
 448 {
 449         nv50_vm_flush_engine(dev, 0);
 450 }
 451
 452 static void
 453 nv84_graph_tlb_flush(struct drm_device *dev, int engine)
 454 {
 455         struct drm_nouveau_private *dev_priv = dev->dev_private;
 456         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 457         bool idle, timeout = false;
 458         unsigned long flags;
 459         u64 start;
 460         u32 tmp;
 461
 462         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 463         nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
 464
 465         start = ptimer->read(dev);
 466         do {
 467                 idle = true;
 468
 469                 for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
 470                         if ((tmp & 7) == 1)
 471                                 idle = false;
 472                 }
 473
 474                 for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
 475                         if ((tmp & 7) == 1)
 476                                 idle = false;
 477                 }
 478
 479                 for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
 480                         if ((tmp & 7) == 1)
 481                                 idle = false;
 482                 }
 483         } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
 484
 485         if (timeout) {
 486                 NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
 487                               "0x%08x 0x%08x 0x%08x 0x%08x\n",
 488                          nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
 489                          nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
 490         }
 491
 492         nv50_vm_flush_engine(dev, 0);
 493
 494         nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
 495         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 496 }
 497
 498 static struct nouveau_enum nv50_mp_exec_error_names[] = {
 499         { 3, "STACK_UNDERFLOW", NULL },
 500         { 4, "QUADON_ACTIVE", NULL },
 501         { 8, "TIMEOUT", NULL },
 502         { 0x10, "INVALID_OPCODE", NULL },
 503         { 0x40, "BREAKPOINT", NULL },
 504         {}
 505 };
 506
 507 static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
 508         { 0x00000001, "NOTIFY" },
 509         { 0x00000002, "IN" },
 510         { 0x00000004, "OUT" },
 511         {}
 512 };
 513
 514 static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
 515         { 0x00000001, "FAULT" },
 516         {}
 517 };
 518
 519 static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
 520         { 0x00000001, "FAULT" },
 521         {}
 522 };
 523
 524 static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
 525         { 0x00000001, "FAULT" },
 526         {}
 527 };
 528
 529 /* There must be a *lot* of these. Will take some time to gather them up. */
 530 struct nouveau_enum nv50_data_error_names[] = {
 531         { 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL },
 532         { 0x00000004, "INVALID_VALUE", NULL },
 533         { 0x00000005, "INVALID_ENUM", NULL },
 534         { 0x00000008, "INVALID_OBJECT", NULL },
 535         { 0x00000009, "READ_ONLY_OBJECT", NULL },
 536         { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
 537         { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
 538         { 0x0000000c, "INVALID_BITFIELD", NULL },
 539         { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
 540         { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
 541         { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
 542         { 0x00000010, "RT_DOUBLE_BIND", NULL },
 543         { 0x00000011, "RT_TYPES_MISMATCH", NULL },
 544         { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
 545         { 0x00000015, "FP_TOO_FEW_REGS", NULL },
 546         { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
 547         { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
 548         { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
 549         { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
 550         { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
 551         { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
 552         { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
 553         { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
 554         { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
 555         { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
 556         { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
 557         { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
 558         { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
 559         { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
 560         { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
 561         { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
 562         { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
 563         { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
 564         { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
 565         { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
 566         { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
 567         { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
 568         { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
 569         { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
 570         { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
 571         { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
 572         {}
 573 };
 574
 575 static struct nouveau_bitfield nv50_graph_intr[] = {
 576         { 0x00000001, "NOTIFY" },
 577         { 0x00000002, "COMPUTE_QUERY" },
 578         { 0x00000010, "ILLEGAL_MTHD" },
 579         { 0x00000020, "ILLEGAL_CLASS" },
 580         { 0x00000040, "DOUBLE_NOTIFY" },
 581         { 0x00001000, "CONTEXT_SWITCH" },
 582         { 0x00010000, "BUFFER_NOTIFY" },
 583         { 0x00100000, "DATA_ERROR" },
 584         { 0x00200000, "TRAP" },
 585         { 0x01000000, "SINGLE_STEP" },
 586         {}
 587 };
 588
 589 static void
 590 nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
 591 {
 592         struct drm_nouveau_private *dev_priv = dev->dev_private;
 593         uint32_t units = nv_rd32(dev, 0x1540);
 594         uint32_t addr, mp10, status, pc, oplow, ophigh;
 595         int i;
 596         int mps = 0;
 597         for (i = 0; i < 4; i++) {
 598                 if (!(units & 1 << (i+24)))
 599                         continue;
 600                 if (dev_priv->chipset < 0xa0)
 601                         addr = 0x408200 + (tpid << 12) + (i << 7);
 602                 else
 603                         addr = 0x408100 + (tpid << 11) + (i << 7);
 604                 mp10 = nv_rd32(dev, addr + 0x10);
 605                 status = nv_rd32(dev, addr + 0x14);
 606                 if (!status)
 607                         continue;
 608                 if (display) {
 609                         nv_rd32(dev, addr + 0x20);
 610                         pc = nv_rd32(dev, addr + 0x24);
 611                         oplow = nv_rd32(dev, addr + 0x70);
 612                         ophigh = nv_rd32(dev, addr + 0x74);
 613                         NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
 614                                         "TP %d MP %d: ", tpid, i);
 615                         nouveau_enum_print(nv50_mp_exec_error_names, status);
 616                         printk(" at %06x warp %d, opcode %08x %08x\n",
 617                                         pc&0xffffff, pc >> 24,
 618                                         oplow, ophigh);
 619                 }
 620                 nv_wr32(dev, addr + 0x10, mp10);
 621                 nv_wr32(dev, addr + 0x14, 0);
 622                 mps++;
 623         }
 624         if (!mps && display)
 625                 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
 626                                 "No MPs claiming errors?\n", tpid);
 627 }
 628
 629 static void
 630 nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
 631                 uint32_t ustatus_new, int display, const char *name)
 632 {
 633         struct drm_nouveau_private *dev_priv = dev->dev_private;
 634         int tps = 0;
 635         uint32_t units = nv_rd32(dev, 0x1540);
 636         int i, r;
 637         uint32_t ustatus_addr, ustatus;
 638         for (i = 0; i < 16; i++) {
 639                 if (!(units & (1 << i)))
 640                         continue;
 641                 if (dev_priv->chipset < 0xa0)
 642                         ustatus_addr = ustatus_old + (i << 12);
 643                 else
 644                         ustatus_addr = ustatus_new + (i << 11);
 645                 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
 646                 if (!ustatus)
 647                         continue;
 648                 tps++;
 649                 switch (type) {
 650                 case 6: /* texture error... unknown for now */
 651                         if (display) {
 652                                 NV_ERROR(dev, "magic set %d:\n", i);
 653                                 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
 654                                         NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
 655                                                 nv_rd32(dev, r));
 656                         }
 657                         break;
 658                 case 7: /* MP error */
 659                         if (ustatus & 0x00010000) {
 660                                 nv50_pgraph_mp_trap(dev, i, display);
 661                                 ustatus &= ~0x00010000;
 662                         }
 663                         break;
 664                 case 8: /* TPDMA error */
 665                         {
 666                         uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
 667                         uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
 668                         uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
 669                         uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
 670                         uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
 671                         uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
 672                         uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
 673                         /* 2d engine destination */
 674                         if (ustatus & 0x00000010) {
 675                                 if (display) {
 676                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
 677                                                         i, e14, e10);
 678                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 679                                                         i, e0c, e18, e1c, e20, e24);
 680                                 }
 681                                 ustatus &= ~0x00000010;
 682                         }
 683                         /* Render target */
 684                         if (ustatus & 0x00000040) {
 685                                 if (display) {
 686                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
 687                                                         i, e14, e10);
 688                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 689                                                         i, e0c, e18, e1c, e20, e24);
 690                                 }
 691                                 ustatus &= ~0x00000040;
 692                         }
 693                         /* CUDA memory: l[], g[] or stack. */
 694                         if (ustatus & 0x00000080) {
 695                                 if (display) {
 696                                         if (e18 & 0x80000000) {
 697                                                 /* g[] read fault? */
 698                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
 699                                                                 i, e14, e10 | ((e18 >> 24) & 0x1f));
 700                                                 e18 &= ~0x1f000000;
 701                                         } else if (e18 & 0xc) {
 702                                                 /* g[] write fault? */
 703                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
 704                                                                 i, e14, e10 | ((e18 >> 7) & 0x1f));
 705                                                 e18 &= ~0x00000f80;
 706                                         } else {
 707                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
 708                                                                 i, e14, e10);
 709                                         }
 710                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 711                                                         i, e0c, e18, e1c, e20, e24);
 712                                 }
 713                                 ustatus &= ~0x00000080;
 714                         }
 715                         }
 716                         break;
 717                 }
 718                 if (ustatus) {
 719                         if (display)
 720                                 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
 721                 }
 722                 nv_wr32(dev, ustatus_addr, 0xc0000000);
 723         }
 724
 725         if (!tps && display)
 726                 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
 727 }
 728
 729 static int
 730 nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
 731 {
 732         u32 status = nv_rd32(dev, 0x400108);
 733         u32 ustatus;
 734
 735         if (!status && display) {
 736                 NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
 737                 return 1;
 738         }
 739
 740         /* DISPATCH: Relays commands to other units and handles NOTIFY,
 741          * COND, QUERY. If you get a trap from it, the command is still stuck
 742          * in DISPATCH and you need to do something about it. */
 743         if (status & 0x001) {
 744                 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
 745                 if (!ustatus && display) {
 746                         NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
 747                 }
 748
 749                 nv_wr32(dev, 0x400500, 0x00000000);
 750
 751                 /* Known to be triggered by screwed up NOTIFY and COND... */
 752                 if (ustatus & 0x00000001) {
 753                         u32 addr = nv_rd32(dev, 0x400808);
 754                         u32 subc = (addr & 0x00070000) >> 16;
 755                         u32 mthd = (addr & 0x00001ffc);
 756                         u32 datal = nv_rd32(dev, 0x40080c);
 757                         u32 datah = nv_rd32(dev, 0x400810);
 758                         u32 class = nv_rd32(dev, 0x400814);
 759                         u32 r848 = nv_rd32(dev, 0x400848);
 760
 761                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
 762                         if (display && (addr & 0x80000000)) {
 763                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 764                                              "subc %d class 0x%04x mthd 0x%04x "
 765                                              "data 0x%08x%08x "
 766                                              "400808 0x%08x 400848 0x%08x\n",
 767                                         chid, inst, subc, class, mthd, datah,
 768                                         datal, addr, r848);
 769                         } else
 770                         if (display) {
 771                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 772                         }
 773
 774                         nv_wr32(dev, 0x400808, 0);
 775                         nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
 776                         nv_wr32(dev, 0x400848, 0);
 777                         ustatus &= ~0x00000001;
 778                 }
 779
 780                 if (ustatus & 0x00000002) {
 781                         u32 addr = nv_rd32(dev, 0x40084c);
 782                         u32 subc = (addr & 0x00070000) >> 16;
 783                         u32 mthd = (addr & 0x00001ffc);
 784                         u32 data = nv_rd32(dev, 0x40085c);
 785                         u32 class = nv_rd32(dev, 0x400814);
 786
 787                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
 788                         if (display && (addr & 0x80000000)) {
 789                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 790                                              "subc %d class 0x%04x mthd 0x%04x "
 791                                              "data 0x%08x 40084c 0x%08x\n",
 792                                         chid, inst, subc, class, mthd,
 793                                         data, addr);
 794                         } else
 795                         if (display) {
 796                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 797                         }
 798
 799                         nv_wr32(dev, 0x40084c, 0);
 800                         ustatus &= ~0x00000002;
 801                 }
 802
 803                 if (ustatus && display) {
 804                         NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
 805                                       "0x%08x)\n", ustatus);
 806                 }
 807
 808                 nv_wr32(dev, 0x400804, 0xc0000000);
 809                 nv_wr32(dev, 0x400108, 0x001);
 810                 status &= ~0x001;
 811                 if (!status)
 812                         return 0;
 813         }
 814
 815         /* M2MF: Memory to memory copy engine. */
 816         if (status & 0x002) {
 817                 u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
 818                 if (display) {
 819                         NV_INFO(dev, "PGRAPH - TRAP_M2MF");
 820                         nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
 821                         printk("\n");
 822                         NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
 823                                 nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
 824                                 nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
 825
 826                 }
 827
 828                 /* No sane way found yet -- just reset the bugger. */
 829                 nv_wr32(dev, 0x400040, 2);
 830                 nv_wr32(dev, 0x400040, 0);
 831                 nv_wr32(dev, 0x406800, 0xc0000000);
 832                 nv_wr32(dev, 0x400108, 0x002);
 833                 status &= ~0x002;
 834         }
 835
 836         /* VFETCH: Fetches data from vertex buffers. */
 837         if (status & 0x004) {
 838                 u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
 839                 if (display) {
 840                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
 841                         nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
 842                         printk("\n");
 843                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
 844                                 nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
 845                                 nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
 846                 }
 847
 848                 nv_wr32(dev, 0x400c04, 0xc0000000);
 849                 nv_wr32(dev, 0x400108, 0x004);
 850                 status &= ~0x004;
 851         }
 852
 853         /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
 854         if (status & 0x008) {
 855                 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
 856                 if (display) {
 857                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
 858                         nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
 859                         printk("\n");
 860                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
 861                                 nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
 862                                 nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
 863
 864                 }
 865
 866                 /* No sane way found yet -- just reset the bugger. */
 867                 nv_wr32(dev, 0x400040, 0x80);
 868                 nv_wr32(dev, 0x400040, 0);
 869                 nv_wr32(dev, 0x401800, 0xc0000000);
 870                 nv_wr32(dev, 0x400108, 0x008);
 871                 status &= ~0x008;
 872         }
 873
 874         /* CCACHE: Handles code and c[] caches and fills them. */
 875         if (status & 0x010) {
 876                 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
 877                 if (display) {
 878                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
 879                         nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
 880                         printk("\n");
 881                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
 882                                      " %08x %08x %08x\n",
 883                                 nv_rd32(dev, 0x405000), nv_rd32(dev, 0x405004),
 884                                 nv_rd32(dev, 0x405008), nv_rd32(dev, 0x40500c),
 885                                 nv_rd32(dev, 0x405010), nv_rd32(dev, 0x405014),
 886                                 nv_rd32(dev, 0x40501c));
 887
 888                 }
 889
 890                 nv_wr32(dev, 0x405018, 0xc0000000);
 891                 nv_wr32(dev, 0x400108, 0x010);
 892                 status &= ~0x010;
 893         }
 894
 895         /* Unknown, not seen yet... 0x402000 is the only trap status reg
 896          * remaining, so try to handle it anyway. Perhaps related to that
 897          * unknown DMA slot on tesla? */
 898         if (status & 0x20) {
 899                 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
 900                 if (display)
 901                         NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
 902                 nv_wr32(dev, 0x402000, 0xc0000000);
 903                 /* no status modifiction on purpose */
 904         }
 905
 906         /* TEXTURE: CUDA texturing units */
 907         if (status & 0x040) {
 908                 nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
 909                                     "PGRAPH - TRAP_TEXTURE");
 910                 nv_wr32(dev, 0x400108, 0x040);
 911                 status &= ~0x040;
 912         }
 913
 914         /* MP: CUDA execution engines. */
 915         if (status & 0x080) {
 916                 nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
 917                                     "PGRAPH - TRAP_MP");
 918                 nv_wr32(dev, 0x400108, 0x080);
 919                 status &= ~0x080;
 920         }
 921
 922         /* TPDMA:  Handles TP-initiated uncached memory accesses:
 923          * l[], g[], stack, 2d surfaces, render targets. */
 924         if (status & 0x100) {
 925                 nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
 926                                     "PGRAPH - TRAP_TPDMA");
 927                 nv_wr32(dev, 0x400108, 0x100);
 928                 status &= ~0x100;
 929         }
 930
 931         if (status) {
 932                 if (display)
 933                         NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
 934                 nv_wr32(dev, 0x400108, status);
 935         }
 936
 937         return 1;
 938 }
 939
 940 int
 941 nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
 942 {
 943         struct drm_nouveau_private *dev_priv = dev->dev_private;
 944         struct nouveau_channel *chan;
 945         unsigned long flags;
 946         int i;
 947
 948         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 949         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 950                 chan = dev_priv->channels.ptr[i];
 951                 if (!chan || !chan->ramin)
 952                         continue;
 953
 954                 if (inst == chan->ramin->vinst)
 955                         break;
 956         }
 957         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 958         return i;
 959 }
 960
 961 static void
 962 nv50_graph_isr(struct drm_device *dev)
 963 {
 964         u32 stat;
 965
 966         while ((stat = nv_rd32(dev, 0x400100))) {
 967                 u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
 968                 u32 chid = nv50_graph_isr_chid(dev, inst);
 969                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
 970                 u32 subc = (addr & 0x00070000) >> 16;
 971                 u32 mthd = (addr & 0x00001ffc);
 972                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
 973                 u32 class = nv_rd32(dev, 0x400814);
 974                 u32 show = stat;
 975
 976                 if (stat & 0x00000010) {
 977                         if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
 978                                                        mthd, data))
 979                                 show &= ~0x00000010;
 980                 }
 981
 982                 if (stat & 0x00001000) {
 983                         nv_wr32(dev, 0x400500, 0x00000000);
 984                         nv_wr32(dev, 0x400100, 0x00001000);
 985                         nv_mask(dev, 0x40013c, 0x00001000, 0x00000000);
 986                         nv50_graph_context_switch(dev);
 987                         stat &= ~0x00001000;
 988                         show &= ~0x00001000;
 989                 }
 990
 991                 show = (show && nouveau_ratelimit()) ? show : 0;
 992
 993                 if (show & 0x00100000) {
 994                         u32 ecode = nv_rd32(dev, 0x400110);
 995                         NV_INFO(dev, "PGRAPH - DATA_ERROR ");
 996                         nouveau_enum_print(nv50_data_error_names, ecode);
 997                         printk("\n");
 998                 }
 999
1000                 if (stat & 0x00200000) {
1001                         if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
1002                                 show &= ~0x00200000;
1003                 }
1004
1005                 nv_wr32(dev, 0x400100, stat);
1006                 nv_wr32(dev, 0x400500, 0x00010001);
1007
1008                 if (show) {
1009                         NV_INFO(dev, "PGRAPH -");
1010                         nouveau_bitfield_print(nv50_graph_intr, show);
1011                         printk("\n");
1012                         NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
1013                                      "class 0x%04x mthd 0x%04x data 0x%08x\n",
1014                                 chid, inst, subc, class, mthd, data);
1015                         nv50_fb_vm_trap(dev, 1);
1016                 }
1017         }
1018
1019         if (nv_rd32(dev, 0x400824) & (1 << 31))
1020                 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
1021 }
1022
1023 static void
1024 nv50_graph_destroy(struct drm_device *dev, int engine)
1025 {
1026         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
1027
1028         NVOBJ_ENGINE_DEL(dev, GR);
1029
1030         nouveau_irq_unregister(dev, 12);
1031         kfree(pgraph);
1032 }
1033
1034 int
1035 nv50_graph_create(struct drm_device *dev)
1036 {
1037         struct drm_nouveau_private *dev_priv = dev->dev_private;
1038         struct nv50_graph_engine *pgraph;
1039         struct nouveau_grctx ctx = {};
1040         int ret;
1041
1042         pgraph = kzalloc(sizeof(*pgraph),GFP_KERNEL);
1043         if (!pgraph)
1044                 return -ENOMEM;
1045
1046         ctx.dev = dev;
1047         ctx.mode = NOUVEAU_GRCTX_PROG;
1048         ctx.data = pgraph->ctxprog;
1049         ctx.ctxprog_max = ARRAY_SIZE(pgraph->ctxprog);
1050
1051         ret = nv50_grctx_init(&ctx);
1052         if (ret) {
1053                 NV_ERROR(dev, "PGRAPH: ctxprog build failed\n");
1054                 kfree(pgraph);
1055                 return 0;
1056         }
1057
1058         pgraph->grctx_size = ctx.ctxvals_pos * 4;
1059         pgraph->ctxprog_size = ctx.ctxprog_len;
1060
1061         pgraph->base.destroy = nv50_graph_destroy;
1062         pgraph->base.init = nv50_graph_init;
1063         pgraph->base.fini = nv50_graph_fini;
1064         pgraph->base.context_new = nv50_graph_context_new;
1065         pgraph->base.context_del = nv50_graph_context_del;
1066         pgraph->base.object_new = nv50_graph_object_new;
1067         if (dev_priv->chipset == 0x50 || dev_priv->chipset == 0xac)
1068                 pgraph->base.tlb_flush = nv50_graph_tlb_flush;
1069         else
1070                 pgraph->base.tlb_flush = nv84_graph_tlb_flush;
1071
1072         nouveau_irq_register(dev, 12, nv50_graph_isr);
1073
1074         /* NVSW really doesn't live here... */
1075         NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
1076         NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
1077         NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
1078         NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
1079         NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
1080         NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip);
1081
1082         NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
1083         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
1084         NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
1085         NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
1086
1087         /* tesla */
1088         if (dev_priv->chipset == 0x50)
1089                 NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
1090         else
1091         if (dev_priv->chipset < 0xa0)
1092                 NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
1093         else {
1094                 switch (dev_priv->chipset) {
1095                 case 0xa0:
1096                 case 0xaa:
1097                 case 0xac:
1098                         NVOBJ_CLASS(dev, 0x8397, GR);
1099                         break;
1100                 case 0xa3:
1101                 case 0xa5:
1102                 case 0xa8:
1103                         NVOBJ_CLASS(dev, 0x8597, GR);
1104                         break;
1105                 case 0xaf:
1106                         NVOBJ_CLASS(dev, 0x8697, GR);
1107                         break;
1108                 }
1109         }
1110
1111         /* compute */
1112         NVOBJ_CLASS(dev, 0x50c0, GR);
1113         if (dev_priv->chipset  > 0xa0 &&
1114             dev_priv->chipset != 0xaa &&
1115             dev_priv->chipset != 0xac)
1116                 NVOBJ_CLASS(dev, 0x85c0, GR);
1117
1118         return 0;
1119 }