drivers/gpu/drm/nouveau/nv50_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_ramht.h"
  31 #include "nouveau_dma.h"
  32 #include "nouveau_vm.h"
  33 #include "nv50_evo.h"
  34
  35 struct nv50_graph_engine {
  36         struct nouveau_exec_engine base;
  37         u32 ctxprog[512];
  38         u32 ctxprog_size;
  39         u32 grctx_size;
  40 };
  41
  42 static void
  43 nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
  44 {
  45         const uint32_t mask = 0x00010001;
  46
  47         if (enabled)
  48                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
  49         else
  50                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
  51 }
  52
  53 static struct nouveau_channel *
  54 nv50_graph_channel(struct drm_device *dev)
  55 {
  56         struct drm_nouveau_private *dev_priv = dev->dev_private;
  57         uint32_t inst;
  58         int i;
  59
  60         /* Be sure we're not in the middle of a context switch or bad things
  61          * will happen, such as unloading the wrong pgraph context.
  62          */
  63         if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
  64                 NV_ERROR(dev, "Ctxprog is still running\n");
  65
  66         inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
  67         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
  68                 return NULL;
  69         inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
  70
  71         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
  72                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
  73
  74                 if (chan && chan->ramin && chan->ramin->vinst == inst)
  75                         return chan;
  76         }
  77
  78         return NULL;
  79 }
  80
  81 static int
  82 nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
  83 {
  84         uint32_t fifo = nv_rd32(dev, 0x400500);
  85
  86         nv_wr32(dev, 0x400500, fifo & ~1);
  87         nv_wr32(dev, 0x400784, inst);
  88         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
  89         nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
  90         nv_wr32(dev, 0x400040, 0xffffffff);
  91         (void)nv_rd32(dev, 0x400040);
  92         nv_wr32(dev, 0x400040, 0x00000000);
  93         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
  94
  95         if (nouveau_wait_for_idle(dev))
  96                 nv_wr32(dev, 0x40032c, inst | (1<<31));
  97         nv_wr32(dev, 0x400500, fifo);
  98
  99         return 0;
 100 }
 101
 102 static int
 103 nv50_graph_unload_context(struct drm_device *dev)
 104 {
 105         uint32_t inst;
 106
 107         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
 108         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
 109                 return 0;
 110         inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
 111
 112         nouveau_wait_for_idle(dev);
 113         nv_wr32(dev, 0x400784, inst);
 114         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
 115         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
 116         nouveau_wait_for_idle(dev);
 117
 118         nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
 119         return 0;
 120 }
 121
 122 static int
 123 nv50_graph_init(struct drm_device *dev, int engine)
 124 {
 125         struct drm_nouveau_private *dev_priv = dev->dev_private;
 126         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
 127         u32 units = nv_rd32(dev, 0x001540);
 128         int i;
 129
 130         NV_DEBUG(dev, "\n");
 131
 132         /* master reset */
 133         nv_mask(dev, 0x000200, 0x00201000, 0x00000000);
 134         nv_mask(dev, 0x000200, 0x00201000, 0x00201000);
 135         nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
 136
 137         /* reset/enable traps and interrupts */
 138         nv_wr32(dev, 0x400804, 0xc0000000);
 139         nv_wr32(dev, 0x406800, 0xc0000000);
 140         nv_wr32(dev, 0x400c04, 0xc0000000);
 141         nv_wr32(dev, 0x401800, 0xc0000000);
 142         nv_wr32(dev, 0x405018, 0xc0000000);
 143         nv_wr32(dev, 0x402000, 0xc0000000);
 144         for (i = 0; i < 16; i++) {
 145                 if (!(units & (1 << i)))
 146                         continue;
 147
 148                 if (dev_priv->chipset < 0xa0) {
 149                         nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
 150                         nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
 151                         nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
 152                 } else {
 153                         nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
 154                         nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
 155                         nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
 156                 }
 157         }
 158
 159         nv_wr32(dev, 0x400108, 0xffffffff);
 160         nv_wr32(dev, 0x400138, 0xffffffff);
 161         nv_wr32(dev, 0x400100, 0xffffffff);
 162         nv_wr32(dev, 0x40013c, 0xffffffff);
 163         nv_wr32(dev, 0x400500, 0x00010001);
 164
 165         /* upload context program, initialise ctxctl defaults */
 166         nv_wr32(dev, 0x400324, 0x00000000);
 167         for (i = 0; i < pgraph->ctxprog_size; i++)
 168                 nv_wr32(dev, 0x400328, pgraph->ctxprog[i]);
 169         nv_wr32(dev, 0x400824, 0x00000000);
 170         nv_wr32(dev, 0x400828, 0x00000000);
 171         nv_wr32(dev, 0x40082c, 0x00000000);
 172         nv_wr32(dev, 0x400830, 0x00000000);
 173         nv_wr32(dev, 0x400724, 0x00000000);
 174         nv_wr32(dev, 0x40032c, 0x00000000);
 175         nv_wr32(dev, 0x400320, 4);      /* CTXCTL_CMD = NEWCTXDMA */
 176
 177         /* some unknown zcull magic */
 178         switch (dev_priv->chipset & 0xf0) {
 179         case 0x50:
 180         case 0x80:
 181         case 0x90:
 182                 nv_wr32(dev, 0x402ca8, 0x00000800);
 183                 break;
 184         case 0xa0:
 185         default:
 186                 nv_wr32(dev, 0x402cc0, 0x00000000);
 187                 if (dev_priv->chipset == 0xa0 ||
 188                     dev_priv->chipset == 0xaa ||
 189                     dev_priv->chipset == 0xac) {
 190                         nv_wr32(dev, 0x402ca8, 0x00000802);
 191                 } else {
 192                         nv_wr32(dev, 0x402cc0, 0x00000000);
 193                         nv_wr32(dev, 0x402ca8, 0x00000002);
 194                 }
 195
 196                 break;
 197         }
 198
 199         /* zero out zcull regions */
 200         for (i = 0; i < 8; i++) {
 201                 nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000);
 202                 nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000);
 203                 nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000);
 204                 nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000);
 205         }
 206
 207         return 0;
 208 }
 209
 210 static int
 211 nv50_graph_fini(struct drm_device *dev, int engine, bool suspend)
 212 {
 213         nv_mask(dev, 0x400500, 0x00010001, 0x00000000);
 214         if (!nv_wait(dev, 0x400700, ~0, 0) && suspend) {
 215                 nv_mask(dev, 0x400500, 0x00010001, 0x00010001);
 216                 return -EBUSY;
 217         }
 218         nv50_graph_unload_context(dev);
 219         nv_wr32(dev, 0x40013c, 0x00000000);
 220         return 0;
 221 }
 222
 223 static int
 224 nv50_graph_context_new(struct nouveau_channel *chan, int engine)
 225 {
 226         struct drm_device *dev = chan->dev;
 227         struct drm_nouveau_private *dev_priv = dev->dev_private;
 228         struct nouveau_gpuobj *ramin = chan->ramin;
 229         struct nouveau_gpuobj *grctx = NULL;
 230         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
 231         int hdr, ret;
 232
 233         NV_DEBUG(dev, "ch%d\n", chan->id);
 234
 235         ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 0,
 236                                  NVOBJ_FLAG_ZERO_ALLOC |
 237                                  NVOBJ_FLAG_ZERO_FREE, &grctx);
 238         if (ret)
 239                 return ret;
 240
 241         hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 242         nv_wo32(ramin, hdr + 0x00, 0x00190002);
 243         nv_wo32(ramin, hdr + 0x04, grctx->vinst + grctx->size - 1);
 244         nv_wo32(ramin, hdr + 0x08, grctx->vinst);
 245         nv_wo32(ramin, hdr + 0x0c, 0);
 246         nv_wo32(ramin, hdr + 0x10, 0);
 247         nv_wo32(ramin, hdr + 0x14, 0x00010000);
 248
 249         nv50_grctx_fill(dev, grctx);
 250         nv_wo32(grctx, 0x00000, chan->ramin->vinst >> 12);
 251
 252         dev_priv->engine.instmem.flush(dev);
 253
 254         atomic_inc(&chan->vm->engref[NVOBJ_ENGINE_GR]);
 255         chan->engctx[NVOBJ_ENGINE_GR] = grctx;
 256         return 0;
 257 }
 258
 259 static void
 260 nv50_graph_context_del(struct nouveau_channel *chan, int engine)
 261 {
 262         struct nouveau_gpuobj *grctx = chan->engctx[engine];
 263         struct drm_device *dev = chan->dev;
 264         struct drm_nouveau_private *dev_priv = dev->dev_private;
 265         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 266         int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 267         unsigned long flags;
 268
 269         NV_DEBUG(dev, "ch%d\n", chan->id);
 270
 271         if (!chan->ramin)
 272                 return;
 273
 274         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 275         pfifo->reassign(dev, false);
 276         nv50_graph_fifo_access(dev, false);
 277
 278         if (nv50_graph_channel(dev) == chan)
 279                 nv50_graph_unload_context(dev);
 280
 281         for (i = hdr; i < hdr + 24; i += 4)
 282                 nv_wo32(chan->ramin, i, 0);
 283         dev_priv->engine.instmem.flush(dev);
 284
 285         nv50_graph_fifo_access(dev, true);
 286         pfifo->reassign(dev, true);
 287         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 288
 289         nouveau_gpuobj_ref(NULL, &grctx);
 290
 291         atomic_dec(&chan->vm->engref[engine]);
 292         chan->engctx[engine] = NULL;
 293 }
 294
 295 static int
 296 nv50_graph_object_new(struct nouveau_channel *chan, int engine,
 297                       u32 handle, u16 class)
 298 {
 299         struct drm_device *dev = chan->dev;
 300         struct drm_nouveau_private *dev_priv = dev->dev_private;
 301         struct nouveau_gpuobj *obj = NULL;
 302         int ret;
 303
 304         ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
 305         if (ret)
 306                 return ret;
 307         obj->engine = 1;
 308         obj->class  = class;
 309
 310         nv_wo32(obj, 0x00, class);
 311         nv_wo32(obj, 0x04, 0x00000000);
 312         nv_wo32(obj, 0x08, 0x00000000);
 313         nv_wo32(obj, 0x0c, 0x00000000);
 314         dev_priv->engine.instmem.flush(dev);
 315
 316         ret = nouveau_ramht_insert(chan, handle, obj);
 317         nouveau_gpuobj_ref(NULL, &obj);
 318         return ret;
 319 }
 320
 321 static void
 322 nv50_graph_context_switch(struct drm_device *dev)
 323 {
 324         uint32_t inst;
 325
 326         nv50_graph_unload_context(dev);
 327
 328         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
 329         inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
 330         nv50_graph_do_load_context(dev, inst);
 331
 332         nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
 333                 NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
 334 }
 335
 336 static void
 337 nv50_graph_tlb_flush(struct drm_device *dev, int engine)
 338 {
 339         nv50_vm_flush_engine(dev, 0);
 340 }
 341
 342 static void
 343 nv84_graph_tlb_flush(struct drm_device *dev, int engine)
 344 {
 345         struct drm_nouveau_private *dev_priv = dev->dev_private;
 346         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 347         bool idle, timeout = false;
 348         unsigned long flags;
 349         u64 start;
 350         u32 tmp;
 351
 352         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 353         nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
 354
 355         start = ptimer->read(dev);
 356         do {
 357                 idle = true;
 358
 359                 for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
 360                         if ((tmp & 7) == 1)
 361                                 idle = false;
 362                 }
 363
 364                 for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
 365                         if ((tmp & 7) == 1)
 366                                 idle = false;
 367                 }
 368
 369                 for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
 370                         if ((tmp & 7) == 1)
 371                                 idle = false;
 372                 }
 373         } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
 374
 375         if (timeout) {
 376                 NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
 377                               "0x%08x 0x%08x 0x%08x 0x%08x\n",
 378                          nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
 379                          nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
 380         }
 381
 382         nv50_vm_flush_engine(dev, 0);
 383
 384         nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
 385         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 386 }
 387
 388 static struct nouveau_enum nv50_mp_exec_error_names[] = {
 389         { 3, "STACK_UNDERFLOW", NULL },
 390         { 4, "QUADON_ACTIVE", NULL },
 391         { 8, "TIMEOUT", NULL },
 392         { 0x10, "INVALID_OPCODE", NULL },
 393         { 0x40, "BREAKPOINT", NULL },
 394         {}
 395 };
 396
 397 static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
 398         { 0x00000001, "NOTIFY" },
 399         { 0x00000002, "IN" },
 400         { 0x00000004, "OUT" },
 401         {}
 402 };
 403
 404 static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
 405         { 0x00000001, "FAULT" },
 406         {}
 407 };
 408
 409 static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
 410         { 0x00000001, "FAULT" },
 411         {}
 412 };
 413
 414 static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
 415         { 0x00000001, "FAULT" },
 416         {}
 417 };
 418
 419 /* There must be a *lot* of these. Will take some time to gather them up. */
 420 struct nouveau_enum nv50_data_error_names[] = {
 421         { 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL },
 422         { 0x00000004, "INVALID_VALUE", NULL },
 423         { 0x00000005, "INVALID_ENUM", NULL },
 424         { 0x00000008, "INVALID_OBJECT", NULL },
 425         { 0x00000009, "READ_ONLY_OBJECT", NULL },
 426         { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
 427         { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
 428         { 0x0000000c, "INVALID_BITFIELD", NULL },
 429         { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
 430         { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
 431         { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
 432         { 0x00000010, "RT_DOUBLE_BIND", NULL },
 433         { 0x00000011, "RT_TYPES_MISMATCH", NULL },
 434         { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
 435         { 0x00000015, "FP_TOO_FEW_REGS", NULL },
 436         { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
 437         { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
 438         { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
 439         { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
 440         { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
 441         { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
 442         { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
 443         { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
 444         { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
 445         { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
 446         { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
 447         { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
 448         { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
 449         { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
 450         { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
 451         { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
 452         { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
 453         { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
 454         { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
 455         { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
 456         { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
 457         { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
 458         { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
 459         { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
 460         { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
 461         { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
 462         {}
 463 };
 464
 465 static struct nouveau_bitfield nv50_graph_intr[] = {
 466         { 0x00000001, "NOTIFY" },
 467         { 0x00000002, "COMPUTE_QUERY" },
 468         { 0x00000010, "ILLEGAL_MTHD" },
 469         { 0x00000020, "ILLEGAL_CLASS" },
 470         { 0x00000040, "DOUBLE_NOTIFY" },
 471         { 0x00001000, "CONTEXT_SWITCH" },
 472         { 0x00010000, "BUFFER_NOTIFY" },
 473         { 0x00100000, "DATA_ERROR" },
 474         { 0x00200000, "TRAP" },
 475         { 0x01000000, "SINGLE_STEP" },
 476         {}
 477 };
 478
 479 static void
 480 nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
 481 {
 482         struct drm_nouveau_private *dev_priv = dev->dev_private;
 483         uint32_t units = nv_rd32(dev, 0x1540);
 484         uint32_t addr, mp10, status, pc, oplow, ophigh;
 485         int i;
 486         int mps = 0;
 487         for (i = 0; i < 4; i++) {
 488                 if (!(units & 1 << (i+24)))
 489                         continue;
 490                 if (dev_priv->chipset < 0xa0)
 491                         addr = 0x408200 + (tpid << 12) + (i << 7);
 492                 else
 493                         addr = 0x408100 + (tpid << 11) + (i << 7);
 494                 mp10 = nv_rd32(dev, addr + 0x10);
 495                 status = nv_rd32(dev, addr + 0x14);
 496                 if (!status)
 497                         continue;
 498                 if (display) {
 499                         nv_rd32(dev, addr + 0x20);
 500                         pc = nv_rd32(dev, addr + 0x24);
 501                         oplow = nv_rd32(dev, addr + 0x70);
 502                         ophigh = nv_rd32(dev, addr + 0x74);
 503                         NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
 504                                         "TP %d MP %d: ", tpid, i);
 505                         nouveau_enum_print(nv50_mp_exec_error_names, status);
 506                         printk(" at %06x warp %d, opcode %08x %08x\n",
 507                                         pc&0xffffff, pc >> 24,
 508                                         oplow, ophigh);
 509                 }
 510                 nv_wr32(dev, addr + 0x10, mp10);
 511                 nv_wr32(dev, addr + 0x14, 0);
 512                 mps++;
 513         }
 514         if (!mps && display)
 515                 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
 516                                 "No MPs claiming errors?\n", tpid);
 517 }
 518
 519 static void
 520 nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
 521                 uint32_t ustatus_new, int display, const char *name)
 522 {
 523         struct drm_nouveau_private *dev_priv = dev->dev_private;
 524         int tps = 0;
 525         uint32_t units = nv_rd32(dev, 0x1540);
 526         int i, r;
 527         uint32_t ustatus_addr, ustatus;
 528         for (i = 0; i < 16; i++) {
 529                 if (!(units & (1 << i)))
 530                         continue;
 531                 if (dev_priv->chipset < 0xa0)
 532                         ustatus_addr = ustatus_old + (i << 12);
 533                 else
 534                         ustatus_addr = ustatus_new + (i << 11);
 535                 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
 536                 if (!ustatus)
 537                         continue;
 538                 tps++;
 539                 switch (type) {
 540                 case 6: /* texture error... unknown for now */
 541                         if (display) {
 542                                 NV_ERROR(dev, "magic set %d:\n", i);
 543                                 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
 544                                         NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
 545                                                 nv_rd32(dev, r));
 546                         }
 547                         break;
 548                 case 7: /* MP error */
 549                         if (ustatus & 0x04030000) {
 550                                 nv50_pgraph_mp_trap(dev, i, display);
 551                                 ustatus &= ~0x04030000;
 552                         }
 553                         break;
 554                 case 8: /* TPDMA error */
 555                         {
 556                         uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
 557                         uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
 558                         uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
 559                         uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
 560                         uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
 561                         uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
 562                         uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
 563                         /* 2d engine destination */
 564                         if (ustatus & 0x00000010) {
 565                                 if (display) {
 566                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
 567                                                         i, e14, e10);
 568                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 569                                                         i, e0c, e18, e1c, e20, e24);
 570                                 }
 571                                 ustatus &= ~0x00000010;
 572                         }
 573                         /* Render target */
 574                         if (ustatus & 0x00000040) {
 575                                 if (display) {
 576                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
 577                                                         i, e14, e10);
 578                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 579                                                         i, e0c, e18, e1c, e20, e24);
 580                                 }
 581                                 ustatus &= ~0x00000040;
 582                         }
 583                         /* CUDA memory: l[], g[] or stack. */
 584                         if (ustatus & 0x00000080) {
 585                                 if (display) {
 586                                         if (e18 & 0x80000000) {
 587                                                 /* g[] read fault? */
 588                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
 589                                                                 i, e14, e10 | ((e18 >> 24) & 0x1f));
 590                                                 e18 &= ~0x1f000000;
 591                                         } else if (e18 & 0xc) {
 592                                                 /* g[] write fault? */
 593                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
 594                                                                 i, e14, e10 | ((e18 >> 7) & 0x1f));
 595                                                 e18 &= ~0x00000f80;
 596                                         } else {
 597                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
 598                                                                 i, e14, e10);
 599                                         }
 600                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 601                                                         i, e0c, e18, e1c, e20, e24);
 602                                 }
 603                                 ustatus &= ~0x00000080;
 604                         }
 605                         }
 606                         break;
 607                 }
 608                 if (ustatus) {
 609                         if (display)
 610                                 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
 611                 }
 612                 nv_wr32(dev, ustatus_addr, 0xc0000000);
 613         }
 614
 615         if (!tps && display)
 616                 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
 617 }
 618
 619 static int
 620 nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
 621 {
 622         u32 status = nv_rd32(dev, 0x400108);
 623         u32 ustatus;
 624
 625         if (!status && display) {
 626                 NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
 627                 return 1;
 628         }
 629
 630         /* DISPATCH: Relays commands to other units and handles NOTIFY,
 631          * COND, QUERY. If you get a trap from it, the command is still stuck
 632          * in DISPATCH and you need to do something about it. */
 633         if (status & 0x001) {
 634                 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
 635                 if (!ustatus && display) {
 636                         NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
 637                 }
 638
 639                 nv_wr32(dev, 0x400500, 0x00000000);
 640
 641                 /* Known to be triggered by screwed up NOTIFY and COND... */
 642                 if (ustatus & 0x00000001) {
 643                         u32 addr = nv_rd32(dev, 0x400808);
 644                         u32 subc = (addr & 0x00070000) >> 16;
 645                         u32 mthd = (addr & 0x00001ffc);
 646                         u32 datal = nv_rd32(dev, 0x40080c);
 647                         u32 datah = nv_rd32(dev, 0x400810);
 648                         u32 class = nv_rd32(dev, 0x400814);
 649                         u32 r848 = nv_rd32(dev, 0x400848);
 650
 651                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
 652                         if (display && (addr & 0x80000000)) {
 653                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 654                                              "subc %d class 0x%04x mthd 0x%04x "
 655                                              "data 0x%08x%08x "
 656                                              "400808 0x%08x 400848 0x%08x\n",
 657                                         chid, inst, subc, class, mthd, datah,
 658                                         datal, addr, r848);
 659                         } else
 660                         if (display) {
 661                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 662                         }
 663
 664                         nv_wr32(dev, 0x400808, 0);
 665                         nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
 666                         nv_wr32(dev, 0x400848, 0);
 667                         ustatus &= ~0x00000001;
 668                 }
 669
 670                 if (ustatus & 0x00000002) {
 671                         u32 addr = nv_rd32(dev, 0x40084c);
 672                         u32 subc = (addr & 0x00070000) >> 16;
 673                         u32 mthd = (addr & 0x00001ffc);
 674                         u32 data = nv_rd32(dev, 0x40085c);
 675                         u32 class = nv_rd32(dev, 0x400814);
 676
 677                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
 678                         if (display && (addr & 0x80000000)) {
 679                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 680                                              "subc %d class 0x%04x mthd 0x%04x "
 681                                              "data 0x%08x 40084c 0x%08x\n",
 682                                         chid, inst, subc, class, mthd,
 683                                         data, addr);
 684                         } else
 685                         if (display) {
 686                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 687                         }
 688
 689                         nv_wr32(dev, 0x40084c, 0);
 690                         ustatus &= ~0x00000002;
 691                 }
 692
 693                 if (ustatus && display) {
 694                         NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
 695                                       "0x%08x)\n", ustatus);
 696                 }
 697
 698                 nv_wr32(dev, 0x400804, 0xc0000000);
 699                 nv_wr32(dev, 0x400108, 0x001);
 700                 status &= ~0x001;
 701                 if (!status)
 702                         return 0;
 703         }
 704
 705         /* M2MF: Memory to memory copy engine. */
 706         if (status & 0x002) {
 707                 u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
 708                 if (display) {
 709                         NV_INFO(dev, "PGRAPH - TRAP_M2MF");
 710                         nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
 711                         printk("\n");
 712                         NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
 713                                 nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
 714                                 nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
 715
 716                 }
 717
 718                 /* No sane way found yet -- just reset the bugger. */
 719                 nv_wr32(dev, 0x400040, 2);
 720                 nv_wr32(dev, 0x400040, 0);
 721                 nv_wr32(dev, 0x406800, 0xc0000000);
 722                 nv_wr32(dev, 0x400108, 0x002);
 723                 status &= ~0x002;
 724         }
 725
 726         /* VFETCH: Fetches data from vertex buffers. */
 727         if (status & 0x004) {
 728                 u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
 729                 if (display) {
 730                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
 731                         nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
 732                         printk("\n");
 733                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
 734                                 nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
 735                                 nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
 736                 }
 737
 738                 nv_wr32(dev, 0x400c04, 0xc0000000);
 739                 nv_wr32(dev, 0x400108, 0x004);
 740                 status &= ~0x004;
 741         }
 742
 743         /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
 744         if (status & 0x008) {
 745                 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
 746                 if (display) {
 747                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
 748                         nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
 749                         printk("\n");
 750                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
 751                                 nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
 752                                 nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
 753
 754                 }
 755
 756                 /* No sane way found yet -- just reset the bugger. */
 757                 nv_wr32(dev, 0x400040, 0x80);
 758                 nv_wr32(dev, 0x400040, 0);
 759                 nv_wr32(dev, 0x401800, 0xc0000000);
 760                 nv_wr32(dev, 0x400108, 0x008);
 761                 status &= ~0x008;
 762         }
 763
 764         /* CCACHE: Handles code and c[] caches and fills them. */
 765         if (status & 0x010) {
 766                 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
 767                 if (display) {
 768                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
 769                         nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
 770                         printk("\n");
 771                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
 772                                      " %08x %08x %08x\n",
 773                                 nv_rd32(dev, 0x405000), nv_rd32(dev, 0x405004),
 774                                 nv_rd32(dev, 0x405008), nv_rd32(dev, 0x40500c),
 775                                 nv_rd32(dev, 0x405010), nv_rd32(dev, 0x405014),
 776                                 nv_rd32(dev, 0x40501c));
 777
 778                 }
 779
 780                 nv_wr32(dev, 0x405018, 0xc0000000);
 781                 nv_wr32(dev, 0x400108, 0x010);
 782                 status &= ~0x010;
 783         }
 784
 785         /* Unknown, not seen yet... 0x402000 is the only trap status reg
 786          * remaining, so try to handle it anyway. Perhaps related to that
 787          * unknown DMA slot on tesla? */
 788         if (status & 0x20) {
 789                 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
 790                 if (display)
 791                         NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
 792                 nv_wr32(dev, 0x402000, 0xc0000000);
 793                 /* no status modifiction on purpose */
 794         }
 795
 796         /* TEXTURE: CUDA texturing units */
 797         if (status & 0x040) {
 798                 nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
 799                                     "PGRAPH - TRAP_TEXTURE");
 800                 nv_wr32(dev, 0x400108, 0x040);
 801                 status &= ~0x040;
 802         }
 803
 804         /* MP: CUDA execution engines. */
 805         if (status & 0x080) {
 806                 nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
 807                                     "PGRAPH - TRAP_MP");
 808                 nv_wr32(dev, 0x400108, 0x080);
 809                 status &= ~0x080;
 810         }
 811
 812         /* TPDMA:  Handles TP-initiated uncached memory accesses:
 813          * l[], g[], stack, 2d surfaces, render targets. */
 814         if (status & 0x100) {
 815                 nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
 816                                     "PGRAPH - TRAP_TPDMA");
 817                 nv_wr32(dev, 0x400108, 0x100);
 818                 status &= ~0x100;
 819         }
 820
 821         if (status) {
 822                 if (display)
 823                         NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
 824                 nv_wr32(dev, 0x400108, status);
 825         }
 826
 827         return 1;
 828 }
 829
 830 int
 831 nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
 832 {
 833         struct drm_nouveau_private *dev_priv = dev->dev_private;
 834         struct nouveau_channel *chan;
 835         unsigned long flags;
 836         int i;
 837
 838         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 839         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 840                 chan = dev_priv->channels.ptr[i];
 841                 if (!chan || !chan->ramin)
 842                         continue;
 843
 844                 if (inst == chan->ramin->vinst)
 845                         break;
 846         }
 847         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 848         return i;
 849 }
 850
 851 static void
 852 nv50_graph_isr(struct drm_device *dev)
 853 {
 854         u32 stat;
 855
 856         while ((stat = nv_rd32(dev, 0x400100))) {
 857                 u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
 858                 u32 chid = nv50_graph_isr_chid(dev, inst);
 859                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
 860                 u32 subc = (addr & 0x00070000) >> 16;
 861                 u32 mthd = (addr & 0x00001ffc);
 862                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
 863                 u32 class = nv_rd32(dev, 0x400814);
 864                 u32 show = stat;
 865
 866                 if (stat & 0x00000010) {
 867                         if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
 868                                                        mthd, data))
 869                                 show &= ~0x00000010;
 870                 }
 871
 872                 if (stat & 0x00001000) {
 873                         nv_wr32(dev, 0x400500, 0x00000000);
 874                         nv_wr32(dev, 0x400100, 0x00001000);
 875                         nv_mask(dev, 0x40013c, 0x00001000, 0x00000000);
 876                         nv50_graph_context_switch(dev);
 877                         stat &= ~0x00001000;
 878                         show &= ~0x00001000;
 879                 }
 880
 881                 show = (show && nouveau_ratelimit()) ? show : 0;
 882
 883                 if (show & 0x00100000) {
 884                         u32 ecode = nv_rd32(dev, 0x400110);
 885                         NV_INFO(dev, "PGRAPH - DATA_ERROR ");
 886                         nouveau_enum_print(nv50_data_error_names, ecode);
 887                         printk("\n");
 888                 }
 889
 890                 if (stat & 0x00200000) {
 891                         if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
 892                                 show &= ~0x00200000;
 893                 }
 894
 895                 nv_wr32(dev, 0x400100, stat);
 896                 nv_wr32(dev, 0x400500, 0x00010001);
 897
 898                 if (show) {
 899                         NV_INFO(dev, "PGRAPH -");
 900                         nouveau_bitfield_print(nv50_graph_intr, show);
 901                         printk("\n");
 902                         NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
 903                                      "class 0x%04x mthd 0x%04x data 0x%08x\n",
 904                                 chid, inst, subc, class, mthd, data);
 905                         nv50_fb_vm_trap(dev, 1);
 906                 }
 907         }
 908
 909         if (nv_rd32(dev, 0x400824) & (1 << 31))
 910                 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
 911 }
 912
 913 static void
 914 nv50_graph_destroy(struct drm_device *dev, int engine)
 915 {
 916         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
 917
 918         NVOBJ_ENGINE_DEL(dev, GR);
 919
 920         nouveau_irq_unregister(dev, 12);
 921         kfree(pgraph);
 922 }
 923
 924 int
 925 nv50_graph_create(struct drm_device *dev)
 926 {
 927         struct drm_nouveau_private *dev_priv = dev->dev_private;
 928         struct nv50_graph_engine *pgraph;
 929         int ret;
 930
 931         pgraph = kzalloc(sizeof(*pgraph),GFP_KERNEL);
 932         if (!pgraph)
 933                 return -ENOMEM;
 934
 935         ret = nv50_grctx_init(dev, pgraph->ctxprog, ARRAY_SIZE(pgraph->ctxprog),
 936                                   &pgraph->ctxprog_size,
 937                                   &pgraph->grctx_size);
 938         if (ret) {
 939                 NV_ERROR(dev, "PGRAPH: ctxprog build failed\n");
 940                 kfree(pgraph);
 941                 return 0;
 942         }
 943
 944         pgraph->base.destroy = nv50_graph_destroy;
 945         pgraph->base.init = nv50_graph_init;
 946         pgraph->base.fini = nv50_graph_fini;
 947         pgraph->base.context_new = nv50_graph_context_new;
 948         pgraph->base.context_del = nv50_graph_context_del;
 949         pgraph->base.object_new = nv50_graph_object_new;
 950         if (dev_priv->chipset == 0x50 || dev_priv->chipset == 0xac)
 951                 pgraph->base.tlb_flush = nv50_graph_tlb_flush;
 952         else
 953                 pgraph->base.tlb_flush = nv84_graph_tlb_flush;
 954
 955         nouveau_irq_register(dev, 12, nv50_graph_isr);
 956
 957         NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
 958         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
 959         NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
 960         NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
 961
 962         /* tesla */
 963         if (dev_priv->chipset == 0x50)
 964                 NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
 965         else
 966         if (dev_priv->chipset < 0xa0)
 967                 NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
 968         else {
 969                 switch (dev_priv->chipset) {
 970                 case 0xa0:
 971                 case 0xaa:
 972                 case 0xac:
 973                         NVOBJ_CLASS(dev, 0x8397, GR);
 974                         break;
 975                 case 0xa3:
 976                 case 0xa5:
 977                 case 0xa8:
 978                         NVOBJ_CLASS(dev, 0x8597, GR);
 979                         break;
 980                 case 0xaf:
 981                         NVOBJ_CLASS(dev, 0x8697, GR);
 982                         break;
 983                 }
 984         }
 985
 986         /* compute */
 987         NVOBJ_CLASS(dev, 0x50c0, GR);
 988         if (dev_priv->chipset  > 0xa0 &&
 989             dev_priv->chipset != 0xaa &&
 990             dev_priv->chipset != 0xac)
 991                 NVOBJ_CLASS(dev, 0x85c0, GR);
 992
 993         return 0;
 994 }