drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
  28 #include "nv50_display.h"
  29 #include "nouveau_crtc.h"
  30 #include "nouveau_encoder.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_fb.h"
  33 #include "nouveau_fbcon.h"
  34 #include "nouveau_ramht.h"
  35 #include "drm_crtc_helper.h"
  36
  37 static void nv50_display_isr(struct drm_device *);
  38 static void nv50_display_bh(unsigned long);
  39
  40 static inline int
  41 nv50_sor_nr(struct drm_device *dev)
  42 {
  43         struct drm_nouveau_private *dev_priv = dev->dev_private;
  44
  45         if (dev_priv->chipset  < 0x90 ||
  46             dev_priv->chipset == 0x92 ||
  47             dev_priv->chipset == 0xa0)
  48                 return 2;
  49
  50         return 4;
  51 }
  52
  53 u32
  54 nv50_display_active_crtcs(struct drm_device *dev)
  55 {
  56         struct drm_nouveau_private *dev_priv = dev->dev_private;
  57         u32 mask = 0;
  58         int i;
  59
  60         if (dev_priv->chipset  < 0x90 ||
  61             dev_priv->chipset == 0x92 ||
  62             dev_priv->chipset == 0xa0) {
  63                 for (i = 0; i < 2; i++)
  64                         mask |= nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
  65         } else {
  66                 for (i = 0; i < 4; i++)
  67                         mask |= nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
  68         }
  69
  70         for (i = 0; i < 3; i++)
  71                 mask |= nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
  72
  73         return mask & 3;
  74 }
  75
  76 static int
  77 evo_icmd(struct drm_device *dev, int ch, u32 mthd, u32 data)
  78 {
  79         int ret = 0;
  80         nv_mask(dev, 0x610300 + (ch * 0x08), 0x00000001, 0x00000001);
  81         nv_wr32(dev, 0x610304 + (ch * 0x08), data);
  82         nv_wr32(dev, 0x610300 + (ch * 0x08), 0x80000001 | mthd);
  83         if (!nv_wait(dev, 0x610300 + (ch * 0x08), 0x80000000, 0x00000000))
  84                 ret = -EBUSY;
  85         if (ret || (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO))
  86                 NV_INFO(dev, "EvoPIO: %d 0x%04x 0x%08x\n", ch, mthd, data);
  87         nv_mask(dev, 0x610300 + (ch * 0x08), 0x00000001, 0x00000000);
  88         return ret;
  89 }
  90
  91 int
  92 nv50_display_early_init(struct drm_device *dev)
  93 {
  94         u32 ctrl = nv_rd32(dev, 0x610200);
  95         int i;
  96
  97         /* check if master evo channel is already active, a good a sign as any
  98          * that the display engine is in a weird state (hibernate/kexec), if
  99          * it is, do our best to reset the display engine...
 100          */
 101         if ((ctrl & 0x00000003) == 0x00000003) {
 102                 NV_INFO(dev, "PDISP: EVO(0) 0x%08x, resetting...\n", ctrl);
 103
 104                 /* deactivate both heads first, PDISP will disappear forever
 105                  * (well, until you power cycle) on some boards as soon as
 106                  * PMC_ENABLE is hit unless they are..
 107                  */
 108                 for (i = 0; i < 2; i++) {
 109                         evo_icmd(dev, 0, 0x0880 + (i * 0x400), 0x05000000);
 110                         evo_icmd(dev, 0, 0x089c + (i * 0x400), 0);
 111                         evo_icmd(dev, 0, 0x0840 + (i * 0x400), 0);
 112                         evo_icmd(dev, 0, 0x0844 + (i * 0x400), 0);
 113                         evo_icmd(dev, 0, 0x085c + (i * 0x400), 0);
 114                         evo_icmd(dev, 0, 0x0874 + (i * 0x400), 0);
 115                 }
 116                 evo_icmd(dev, 0, 0x0080, 0);
 117
 118                 /* reset PDISP */
 119                 nv_mask(dev, 0x000200, 0x40000000, 0x00000000);
 120                 nv_mask(dev, 0x000200, 0x40000000, 0x40000000);
 121         }
 122
 123         return 0;
 124 }
 125
 126 void
 127 nv50_display_late_takedown(struct drm_device *dev)
 128 {
 129 }
 130
 131 int
 132 nv50_display_sync(struct drm_device *dev)
 133 {
 134         struct drm_nouveau_private *dev_priv = dev->dev_private;
 135         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 136         struct nv50_display *disp = nv50_display(dev);
 137         struct nouveau_channel *evo = disp->master;
 138         u64 start;
 139         int ret;
 140
 141         ret = RING_SPACE(evo, 6);
 142         if (ret == 0) {
 143                 BEGIN_NV04(evo, 0, 0x0084, 1);
 144                 OUT_RING  (evo, 0x80000000);
 145                 BEGIN_NV04(evo, 0, 0x0080, 1);
 146                 OUT_RING  (evo, 0);
 147                 BEGIN_NV04(evo, 0, 0x0084, 1);
 148                 OUT_RING  (evo, 0x00000000);
 149
 150                 nv_wo32(disp->ntfy, 0x000, 0x00000000);
 151                 FIRE_RING (evo);
 152
 153                 start = ptimer->read(dev);
 154                 do {
 155                         if (nv_ro32(disp->ntfy, 0x000))
 156                                 return 0;
 157                 } while (ptimer->read(dev) - start < 2000000000ULL);
 158         }
 159
 160         return -EBUSY;
 161 }
 162
 163 int
 164 nv50_display_init(struct drm_device *dev)
 165 {
 166         struct nouveau_channel *evo;
 167         int ret, i;
 168         u32 val;
 169
 170         NV_DEBUG_KMS(dev, "\n");
 171
 172         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
 173
 174         /*
 175          * I think the 0x006101XX range is some kind of main control area
 176          * that enables things.
 177          */
 178         /* CRTC? */
 179         for (i = 0; i < 2; i++) {
 180                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
 181                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
 182                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
 183                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
 184                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
 185                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
 186                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
 187                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
 188         }
 189
 190         /* DAC */
 191         for (i = 0; i < 3; i++) {
 192                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
 193                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
 194         }
 195
 196         /* SOR */
 197         for (i = 0; i < nv50_sor_nr(dev); i++) {
 198                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 199                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 200         }
 201
 202         /* EXT */
 203         for (i = 0; i < 3; i++) {
 204                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 205                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 206         }
 207
 208         for (i = 0; i < 3; i++) {
 209                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 210                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 211                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 212         }
 213
 214         /* The precise purpose is unknown, i suspect it has something to do
 215          * with text mode.
 216          */
 217         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 218                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 219                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 220                 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
 221                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 222                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 223                                                 nv_rd32(dev, 0x6194e8));
 224                         return -EBUSY;
 225                 }
 226         }
 227
 228         for (i = 0; i < 2; i++) {
 229                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 230                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 231                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 232                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 233                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 234                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 235                         return -EBUSY;
 236                 }
 237
 238                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 239                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 240                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 241                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 242                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 243                         NV_ERROR(dev, "timeout: "
 244                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 245                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 246                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 247                         return -EBUSY;
 248                 }
 249         }
 250
 251         nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
 252         nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
 253         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
 254         nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
 255         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
 256                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
 257                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
 258                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
 259
 260         ret = nv50_evo_init(dev);
 261         if (ret)
 262                 return ret;
 263         evo = nv50_display(dev)->master;
 264
 265         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
 266
 267         ret = RING_SPACE(evo, 3);
 268         if (ret)
 269                 return ret;
 270         BEGIN_NV04(evo, 0, NV50_EVO_UNK84, 2);
 271         OUT_RING  (evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 272         OUT_RING  (evo, NvEvoSync);
 273
 274         return nv50_display_sync(dev);
 275 }
 276
 277 void
 278 nv50_display_fini(struct drm_device *dev)
 279 {
 280         struct nv50_display *disp = nv50_display(dev);
 281         struct nouveau_channel *evo = disp->master;
 282         struct drm_crtc *drm_crtc;
 283         int ret, i;
 284
 285         NV_DEBUG_KMS(dev, "\n");
 286
 287         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 288                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 289
 290                 nv50_crtc_blank(crtc, true);
 291         }
 292
 293         ret = RING_SPACE(evo, 2);
 294         if (ret == 0) {
 295                 BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1);
 296                 OUT_RING(evo, 0);
 297         }
 298         FIRE_RING(evo);
 299
 300         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 301          * cleaning up?
 302          */
 303         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 304                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 305                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 306
 307                 if (!crtc->base.enabled)
 308                         continue;
 309
 310                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 311                 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
 312                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 313                                       "0x%08x\n", mask, mask);
 314                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 315                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 316                 }
 317         }
 318
 319         for (i = 0; i < 2; i++) {
 320                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0);
 321                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 322                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 323                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 324                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 325                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 326                 }
 327         }
 328
 329         nv50_evo_fini(dev);
 330
 331         for (i = 0; i < 3; i++) {
 332                 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
 333                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 334                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 335                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 336                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 337                 }
 338         }
 339
 340         /* disable interrupts. */
 341         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
 342 }
 343
 344 int
 345 nv50_display_create(struct drm_device *dev)
 346 {
 347         struct drm_nouveau_private *dev_priv = dev->dev_private;
 348         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 349         struct drm_connector *connector, *ct;
 350         struct nv50_display *priv;
 351         int ret, i;
 352
 353         NV_DEBUG_KMS(dev, "\n");
 354
 355         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 356         if (!priv)
 357                 return -ENOMEM;
 358         dev_priv->engine.display.priv = priv;
 359
 360         /* Create CRTC objects */
 361         for (i = 0; i < 2; i++) {
 362                 ret = nv50_crtc_create(dev, i);
 363                 if (ret)
 364                         return ret;
 365         }
 366
 367         /* We setup the encoders from the BIOS table */
 368         for (i = 0 ; i < dcb->entries; i++) {
 369                 struct dcb_entry *entry = &dcb->entry[i];
 370
 371                 if (entry->location != DCB_LOC_ON_CHIP) {
 372                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 373                                 entry->type, ffs(entry->or) - 1);
 374                         continue;
 375                 }
 376
 377                 connector = nouveau_connector_create(dev, entry->connector);
 378                 if (IS_ERR(connector))
 379                         continue;
 380
 381                 switch (entry->type) {
 382                 case OUTPUT_TMDS:
 383                 case OUTPUT_LVDS:
 384                 case OUTPUT_DP:
 385                         nv50_sor_create(connector, entry);
 386                         break;
 387                 case OUTPUT_ANALOG:
 388                         nv50_dac_create(connector, entry);
 389                         break;
 390                 default:
 391                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 392                         continue;
 393                 }
 394         }
 395
 396         list_for_each_entry_safe(connector, ct,
 397                                  &dev->mode_config.connector_list, head) {
 398                 if (!connector->encoder_ids[0]) {
 399                         NV_WARN(dev, "%s has no encoders, removing\n",
 400                                 drm_get_connector_name(connector));
 401                         connector->funcs->destroy(connector);
 402                 }
 403         }
 404
 405         tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev);
 406         nouveau_irq_register(dev, 26, nv50_display_isr);
 407
 408         ret = nv50_evo_create(dev);
 409         if (ret) {
 410                 nv50_display_destroy(dev);
 411                 return ret;
 412         }
 413
 414         return 0;
 415 }
 416
 417 void
 418 nv50_display_destroy(struct drm_device *dev)
 419 {
 420         struct nv50_display *disp = nv50_display(dev);
 421
 422         NV_DEBUG_KMS(dev, "\n");
 423
 424         nv50_evo_destroy(dev);
 425         nouveau_irq_unregister(dev, 26);
 426         kfree(disp);
 427 }
 428
 429 void
 430 nv50_display_flip_stop(struct drm_crtc *crtc)
 431 {
 432         struct nv50_display *disp = nv50_display(crtc->dev);
 433         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 434         struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
 435         struct nouveau_channel *evo = dispc->sync;
 436         int ret;
 437
 438         ret = RING_SPACE(evo, 8);
 439         if (ret) {
 440                 WARN_ON(1);
 441                 return;
 442         }
 443
 444         BEGIN_NV04(evo, 0, 0x0084, 1);
 445         OUT_RING  (evo, 0x00000000);
 446         BEGIN_NV04(evo, 0, 0x0094, 1);
 447         OUT_RING  (evo, 0x00000000);
 448         BEGIN_NV04(evo, 0, 0x00c0, 1);
 449         OUT_RING  (evo, 0x00000000);
 450         BEGIN_NV04(evo, 0, 0x0080, 1);
 451         OUT_RING  (evo, 0x00000000);
 452         FIRE_RING (evo);
 453 }
 454
 455 int
 456 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 457                        struct nouveau_channel *chan)
 458 {
 459         struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
 460         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 461         struct nv50_display *disp = nv50_display(crtc->dev);
 462         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 463         struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
 464         struct nouveau_channel *evo = dispc->sync;
 465         int ret;
 466
 467         ret = RING_SPACE(evo, chan ? 25 : 27);
 468         if (unlikely(ret))
 469                 return ret;
 470
 471         /* synchronise with the rendering channel, if necessary */
 472         if (likely(chan)) {
 473                 ret = RING_SPACE(chan, 10);
 474                 if (ret) {
 475                         WIND_RING(evo);
 476                         return ret;
 477                 }
 478
 479                 if (dev_priv->chipset < 0xc0) {
 480                         BEGIN_NV04(chan, 0, 0x0060, 2);
 481                         OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 482                         OUT_RING  (chan, dispc->sem.offset);
 483                         BEGIN_NV04(chan, 0, 0x006c, 1);
 484                         OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
 485                         BEGIN_NV04(chan, 0, 0x0064, 2);
 486                         OUT_RING  (chan, dispc->sem.offset ^ 0x10);
 487                         OUT_RING  (chan, 0x74b1e000);
 488                         BEGIN_NV04(chan, 0, 0x0060, 1);
 489                         if (dev_priv->chipset < 0x84)
 490                                 OUT_RING  (chan, NvSema);
 491                         else
 492                                 OUT_RING  (chan, chan->vram_handle);
 493                 } else {
 494                         u64 offset = chan->dispc_vma[nv_crtc->index].offset;
 495                         offset += dispc->sem.offset;
 496                         BEGIN_NVC0(chan, 0, 0x0010, 4);
 497                         OUT_RING  (chan, upper_32_bits(offset));
 498                         OUT_RING  (chan, lower_32_bits(offset));
 499                         OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
 500                         OUT_RING  (chan, 0x1002);
 501                         BEGIN_NVC0(chan, 0, 0x0010, 4);
 502                         OUT_RING  (chan, upper_32_bits(offset));
 503                         OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
 504                         OUT_RING  (chan, 0x74b1e000);
 505                         OUT_RING  (chan, 0x1001);
 506                 }
 507                 FIRE_RING (chan);
 508         } else {
 509                 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
 510                                 0xf00d0000 | dispc->sem.value);
 511         }
 512
 513         /* queue the flip on the crtc's "display sync" channel */
 514         BEGIN_NV04(evo, 0, 0x0100, 1);
 515         OUT_RING  (evo, 0xfffe0000);
 516         if (chan) {
 517                 BEGIN_NV04(evo, 0, 0x0084, 1);
 518                 OUT_RING  (evo, 0x00000100);
 519         } else {
 520                 BEGIN_NV04(evo, 0, 0x0084, 1);
 521                 OUT_RING  (evo, 0x00000010);
 522                 /* allows gamma somehow, PDISP will bitch at you if
 523                  * you don't wait for vblank before changing this..
 524                  */
 525                 BEGIN_NV04(evo, 0, 0x00e0, 1);
 526                 OUT_RING  (evo, 0x40000000);
 527         }
 528         BEGIN_NV04(evo, 0, 0x0088, 4);
 529         OUT_RING  (evo, dispc->sem.offset);
 530         OUT_RING  (evo, 0xf00d0000 | dispc->sem.value);
 531         OUT_RING  (evo, 0x74b1e000);
 532         OUT_RING  (evo, NvEvoSync);
 533         BEGIN_NV04(evo, 0, 0x00a0, 2);
 534         OUT_RING  (evo, 0x00000000);
 535         OUT_RING  (evo, 0x00000000);
 536         BEGIN_NV04(evo, 0, 0x00c0, 1);
 537         OUT_RING  (evo, nv_fb->r_dma);
 538         BEGIN_NV04(evo, 0, 0x0110, 2);
 539         OUT_RING  (evo, 0x00000000);
 540         OUT_RING  (evo, 0x00000000);
 541         BEGIN_NV04(evo, 0, 0x0800, 5);
 542         OUT_RING  (evo, nv_fb->nvbo->bo.offset >> 8);
 543         OUT_RING  (evo, 0);
 544         OUT_RING  (evo, (fb->height << 16) | fb->width);
 545         OUT_RING  (evo, nv_fb->r_pitch);
 546         OUT_RING  (evo, nv_fb->r_format);
 547         BEGIN_NV04(evo, 0, 0x0080, 1);
 548         OUT_RING  (evo, 0x00000000);
 549         FIRE_RING (evo);
 550
 551         dispc->sem.offset ^= 0x10;
 552         dispc->sem.value++;
 553         return 0;
 554 }
 555
 556 static u16
 557 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
 558                            u32 mc, int pxclk)
 559 {
 560         struct drm_nouveau_private *dev_priv = dev->dev_private;
 561         struct nouveau_connector *nv_connector = NULL;
 562         struct drm_encoder *encoder;
 563         struct nvbios *bios = &dev_priv->vbios;
 564         u32 script = 0, or;
 565
 566         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 567                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 568
 569                 if (nv_encoder->dcb != dcb)
 570                         continue;
 571
 572                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 573                 break;
 574         }
 575
 576         or = ffs(dcb->or) - 1;
 577         switch (dcb->type) {
 578         case OUTPUT_LVDS:
 579                 script = (mc >> 8) & 0xf;
 580                 if (bios->fp_no_ddc) {
 581                         if (bios->fp.dual_link)
 582                                 script |= 0x0100;
 583                         if (bios->fp.if_is_24bit)
 584                                 script |= 0x0200;
 585                 } else {
 586                         /* determine number of lvds links */
 587                         if (nv_connector && nv_connector->edid &&
 588                             nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
 589                                 /* http://www.spwg.org */
 590                                 if (((u8 *)nv_connector->edid)[121] == 2)
 591                                         script |= 0x0100;
 592                         } else
 593                         if (pxclk >= bios->fp.duallink_transition_clk) {
 594                                 script |= 0x0100;
 595                         }
 596
 597                         /* determine panel depth */
 598                         if (script & 0x0100) {
 599                                 if (bios->fp.strapless_is_24bit & 2)
 600                                         script |= 0x0200;
 601                         } else {
 602                                 if (bios->fp.strapless_is_24bit & 1)
 603                                         script |= 0x0200;
 604                         }
 605
 606                         if (nv_connector && nv_connector->edid &&
 607                             (nv_connector->edid->revision >= 4) &&
 608                             (nv_connector->edid->input & 0x70) >= 0x20)
 609                                 script |= 0x0200;
 610                 }
 611
 612                 if (nouveau_uscript_lvds >= 0) {
 613                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 614                                      "for output LVDS-%d\n", script,
 615                                      nouveau_uscript_lvds, or);
 616                         script = nouveau_uscript_lvds;
 617                 }
 618                 break;
 619         case OUTPUT_TMDS:
 620                 script = (mc >> 8) & 0xf;
 621                 if (pxclk >= 165000)
 622                         script |= 0x0100;
 623
 624                 if (nouveau_uscript_tmds >= 0) {
 625                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 626                                      "for output TMDS-%d\n", script,
 627                                      nouveau_uscript_tmds, or);
 628                         script = nouveau_uscript_tmds;
 629                 }
 630                 break;
 631         case OUTPUT_DP:
 632                 script = (mc >> 8) & 0xf;
 633                 break;
 634         case OUTPUT_ANALOG:
 635                 script = 0xff;
 636                 break;
 637         default:
 638                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 639                 break;
 640         }
 641
 642         return script;
 643 }
 644
 645 static void
 646 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
 647 {
 648         struct drm_nouveau_private *dev_priv = dev->dev_private;
 649         struct nouveau_channel *chan, *tmp;
 650
 651         list_for_each_entry_safe(chan, tmp, &dev_priv->vbl_waiting,
 652                                  nvsw.vbl_wait) {
 653                 if (chan->nvsw.vblsem_head != crtc)
 654                         continue;
 655
 656                 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
 657                                                 chan->nvsw.vblsem_rval);
 658                 list_del(&chan->nvsw.vbl_wait);
 659                 drm_vblank_put(dev, crtc);
 660         }
 661
 662         drm_handle_vblank(dev, crtc);
 663 }
 664
 665 static void
 666 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
 667 {
 668         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
 669                 nv50_display_vblank_crtc_handler(dev, 0);
 670
 671         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
 672                 nv50_display_vblank_crtc_handler(dev, 1);
 673
 674         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC);
 675 }
 676
 677 static void
 678 nv50_display_unk10_handler(struct drm_device *dev)
 679 {
 680         struct drm_nouveau_private *dev_priv = dev->dev_private;
 681         struct nv50_display *disp = nv50_display(dev);
 682         u32 unk30 = nv_rd32(dev, 0x610030), mc;
 683         int i, crtc, or = 0, type = OUTPUT_ANY;
 684
 685         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 686         disp->irq.dcb = NULL;
 687
 688         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 689
 690         /* Determine which CRTC we're dealing with, only 1 ever will be
 691          * signalled at the same time with the current nouveau code.
 692          */
 693         crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
 694         if (crtc < 0)
 695                 goto ack;
 696
 697         /* Nothing needs to be done for the encoder */
 698         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 699         if (crtc < 0)
 700                 goto ack;
 701
 702         /* Find which encoder was connected to the CRTC */
 703         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 704                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
 705                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 706                 if (!(mc & (1 << crtc)))
 707                         continue;
 708
 709                 switch ((mc & 0x00000f00) >> 8) {
 710                 case 0: type = OUTPUT_ANALOG; break;
 711                 case 1: type = OUTPUT_TV; break;
 712                 default:
 713                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 714                         goto ack;
 715                 }
 716
 717                 or = i;
 718         }
 719
 720         for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 721                 if (dev_priv->chipset  < 0x90 ||
 722                     dev_priv->chipset == 0x92 ||
 723                     dev_priv->chipset == 0xa0)
 724                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
 725                 else
 726                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
 727
 728                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 729                 if (!(mc & (1 << crtc)))
 730                         continue;
 731
 732                 switch ((mc & 0x00000f00) >> 8) {
 733                 case 0: type = OUTPUT_LVDS; break;
 734                 case 1: type = OUTPUT_TMDS; break;
 735                 case 2: type = OUTPUT_TMDS; break;
 736                 case 5: type = OUTPUT_TMDS; break;
 737                 case 8: type = OUTPUT_DP; break;
 738                 case 9: type = OUTPUT_DP; break;
 739                 default:
 740                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 741                         goto ack;
 742                 }
 743
 744                 or = i;
 745         }
 746
 747         /* There was no encoder to disable */
 748         if (type == OUTPUT_ANY)
 749                 goto ack;
 750
 751         /* Disable the encoder */
 752         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 753                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
 754
 755                 if (dcb->type == type && (dcb->or & (1 << or))) {
 756                         nouveau_bios_run_display_table(dev, 0, -1, dcb, -1);
 757                         disp->irq.dcb = dcb;
 758                         goto ack;
 759                 }
 760         }
 761
 762         NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 763 ack:
 764         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 765         nv_wr32(dev, 0x610030, 0x80000000);
 766 }
 767
 768 static void
 769 nv50_display_unk20_handler(struct drm_device *dev)
 770 {
 771         struct drm_nouveau_private *dev_priv = dev->dev_private;
 772         struct nv50_display *disp = nv50_display(dev);
 773         u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
 774         struct dcb_entry *dcb;
 775         int i, crtc, or = 0, type = OUTPUT_ANY;
 776
 777         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 778         dcb = disp->irq.dcb;
 779         if (dcb) {
 780                 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1);
 781                 disp->irq.dcb = NULL;
 782         }
 783
 784         /* CRTC clock change requested? */
 785         crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
 786         if (crtc >= 0) {
 787                 pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
 788                 pclk &= 0x003fffff;
 789                 if (pclk)
 790                         nv50_crtc_set_clock(dev, crtc, pclk);
 791
 792                 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
 793                 tmp &= ~0x000000f;
 794                 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
 795         }
 796
 797         /* Nothing needs to be done for the encoder */
 798         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 799         if (crtc < 0)
 800                 goto ack;
 801         pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
 802
 803         /* Find which encoder is connected to the CRTC */
 804         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 805                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
 806                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 807                 if (!(mc & (1 << crtc)))
 808                         continue;
 809
 810                 switch ((mc & 0x00000f00) >> 8) {
 811                 case 0: type = OUTPUT_ANALOG; break;
 812                 case 1: type = OUTPUT_TV; break;
 813                 default:
 814                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 815                         goto ack;
 816                 }
 817
 818                 or = i;
 819         }
 820
 821         for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 822                 if (dev_priv->chipset  < 0x90 ||
 823                     dev_priv->chipset == 0x92 ||
 824                     dev_priv->chipset == 0xa0)
 825                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
 826                 else
 827                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
 828
 829                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 830                 if (!(mc & (1 << crtc)))
 831                         continue;
 832
 833                 switch ((mc & 0x00000f00) >> 8) {
 834                 case 0: type = OUTPUT_LVDS; break;
 835                 case 1: type = OUTPUT_TMDS; break;
 836                 case 2: type = OUTPUT_TMDS; break;
 837                 case 5: type = OUTPUT_TMDS; break;
 838                 case 8: type = OUTPUT_DP; break;
 839                 case 9: type = OUTPUT_DP; break;
 840                 default:
 841                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 842                         goto ack;
 843                 }
 844
 845                 or = i;
 846         }
 847
 848         if (type == OUTPUT_ANY)
 849                 goto ack;
 850
 851         /* Enable the encoder */
 852         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 853                 dcb = &dev_priv->vbios.dcb.entry[i];
 854                 if (dcb->type == type && (dcb->or & (1 << or)))
 855                         break;
 856         }
 857
 858         if (i == dev_priv->vbios.dcb.entries) {
 859                 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 860                 goto ack;
 861         }
 862
 863         script = nv50_display_script_select(dev, dcb, mc, pclk);
 864         nouveau_bios_run_display_table(dev, script, pclk, dcb, -1);
 865
 866         if (type == OUTPUT_DP) {
 867                 int link = !(dcb->dpconf.sor.link & 1);
 868                 if ((mc & 0x000f0000) == 0x00020000)
 869                         nv50_sor_dp_calc_tu(dev, or, link, pclk, 18);
 870                 else
 871                         nv50_sor_dp_calc_tu(dev, or, link, pclk, 24);
 872         }
 873
 874         if (dcb->type != OUTPUT_ANALOG) {
 875                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 876                 tmp &= ~0x00000f0f;
 877                 if (script & 0x0100)
 878                         tmp |= 0x00000101;
 879                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 880         } else {
 881                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 882         }
 883
 884         disp->irq.dcb = dcb;
 885         disp->irq.pclk = pclk;
 886         disp->irq.script = script;
 887
 888 ack:
 889         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 890         nv_wr32(dev, 0x610030, 0x80000000);
 891 }
 892
 893 /* If programming a TMDS output on a SOR that can also be configured for
 894  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 895  *
 896  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 897  * the VBIOS scripts on at least one board I have only switch it off on
 898  * link 0, causing a blank display if the output has previously been
 899  * programmed for DisplayPort.
 900  */
 901 static void
 902 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
 903 {
 904         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 905         struct drm_encoder *encoder;
 906         u32 tmp;
 907
 908         if (dcb->type != OUTPUT_TMDS)
 909                 return;
 910
 911         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 912                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 913
 914                 if (nv_encoder->dcb->type == OUTPUT_DP &&
 915                     nv_encoder->dcb->or & (1 << or)) {
 916                         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 917                         tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
 918                         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 919                         break;
 920                 }
 921         }
 922 }
 923
 924 static void
 925 nv50_display_unk40_handler(struct drm_device *dev)
 926 {
 927         struct nv50_display *disp = nv50_display(dev);
 928         struct dcb_entry *dcb = disp->irq.dcb;
 929         u16 script = disp->irq.script;
 930         u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk;
 931
 932         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 933         disp->irq.dcb = NULL;
 934         if (!dcb)
 935                 goto ack;
 936
 937         nouveau_bios_run_display_table(dev, script, -pclk, dcb, -1);
 938         nv50_display_unk40_dp_set_tmds(dev, dcb);
 939
 940 ack:
 941         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 942         nv_wr32(dev, 0x610030, 0x80000000);
 943         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 944 }
 945
 946 static void
 947 nv50_display_bh(unsigned long data)
 948 {
 949         struct drm_device *dev = (struct drm_device *)data;
 950
 951         for (;;) {
 952                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 953                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 954
 955                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 956
 957                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 958                         nv50_display_unk10_handler(dev);
 959                 else
 960                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 961                         nv50_display_unk20_handler(dev);
 962                 else
 963                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 964                         nv50_display_unk40_handler(dev);
 965                 else
 966                         break;
 967         }
 968
 969         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 970 }
 971
 972 static void
 973 nv50_display_error_handler(struct drm_device *dev)
 974 {
 975         u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
 976         u32 addr, data;
 977         int chid;
 978
 979         for (chid = 0; chid < 5; chid++) {
 980                 if (!(channels & (1 << chid)))
 981                         continue;
 982
 983                 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
 984                 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
 985                 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
 986                 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
 987                               "(0x%04x 0x%02x)\n", chid,
 988                          addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
 989
 990                 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
 991         }
 992 }
 993
 994 static void
 995 nv50_display_isr(struct drm_device *dev)
 996 {
 997         struct nv50_display *disp = nv50_display(dev);
 998         uint32_t delayed = 0;
 999
1000         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
1001                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
1002                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1003                 uint32_t clock;
1004
1005                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
1006
1007                 if (!intr0 && !(intr1 & ~delayed))
1008                         break;
1009
1010                 if (intr0 & 0x001f0000) {
1011                         nv50_display_error_handler(dev);
1012                         intr0 &= ~0x001f0000;
1013                 }
1014
1015                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1016                         nv50_display_vblank_handler(dev, intr1);
1017                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1018                 }
1019
1020                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1021                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1022                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
1023                 if (clock) {
1024                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1025                         tasklet_schedule(&disp->tasklet);
1026                         delayed |= clock;
1027                         intr1 &= ~clock;
1028                 }
1029
1030                 if (intr0) {
1031                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1032                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1033                 }
1034
1035                 if (intr1) {
1036                         NV_ERROR(dev,
1037                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1038                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1039                 }
1040         }
1041 }