2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/dma-mapping.h>
28 #include <drm/drm_crtc_helper.h>
30 #include "nouveau_drm.h"
31 #include "nouveau_dma.h"
32 #include "nouveau_gem.h"
33 #include "nouveau_connector.h"
34 #include "nouveau_encoder.h"
35 #include "nouveau_crtc.h"
36 #include "nouveau_fence.h"
37 #include "nv50_display.h"
39 #include <core/client.h>
40 #include <core/gpuobj.h>
41 #include <core/class.h>
43 #include <subdev/timer.h>
44 #include <subdev/bar.h>
45 #include <subdev/fb.h>
46 #include <subdev/i2c.h>
50 #define EVO_MASTER (0x00)
51 #define EVO_FLIP(c) (0x01 + (c))
52 #define EVO_OVLY(c) (0x05 + (c))
53 #define EVO_OIMM(c) (0x09 + (c))
54 #define EVO_CURS(c) (0x0d + (c))
56 /* offsets in shared sync bo of various structures */
57 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
58 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
59 #define EVO_FLIP_SEM0(c) EVO_SYNC((c), 0x00)
60 #define EVO_FLIP_SEM1(c) EVO_SYNC((c), 0x10)
62 #define EVO_CORE_HANDLE (0xd1500000)
63 #define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
64 #define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff))
65 #define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \
66 (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
68 /******************************************************************************
70 *****************************************************************************/
73 struct nouveau_object *user;
78 nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head,
79 void *data, u32 size, struct nv50_chan *chan)
81 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
82 const u32 oclass = EVO_CHAN_OCLASS(bclass, core);
83 const u32 handle = EVO_CHAN_HANDLE(bclass, head);
86 ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle,
87 oclass, data, size, &chan->user);
91 chan->handle = handle;
96 nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan)
98 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
100 nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle);
103 /******************************************************************************
105 *****************************************************************************/
108 struct nv50_chan base;
112 nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc)
114 nv50_chan_destroy(core, &pioc->base);
118 nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head,
119 void *data, u32 size, struct nv50_pioc *pioc)
121 return nv50_chan_create(core, bclass, head, data, size, &pioc->base);
124 /******************************************************************************
126 *****************************************************************************/
129 struct nv50_chan base;
133 /* Protects against concurrent pushbuf access to this channel, lock is
134 * grabbed by evo_wait (if the pushbuf reservation is successful) and
135 * dropped again by evo_kick. */
140 nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac)
143 struct pci_dev *pdev = nv_device(core)->pdev;
144 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
147 nv50_chan_destroy(core, &dmac->base);
151 nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
153 struct nouveau_fb *pfb = nouveau_fb(core);
154 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
155 struct nouveau_object *object;
156 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
157 NV_DMA_IN_MEMORY_CLASS,
158 &(struct nv_dma_class) {
159 .flags = NV_DMA_TARGET_VRAM |
162 .limit = pfb->ram.size - 1,
163 .conf0 = NV50_DMA_CONF0_ENABLE |
164 NV50_DMA_CONF0_PART_256,
165 }, sizeof(struct nv_dma_class), &object);
169 ret = nouveau_object_new(client, parent, NvEvoFB16,
170 NV_DMA_IN_MEMORY_CLASS,
171 &(struct nv_dma_class) {
172 .flags = NV_DMA_TARGET_VRAM |
175 .limit = pfb->ram.size - 1,
176 .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 |
177 NV50_DMA_CONF0_PART_256,
178 }, sizeof(struct nv_dma_class), &object);
182 ret = nouveau_object_new(client, parent, NvEvoFB32,
183 NV_DMA_IN_MEMORY_CLASS,
184 &(struct nv_dma_class) {
185 .flags = NV_DMA_TARGET_VRAM |
188 .limit = pfb->ram.size - 1,
189 .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a |
190 NV50_DMA_CONF0_PART_256,
191 }, sizeof(struct nv_dma_class), &object);
196 nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
198 struct nouveau_fb *pfb = nouveau_fb(core);
199 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
200 struct nouveau_object *object;
201 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
202 NV_DMA_IN_MEMORY_CLASS,
203 &(struct nv_dma_class) {
204 .flags = NV_DMA_TARGET_VRAM |
207 .limit = pfb->ram.size - 1,
208 .conf0 = NVC0_DMA_CONF0_ENABLE,
209 }, sizeof(struct nv_dma_class), &object);
213 ret = nouveau_object_new(client, parent, NvEvoFB16,
214 NV_DMA_IN_MEMORY_CLASS,
215 &(struct nv_dma_class) {
216 .flags = NV_DMA_TARGET_VRAM |
219 .limit = pfb->ram.size - 1,
220 .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
221 }, sizeof(struct nv_dma_class), &object);
225 ret = nouveau_object_new(client, parent, NvEvoFB32,
226 NV_DMA_IN_MEMORY_CLASS,
227 &(struct nv_dma_class) {
228 .flags = NV_DMA_TARGET_VRAM |
231 .limit = pfb->ram.size - 1,
232 .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
233 }, sizeof(struct nv_dma_class), &object);
238 nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
240 struct nouveau_fb *pfb = nouveau_fb(core);
241 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
242 struct nouveau_object *object;
243 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
244 NV_DMA_IN_MEMORY_CLASS,
245 &(struct nv_dma_class) {
246 .flags = NV_DMA_TARGET_VRAM |
249 .limit = pfb->ram.size - 1,
250 .conf0 = NVD0_DMA_CONF0_ENABLE |
251 NVD0_DMA_CONF0_PAGE_LP,
252 }, sizeof(struct nv_dma_class), &object);
256 ret = nouveau_object_new(client, parent, NvEvoFB32,
257 NV_DMA_IN_MEMORY_CLASS,
258 &(struct nv_dma_class) {
259 .flags = NV_DMA_TARGET_VRAM |
262 .limit = pfb->ram.size - 1,
263 .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe |
264 NVD0_DMA_CONF0_PAGE_LP,
265 }, sizeof(struct nv_dma_class), &object);
270 nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head,
271 void *data, u32 size, u64 syncbuf,
272 struct nv50_dmac *dmac)
274 struct nouveau_fb *pfb = nouveau_fb(core);
275 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
276 struct nouveau_object *object;
277 u32 pushbuf = *(u32 *)data;
280 mutex_init(&dmac->lock);
282 dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE,
287 ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf,
288 NV_DMA_FROM_MEMORY_CLASS,
289 &(struct nv_dma_class) {
290 .flags = NV_DMA_TARGET_PCI_US |
292 .start = dmac->handle + 0x0000,
293 .limit = dmac->handle + 0x0fff,
294 }, sizeof(struct nv_dma_class), &object);
298 ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base);
302 ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync,
303 NV_DMA_IN_MEMORY_CLASS,
304 &(struct nv_dma_class) {
305 .flags = NV_DMA_TARGET_VRAM |
307 .start = syncbuf + 0x0000,
308 .limit = syncbuf + 0x0fff,
309 }, sizeof(struct nv_dma_class), &object);
313 ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM,
314 NV_DMA_IN_MEMORY_CLASS,
315 &(struct nv_dma_class) {
316 .flags = NV_DMA_TARGET_VRAM |
319 .limit = pfb->ram.size - 1,
320 }, sizeof(struct nv_dma_class), &object);
324 if (nv_device(core)->card_type < NV_C0)
325 ret = nv50_dmac_create_fbdma(core, dmac->base.handle);
327 if (nv_device(core)->card_type < NV_D0)
328 ret = nvc0_dmac_create_fbdma(core, dmac->base.handle);
330 ret = nvd0_dmac_create_fbdma(core, dmac->base.handle);
335 struct nv50_dmac base;
339 struct nv50_pioc base;
343 struct nv50_dmac base;
351 struct nv50_dmac base;
355 struct nv50_pioc base;
359 struct nouveau_crtc base;
360 struct nv50_curs curs;
361 struct nv50_sync sync;
362 struct nv50_ovly ovly;
363 struct nv50_oimm oimm;
366 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
367 #define nv50_curs(c) (&nv50_head(c)->curs)
368 #define nv50_sync(c) (&nv50_head(c)->sync)
369 #define nv50_ovly(c) (&nv50_head(c)->ovly)
370 #define nv50_oimm(c) (&nv50_head(c)->oimm)
371 #define nv50_chan(c) (&(c)->base.base)
372 #define nv50_vers(c) nv_mclass(nv50_chan(c)->user)
375 struct nouveau_object *core;
376 struct nv50_mast mast;
380 struct nouveau_bo *sync;
383 static struct nv50_disp *
384 nv50_disp(struct drm_device *dev)
386 return nouveau_display(dev)->priv;
389 #define nv50_mast(d) (&nv50_disp(d)->mast)
391 static struct drm_crtc *
392 nv50_display_crtc_get(struct drm_encoder *encoder)
394 return nouveau_encoder(encoder)->crtc;
397 /******************************************************************************
398 * EVO channel helpers
399 *****************************************************************************/
401 evo_wait(void *evoc, int nr)
403 struct nv50_dmac *dmac = evoc;
404 u32 put = nv_ro32(dmac->base.user, 0x0000) / 4;
406 mutex_lock(&dmac->lock);
407 if (put + nr >= (PAGE_SIZE / 4) - 8) {
408 dmac->ptr[put] = 0x20000000;
410 nv_wo32(dmac->base.user, 0x0000, 0x00000000);
411 if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) {
412 mutex_unlock(&dmac->lock);
413 NV_ERROR(dmac->base.user, "channel stalled\n");
420 return dmac->ptr + put;
424 evo_kick(u32 *push, void *evoc)
426 struct nv50_dmac *dmac = evoc;
427 nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
428 mutex_unlock(&dmac->lock);
431 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
432 #define evo_data(p,d) *((p)++) = (d)
435 evo_sync_wait(void *data)
437 if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
444 evo_sync(struct drm_device *dev)
446 struct nouveau_device *device = nouveau_dev(dev);
447 struct nv50_disp *disp = nv50_disp(dev);
448 struct nv50_mast *mast = nv50_mast(dev);
449 u32 *push = evo_wait(mast, 8);
451 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
452 evo_mthd(push, 0x0084, 1);
453 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
454 evo_mthd(push, 0x0080, 2);
455 evo_data(push, 0x00000000);
456 evo_data(push, 0x00000000);
457 evo_kick(push, mast);
458 if (nv_wait_cb(device, evo_sync_wait, disp->sync))
465 /******************************************************************************
466 * Page flipping channel
467 *****************************************************************************/
469 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
471 return nv50_disp(dev)->sync;
475 nv50_display_flip_stop(struct drm_crtc *crtc)
477 struct nv50_sync *sync = nv50_sync(crtc);
480 push = evo_wait(sync, 8);
482 evo_mthd(push, 0x0084, 1);
483 evo_data(push, 0x00000000);
484 evo_mthd(push, 0x0094, 1);
485 evo_data(push, 0x00000000);
486 evo_mthd(push, 0x00c0, 1);
487 evo_data(push, 0x00000000);
488 evo_mthd(push, 0x0080, 1);
489 evo_data(push, 0x00000000);
490 evo_kick(push, sync);
495 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
496 struct nouveau_channel *chan, u32 swap_interval)
498 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
499 struct nv50_disp *disp = nv50_disp(crtc->dev);
500 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
501 struct nv50_sync *sync = nv50_sync(crtc);
506 if (swap_interval == 0)
507 swap_interval |= 0x100;
509 push = evo_wait(sync, 128);
510 if (unlikely(push == NULL))
513 /* synchronise with the rendering channel, if necessary */
515 ret = RING_SPACE(chan, 10);
519 if (nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
520 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
521 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
522 OUT_RING (chan, sync->sem.offset);
523 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
524 OUT_RING (chan, 0xf00d0000 | sync->sem.value);
525 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
526 OUT_RING (chan, sync->sem.offset ^ 0x10);
527 OUT_RING (chan, 0x74b1e000);
528 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
529 OUT_RING (chan, NvSema);
531 if (nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
532 u64 offset = nv84_fence_crtc(chan, nv_crtc->index);
533 offset += sync->sem.offset;
535 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
536 OUT_RING (chan, upper_32_bits(offset));
537 OUT_RING (chan, lower_32_bits(offset));
538 OUT_RING (chan, 0xf00d0000 | sync->sem.value);
539 OUT_RING (chan, 0x00000002);
540 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
541 OUT_RING (chan, upper_32_bits(offset));
542 OUT_RING (chan, lower_32_bits(offset ^ 0x10));
543 OUT_RING (chan, 0x74b1e000);
544 OUT_RING (chan, 0x00000001);
546 u64 offset = nv84_fence_crtc(chan, nv_crtc->index);
547 offset += sync->sem.offset;
549 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
550 OUT_RING (chan, upper_32_bits(offset));
551 OUT_RING (chan, lower_32_bits(offset));
552 OUT_RING (chan, 0xf00d0000 | sync->sem.value);
553 OUT_RING (chan, 0x00001002);
554 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
555 OUT_RING (chan, upper_32_bits(offset));
556 OUT_RING (chan, lower_32_bits(offset ^ 0x10));
557 OUT_RING (chan, 0x74b1e000);
558 OUT_RING (chan, 0x00001001);
563 nouveau_bo_wr32(disp->sync, sync->sem.offset / 4,
564 0xf00d0000 | sync->sem.value);
569 evo_mthd(push, 0x0100, 1);
570 evo_data(push, 0xfffe0000);
571 evo_mthd(push, 0x0084, 1);
572 evo_data(push, swap_interval);
573 if (!(swap_interval & 0x00000100)) {
574 evo_mthd(push, 0x00e0, 1);
575 evo_data(push, 0x40000000);
577 evo_mthd(push, 0x0088, 4);
578 evo_data(push, sync->sem.offset);
579 evo_data(push, 0xf00d0000 | sync->sem.value);
580 evo_data(push, 0x74b1e000);
581 evo_data(push, NvEvoSync);
582 evo_mthd(push, 0x00a0, 2);
583 evo_data(push, 0x00000000);
584 evo_data(push, 0x00000000);
585 evo_mthd(push, 0x00c0, 1);
586 evo_data(push, nv_fb->r_dma);
587 evo_mthd(push, 0x0110, 2);
588 evo_data(push, 0x00000000);
589 evo_data(push, 0x00000000);
590 if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
591 evo_mthd(push, 0x0800, 5);
592 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
594 evo_data(push, (fb->height << 16) | fb->width);
595 evo_data(push, nv_fb->r_pitch);
596 evo_data(push, nv_fb->r_format);
598 evo_mthd(push, 0x0400, 5);
599 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
601 evo_data(push, (fb->height << 16) | fb->width);
602 evo_data(push, nv_fb->r_pitch);
603 evo_data(push, nv_fb->r_format);
605 evo_mthd(push, 0x0080, 1);
606 evo_data(push, 0x00000000);
607 evo_kick(push, sync);
609 sync->sem.offset ^= 0x10;
614 /******************************************************************************
616 *****************************************************************************/
618 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
620 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
621 struct nouveau_connector *nv_connector;
622 struct drm_connector *connector;
623 u32 *push, mode = 0x00;
625 nv_connector = nouveau_crtc_connector_get(nv_crtc);
626 connector = &nv_connector->base;
627 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
628 if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
629 mode = DITHERING_MODE_DYNAMIC2X2;
631 mode = nv_connector->dithering_mode;
634 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
635 if (connector->display_info.bpc >= 8)
636 mode |= DITHERING_DEPTH_8BPC;
638 mode |= nv_connector->dithering_depth;
641 push = evo_wait(mast, 4);
643 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
644 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
645 evo_data(push, mode);
647 if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
648 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
649 evo_data(push, mode);
651 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
652 evo_data(push, mode);
656 evo_mthd(push, 0x0080, 1);
657 evo_data(push, 0x00000000);
659 evo_kick(push, mast);
666 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
668 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
669 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
670 struct drm_crtc *crtc = &nv_crtc->base;
671 struct nouveau_connector *nv_connector;
672 int mode = DRM_MODE_SCALE_NONE;
675 /* start off at the resolution we programmed the crtc for, this
676 * effectively handles NONE/FULL scaling
678 nv_connector = nouveau_crtc_connector_get(nv_crtc);
679 if (nv_connector && nv_connector->native_mode)
680 mode = nv_connector->scaling_mode;
682 if (mode != DRM_MODE_SCALE_NONE)
683 omode = nv_connector->native_mode;
687 oX = omode->hdisplay;
688 oY = omode->vdisplay;
689 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
692 /* add overscan compensation if necessary, will keep the aspect
693 * ratio the same as the backend mode unless overridden by the
694 * user setting both hborder and vborder properties.
696 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
697 (nv_connector->underscan == UNDERSCAN_AUTO &&
698 nv_connector->edid &&
699 drm_detect_hdmi_monitor(nv_connector->edid)))) {
700 u32 bX = nv_connector->underscan_hborder;
701 u32 bY = nv_connector->underscan_vborder;
702 u32 aspect = (oY << 19) / oX;
706 if (bY) oY -= (bY * 2);
707 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
709 oX -= (oX >> 4) + 32;
710 if (bY) oY -= (bY * 2);
711 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
715 /* handle CENTER/ASPECT scaling, taking into account the areas
716 * removed already for overscan compensation
719 case DRM_MODE_SCALE_CENTER:
720 oX = min((u32)umode->hdisplay, oX);
721 oY = min((u32)umode->vdisplay, oY);
723 case DRM_MODE_SCALE_ASPECT:
725 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
726 oX = ((oY * aspect) + (aspect / 2)) >> 19;
728 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
729 oY = ((oX * aspect) + (aspect / 2)) >> 19;
736 push = evo_wait(mast, 8);
738 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
739 /*XXX: SCALE_CTRL_ACTIVE??? */
740 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
741 evo_data(push, (oY << 16) | oX);
742 evo_data(push, (oY << 16) | oX);
743 evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
744 evo_data(push, 0x00000000);
745 evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
746 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
748 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
749 evo_data(push, (oY << 16) | oX);
750 evo_data(push, (oY << 16) | oX);
751 evo_data(push, (oY << 16) | oX);
752 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
753 evo_data(push, 0x00000000);
754 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
755 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
758 evo_kick(push, mast);
761 nv50_display_flip_stop(crtc);
762 nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
770 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
772 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
776 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
777 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
778 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
780 push = evo_wait(mast, 16);
782 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
783 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
784 evo_data(push, (hue << 20) | (vib << 8));
786 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
787 evo_data(push, (hue << 20) | (vib << 8));
791 evo_mthd(push, 0x0080, 1);
792 evo_data(push, 0x00000000);
794 evo_kick(push, mast);
801 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
802 int x, int y, bool update)
804 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
805 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
808 push = evo_wait(mast, 16);
810 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
811 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
812 evo_data(push, nvfb->nvbo->bo.offset >> 8);
813 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
814 evo_data(push, (fb->height << 16) | fb->width);
815 evo_data(push, nvfb->r_pitch);
816 evo_data(push, nvfb->r_format);
817 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
818 evo_data(push, (y << 16) | x);
819 if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
820 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
821 evo_data(push, nvfb->r_dma);
824 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
825 evo_data(push, nvfb->nvbo->bo.offset >> 8);
826 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
827 evo_data(push, (fb->height << 16) | fb->width);
828 evo_data(push, nvfb->r_pitch);
829 evo_data(push, nvfb->r_format);
830 evo_data(push, nvfb->r_dma);
831 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
832 evo_data(push, (y << 16) | x);
836 evo_mthd(push, 0x0080, 1);
837 evo_data(push, 0x00000000);
839 evo_kick(push, mast);
842 nv_crtc->fb.tile_flags = nvfb->r_dma;
847 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
849 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
850 u32 *push = evo_wait(mast, 16);
852 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
853 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
854 evo_data(push, 0x85000000);
855 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
857 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
858 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
859 evo_data(push, 0x85000000);
860 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
861 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
862 evo_data(push, NvEvoVRAM);
864 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
865 evo_data(push, 0x85000000);
866 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
867 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
868 evo_data(push, NvEvoVRAM);
870 evo_kick(push, mast);
875 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
877 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
878 u32 *push = evo_wait(mast, 16);
880 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
881 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
882 evo_data(push, 0x05000000);
884 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
885 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
886 evo_data(push, 0x05000000);
887 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
888 evo_data(push, 0x00000000);
890 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
891 evo_data(push, 0x05000000);
892 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
893 evo_data(push, 0x00000000);
895 evo_kick(push, mast);
900 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
902 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
905 nv50_crtc_cursor_show(nv_crtc);
907 nv50_crtc_cursor_hide(nv_crtc);
910 u32 *push = evo_wait(mast, 2);
912 evo_mthd(push, 0x0080, 1);
913 evo_data(push, 0x00000000);
914 evo_kick(push, mast);
920 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
925 nv50_crtc_prepare(struct drm_crtc *crtc)
927 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
928 struct nv50_mast *mast = nv50_mast(crtc->dev);
931 nv50_display_flip_stop(crtc);
933 push = evo_wait(mast, 2);
935 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
936 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
937 evo_data(push, 0x00000000);
938 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
939 evo_data(push, 0x40000000);
941 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
942 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
943 evo_data(push, 0x00000000);
944 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
945 evo_data(push, 0x40000000);
946 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
947 evo_data(push, 0x00000000);
949 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
950 evo_data(push, 0x00000000);
951 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
952 evo_data(push, 0x03000000);
953 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
954 evo_data(push, 0x00000000);
957 evo_kick(push, mast);
960 nv50_crtc_cursor_show_hide(nv_crtc, false, false);
964 nv50_crtc_commit(struct drm_crtc *crtc)
966 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
967 struct nv50_mast *mast = nv50_mast(crtc->dev);
970 push = evo_wait(mast, 32);
972 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
973 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
974 evo_data(push, NvEvoVRAM_LP);
975 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
976 evo_data(push, 0xc0000000);
977 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
979 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
980 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
981 evo_data(push, nv_crtc->fb.tile_flags);
982 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
983 evo_data(push, 0xc0000000);
984 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
985 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
986 evo_data(push, NvEvoVRAM);
988 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
989 evo_data(push, nv_crtc->fb.tile_flags);
990 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
991 evo_data(push, 0x83000000);
992 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
993 evo_data(push, 0x00000000);
994 evo_data(push, 0x00000000);
995 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
996 evo_data(push, NvEvoVRAM);
997 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
998 evo_data(push, 0xffffff00);
1001 evo_kick(push, mast);
1004 nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
1005 nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
1009 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1010 struct drm_display_mode *adjusted_mode)
1016 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1018 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
1021 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
1026 nvfb = nouveau_framebuffer(old_fb);
1027 nouveau_bo_unpin(nvfb->nvbo);
1034 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1035 struct drm_display_mode *mode, int x, int y,
1036 struct drm_framebuffer *old_fb)
1038 struct nv50_mast *mast = nv50_mast(crtc->dev);
1039 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1040 struct nouveau_connector *nv_connector;
1041 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1042 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1043 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1044 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1045 u32 vblan2e = 0, vblan2s = 1;
1049 hactive = mode->htotal;
1050 hsynce = mode->hsync_end - mode->hsync_start - 1;
1051 hbackp = mode->htotal - mode->hsync_end;
1052 hblanke = hsynce + hbackp;
1053 hfrontp = mode->hsync_start - mode->hdisplay;
1054 hblanks = mode->htotal - hfrontp - 1;
1056 vactive = mode->vtotal * vscan / ilace;
1057 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1058 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1059 vblanke = vsynce + vbackp;
1060 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1061 vblanks = vactive - vfrontp - 1;
1062 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1063 vblan2e = vactive + vsynce + vbackp;
1064 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1065 vactive = (vactive * 2) + 1;
1068 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1072 push = evo_wait(mast, 64);
1074 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1075 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1076 evo_data(push, 0x00800000 | mode->clock);
1077 evo_data(push, (ilace == 2) ? 2 : 0);
1078 evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1079 evo_data(push, 0x00000000);
1080 evo_data(push, (vactive << 16) | hactive);
1081 evo_data(push, ( vsynce << 16) | hsynce);
1082 evo_data(push, (vblanke << 16) | hblanke);
1083 evo_data(push, (vblanks << 16) | hblanks);
1084 evo_data(push, (vblan2e << 16) | vblan2s);
1085 evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1086 evo_data(push, 0x00000000);
1087 evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1088 evo_data(push, 0x00000311);
1089 evo_data(push, 0x00000100);
1091 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1092 evo_data(push, 0x00000000);
1093 evo_data(push, (vactive << 16) | hactive);
1094 evo_data(push, ( vsynce << 16) | hsynce);
1095 evo_data(push, (vblanke << 16) | hblanke);
1096 evo_data(push, (vblanks << 16) | hblanks);
1097 evo_data(push, (vblan2e << 16) | vblan2s);
1098 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1099 evo_data(push, 0x00000000); /* ??? */
1100 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1101 evo_data(push, mode->clock * 1000);
1102 evo_data(push, 0x00200000); /* ??? */
1103 evo_data(push, mode->clock * 1000);
1104 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1105 evo_data(push, 0x00000311);
1106 evo_data(push, 0x00000100);
1109 evo_kick(push, mast);
1112 nv_connector = nouveau_crtc_connector_get(nv_crtc);
1113 nv50_crtc_set_dither(nv_crtc, false);
1114 nv50_crtc_set_scale(nv_crtc, false);
1115 nv50_crtc_set_color_vibrance(nv_crtc, false);
1116 nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
1121 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1122 struct drm_framebuffer *old_fb)
1124 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1125 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1129 NV_DEBUG(drm, "No FB bound\n");
1133 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1137 nv50_display_flip_stop(crtc);
1138 nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
1139 nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
1144 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1145 struct drm_framebuffer *fb, int x, int y,
1146 enum mode_set_atomic state)
1148 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1149 nv50_display_flip_stop(crtc);
1150 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1155 nv50_crtc_lut_load(struct drm_crtc *crtc)
1157 struct nv50_disp *disp = nv50_disp(crtc->dev);
1158 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1159 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1162 for (i = 0; i < 256; i++) {
1163 u16 r = nv_crtc->lut.r[i] >> 2;
1164 u16 g = nv_crtc->lut.g[i] >> 2;
1165 u16 b = nv_crtc->lut.b[i] >> 2;
1167 if (nv_mclass(disp->core) < NVD0_DISP_CLASS) {
1168 writew(r + 0x0000, lut + (i * 0x08) + 0);
1169 writew(g + 0x0000, lut + (i * 0x08) + 2);
1170 writew(b + 0x0000, lut + (i * 0x08) + 4);
1172 writew(r + 0x6000, lut + (i * 0x20) + 0);
1173 writew(g + 0x6000, lut + (i * 0x20) + 2);
1174 writew(b + 0x6000, lut + (i * 0x20) + 4);
1180 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1181 uint32_t handle, uint32_t width, uint32_t height)
1183 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1184 struct drm_device *dev = crtc->dev;
1185 struct drm_gem_object *gem;
1186 struct nouveau_bo *nvbo;
1187 bool visible = (handle != 0);
1191 if (width != 64 || height != 64)
1194 gem = drm_gem_object_lookup(dev, file_priv, handle);
1197 nvbo = nouveau_gem_object(gem);
1199 ret = nouveau_bo_map(nvbo);
1201 for (i = 0; i < 64 * 64; i++) {
1202 u32 v = nouveau_bo_rd32(nvbo, i);
1203 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1205 nouveau_bo_unmap(nvbo);
1208 drm_gem_object_unreference_unlocked(gem);
1211 if (visible != nv_crtc->cursor.visible) {
1212 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
1213 nv_crtc->cursor.visible = visible;
1220 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1222 struct nv50_curs *curs = nv50_curs(crtc);
1223 struct nv50_chan *chan = nv50_chan(curs);
1224 nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff));
1225 nv_wo32(chan->user, 0x0080, 0x00000000);
1230 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1231 uint32_t start, uint32_t size)
1233 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1234 u32 end = max(start + size, (u32)256);
1237 for (i = start; i < end; i++) {
1238 nv_crtc->lut.r[i] = r[i];
1239 nv_crtc->lut.g[i] = g[i];
1240 nv_crtc->lut.b[i] = b[i];
1243 nv50_crtc_lut_load(crtc);
1247 nv50_crtc_destroy(struct drm_crtc *crtc)
1249 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1250 struct nv50_disp *disp = nv50_disp(crtc->dev);
1251 struct nv50_head *head = nv50_head(crtc);
1252 nv50_dmac_destroy(disp->core, &head->ovly.base);
1253 nv50_pioc_destroy(disp->core, &head->oimm.base);
1254 nv50_dmac_destroy(disp->core, &head->sync.base);
1255 nv50_pioc_destroy(disp->core, &head->curs.base);
1256 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
1257 if (nv_crtc->cursor.nvbo)
1258 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1259 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1260 nouveau_bo_unmap(nv_crtc->lut.nvbo);
1261 if (nv_crtc->lut.nvbo)
1262 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1263 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1264 drm_crtc_cleanup(crtc);
1268 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1269 .dpms = nv50_crtc_dpms,
1270 .prepare = nv50_crtc_prepare,
1271 .commit = nv50_crtc_commit,
1272 .mode_fixup = nv50_crtc_mode_fixup,
1273 .mode_set = nv50_crtc_mode_set,
1274 .mode_set_base = nv50_crtc_mode_set_base,
1275 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1276 .load_lut = nv50_crtc_lut_load,
1279 static const struct drm_crtc_funcs nv50_crtc_func = {
1280 .cursor_set = nv50_crtc_cursor_set,
1281 .cursor_move = nv50_crtc_cursor_move,
1282 .gamma_set = nv50_crtc_gamma_set,
1283 .set_config = drm_crtc_helper_set_config,
1284 .destroy = nv50_crtc_destroy,
1285 .page_flip = nouveau_crtc_page_flip,
1289 nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
1294 nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
1299 nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index)
1301 struct nv50_disp *disp = nv50_disp(dev);
1302 struct nv50_head *head;
1303 struct drm_crtc *crtc;
1306 head = kzalloc(sizeof(*head), GFP_KERNEL);
1310 head->base.index = index;
1311 head->base.set_dither = nv50_crtc_set_dither;
1312 head->base.set_scale = nv50_crtc_set_scale;
1313 head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1314 head->base.color_vibrance = 50;
1315 head->base.vibrant_hue = 0;
1316 head->base.cursor.set_offset = nv50_cursor_set_offset;
1317 head->base.cursor.set_pos = nv50_cursor_set_pos;
1318 for (i = 0; i < 256; i++) {
1319 head->base.lut.r[i] = i << 8;
1320 head->base.lut.g[i] = i << 8;
1321 head->base.lut.b[i] = i << 8;
1324 crtc = &head->base.base;
1325 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1326 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1327 drm_mode_crtc_set_gamma_size(crtc, 256);
1329 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1330 0, 0x0000, NULL, &head->base.lut.nvbo);
1332 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
1334 ret = nouveau_bo_map(head->base.lut.nvbo);
1336 nouveau_bo_unpin(head->base.lut.nvbo);
1339 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1345 nv50_crtc_lut_load(crtc);
1347 /* allocate cursor resources */
1348 ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index,
1349 &(struct nv50_display_curs_class) {
1351 }, sizeof(struct nv50_display_curs_class),
1356 ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
1357 0, 0x0000, NULL, &head->base.cursor.nvbo);
1359 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
1361 ret = nouveau_bo_map(head->base.cursor.nvbo);
1363 nouveau_bo_unpin(head->base.lut.nvbo);
1366 nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
1372 /* allocate page flip / sync resources */
1373 ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index,
1374 &(struct nv50_display_sync_class) {
1375 .pushbuf = EVO_PUSH_HANDLE(SYNC, index),
1377 }, sizeof(struct nv50_display_sync_class),
1378 disp->sync->bo.offset, &head->sync.base);
1382 head->sync.sem.offset = EVO_SYNC(1 + index, 0x00);
1384 /* allocate overlay resources */
1385 ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
1386 &(struct nv50_display_oimm_class) {
1388 }, sizeof(struct nv50_display_oimm_class),
1393 ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index,
1394 &(struct nv50_display_ovly_class) {
1395 .pushbuf = EVO_PUSH_HANDLE(OVLY, index),
1397 }, sizeof(struct nv50_display_ovly_class),
1398 disp->sync->bo.offset, &head->ovly.base);
1404 nv50_crtc_destroy(crtc);
1408 /******************************************************************************
1410 *****************************************************************************/
1412 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1414 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1415 struct nv50_disp *disp = nv50_disp(encoder->dev);
1416 int or = nv_encoder->or;
1419 dpms_ctrl = 0x00000000;
1420 if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
1421 dpms_ctrl |= 0x00000001;
1422 if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
1423 dpms_ctrl |= 0x00000004;
1425 nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl);
1429 nv50_dac_mode_fixup(struct drm_encoder *encoder,
1430 const struct drm_display_mode *mode,
1431 struct drm_display_mode *adjusted_mode)
1433 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1434 struct nouveau_connector *nv_connector;
1436 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1437 if (nv_connector && nv_connector->native_mode) {
1438 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1439 int id = adjusted_mode->base.id;
1440 *adjusted_mode = *nv_connector->native_mode;
1441 adjusted_mode->base.id = id;
1449 nv50_dac_commit(struct drm_encoder *encoder)
1454 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1455 struct drm_display_mode *adjusted_mode)
1457 struct nv50_mast *mast = nv50_mast(encoder->dev);
1458 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1459 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1462 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1464 push = evo_wait(mast, 8);
1466 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1467 u32 syncs = 0x00000000;
1469 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1470 syncs |= 0x00000001;
1471 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1472 syncs |= 0x00000002;
1474 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1475 evo_data(push, 1 << nv_crtc->index);
1476 evo_data(push, syncs);
1478 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1479 u32 syncs = 0x00000001;
1481 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1482 syncs |= 0x00000008;
1483 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1484 syncs |= 0x00000010;
1486 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1487 magic |= 0x00000001;
1489 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1490 evo_data(push, syncs);
1491 evo_data(push, magic);
1492 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1493 evo_data(push, 1 << nv_crtc->index);
1496 evo_kick(push, mast);
1499 nv_encoder->crtc = encoder->crtc;
1503 nv50_dac_disconnect(struct drm_encoder *encoder)
1505 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1506 struct nv50_mast *mast = nv50_mast(encoder->dev);
1507 const int or = nv_encoder->or;
1510 if (nv_encoder->crtc) {
1511 nv50_crtc_prepare(nv_encoder->crtc);
1513 push = evo_wait(mast, 4);
1515 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1516 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1517 evo_data(push, 0x00000000);
1519 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1520 evo_data(push, 0x00000000);
1523 evo_mthd(push, 0x0080, 1);
1524 evo_data(push, 0x00000000);
1525 evo_kick(push, mast);
1529 nv_encoder->crtc = NULL;
1532 static enum drm_connector_status
1533 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1535 struct nv50_disp *disp = nv50_disp(encoder->dev);
1536 int ret, or = nouveau_encoder(encoder)->or;
1539 ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
1540 if (ret || load != 7)
1541 return connector_status_disconnected;
1543 return connector_status_connected;
1547 nv50_dac_destroy(struct drm_encoder *encoder)
1549 drm_encoder_cleanup(encoder);
1553 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1554 .dpms = nv50_dac_dpms,
1555 .mode_fixup = nv50_dac_mode_fixup,
1556 .prepare = nv50_dac_disconnect,
1557 .commit = nv50_dac_commit,
1558 .mode_set = nv50_dac_mode_set,
1559 .disable = nv50_dac_disconnect,
1560 .get_crtc = nv50_display_crtc_get,
1561 .detect = nv50_dac_detect
1564 static const struct drm_encoder_funcs nv50_dac_func = {
1565 .destroy = nv50_dac_destroy,
1569 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1571 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1572 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1573 struct nouveau_encoder *nv_encoder;
1574 struct drm_encoder *encoder;
1575 int type = DRM_MODE_ENCODER_DAC;
1577 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1580 nv_encoder->dcb = dcbe;
1581 nv_encoder->or = ffs(dcbe->or) - 1;
1582 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1584 encoder = to_drm_encoder(nv_encoder);
1585 encoder->possible_crtcs = dcbe->heads;
1586 encoder->possible_clones = 0;
1587 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
1588 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1590 drm_mode_connector_attach_encoder(connector, encoder);
1594 /******************************************************************************
1596 *****************************************************************************/
1598 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1600 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1601 struct nouveau_connector *nv_connector;
1602 struct nv50_disp *disp = nv50_disp(encoder->dev);
1604 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1605 if (!drm_detect_monitor_audio(nv_connector->edid))
1608 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1610 nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
1611 nv_connector->base.eld,
1612 nv_connector->base.eld[2] * 4);
1616 nv50_audio_disconnect(struct drm_encoder *encoder)
1618 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1619 struct nv50_disp *disp = nv50_disp(encoder->dev);
1621 nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
1624 /******************************************************************************
1626 *****************************************************************************/
1628 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1630 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1631 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1632 struct nouveau_connector *nv_connector;
1633 struct nv50_disp *disp = nv50_disp(encoder->dev);
1634 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1635 u32 rekey = 56; /* binary driver, and tegra constant */
1638 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1639 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1642 max_ac_packet = mode->htotal - mode->hdisplay;
1643 max_ac_packet -= rekey;
1644 max_ac_packet -= 18; /* constant from tegra */
1645 max_ac_packet /= 32;
1647 nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff,
1648 NV84_DISP_SOR_HDMI_PWR_STATE_ON |
1649 (max_ac_packet << 16) | rekey);
1651 nv50_audio_mode_set(encoder, mode);
1655 nv50_hdmi_disconnect(struct drm_encoder *encoder)
1657 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1658 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1659 struct nv50_disp *disp = nv50_disp(encoder->dev);
1660 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1662 nv50_audio_disconnect(encoder);
1664 nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000);
1667 /******************************************************************************
1669 *****************************************************************************/
1671 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1673 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1674 struct drm_device *dev = encoder->dev;
1675 struct nv50_disp *disp = nv50_disp(dev);
1676 struct drm_encoder *partner;
1677 int or = nv_encoder->or;
1679 nv_encoder->last_dpms = mode;
1681 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1682 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1684 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1687 if (nv_partner != nv_encoder &&
1688 nv_partner->dcb->or == nv_encoder->dcb->or) {
1689 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1695 nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON));
1699 nv50_sor_mode_fixup(struct drm_encoder *encoder,
1700 const struct drm_display_mode *mode,
1701 struct drm_display_mode *adjusted_mode)
1703 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1704 struct nouveau_connector *nv_connector;
1706 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1707 if (nv_connector && nv_connector->native_mode) {
1708 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1709 int id = adjusted_mode->base.id;
1710 *adjusted_mode = *nv_connector->native_mode;
1711 adjusted_mode->base.id = id;
1719 nv50_sor_disconnect(struct drm_encoder *encoder)
1721 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1722 struct nv50_mast *mast = nv50_mast(encoder->dev);
1723 const int or = nv_encoder->or;
1726 if (nv_encoder->crtc) {
1727 nv50_crtc_prepare(nv_encoder->crtc);
1729 push = evo_wait(mast, 4);
1731 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1732 evo_mthd(push, 0x0600 + (or * 0x40), 1);
1733 evo_data(push, 0x00000000);
1735 evo_mthd(push, 0x0200 + (or * 0x20), 1);
1736 evo_data(push, 0x00000000);
1739 evo_mthd(push, 0x0080, 1);
1740 evo_data(push, 0x00000000);
1741 evo_kick(push, mast);
1744 nv50_hdmi_disconnect(encoder);
1747 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1748 nv_encoder->crtc = NULL;
1752 nv50_sor_commit(struct drm_encoder *encoder)
1757 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1758 struct drm_display_mode *mode)
1760 struct nv50_disp *disp = nv50_disp(encoder->dev);
1761 struct nv50_mast *mast = nv50_mast(encoder->dev);
1762 struct drm_device *dev = encoder->dev;
1763 struct nouveau_drm *drm = nouveau_drm(dev);
1764 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1765 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1766 struct nouveau_connector *nv_connector;
1767 struct nvbios *bios = &drm->vbios;
1768 u32 *push, lvds = 0;
1769 u8 owner = 1 << nv_crtc->index;
1773 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1774 switch (nv_encoder->dcb->type) {
1775 case DCB_OUTPUT_TMDS:
1776 if (nv_encoder->dcb->sorconf.link & 1) {
1777 if (mode->clock < 165000)
1785 nv50_hdmi_mode_set(encoder, mode);
1787 case DCB_OUTPUT_LVDS:
1790 if (bios->fp_no_ddc) {
1791 if (bios->fp.dual_link)
1793 if (bios->fp.if_is_24bit)
1796 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1797 if (((u8 *)nv_connector->edid)[121] == 2)
1800 if (mode->clock >= bios->fp.duallink_transition_clk) {
1804 if (lvds & 0x0100) {
1805 if (bios->fp.strapless_is_24bit & 2)
1808 if (bios->fp.strapless_is_24bit & 1)
1812 if (nv_connector->base.display_info.bpc == 8)
1816 nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds);
1819 if (nv_connector->base.display_info.bpc == 6) {
1820 nv_encoder->dp.datarate = mode->clock * 18 / 8;
1823 if (nv_connector->base.display_info.bpc == 8) {
1824 nv_encoder->dp.datarate = mode->clock * 24 / 8;
1827 nv_encoder->dp.datarate = mode->clock * 30 / 8;
1831 if (nv_encoder->dcb->sorconf.link & 1)
1841 nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
1843 push = evo_wait(nv50_mast(dev), 8);
1845 if (nv50_vers(mast) < NVD0_DISP_CLASS) {
1846 u32 ctrl = (depth << 16) | (proto << 8) | owner;
1847 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1849 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1851 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1);
1852 evo_data(push, ctrl);
1854 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1855 u32 syncs = 0x00000001;
1857 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1858 syncs |= 0x00000008;
1859 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1860 syncs |= 0x00000010;
1862 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1863 magic |= 0x00000001;
1865 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1866 evo_data(push, syncs | (depth << 6));
1867 evo_data(push, magic);
1868 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1);
1869 evo_data(push, owner | (proto << 8));
1872 evo_kick(push, mast);
1875 nv_encoder->crtc = encoder->crtc;
1879 nv50_sor_destroy(struct drm_encoder *encoder)
1881 drm_encoder_cleanup(encoder);
1885 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
1886 .dpms = nv50_sor_dpms,
1887 .mode_fixup = nv50_sor_mode_fixup,
1888 .prepare = nv50_sor_disconnect,
1889 .commit = nv50_sor_commit,
1890 .mode_set = nv50_sor_mode_set,
1891 .disable = nv50_sor_disconnect,
1892 .get_crtc = nv50_display_crtc_get,
1895 static const struct drm_encoder_funcs nv50_sor_func = {
1896 .destroy = nv50_sor_destroy,
1900 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1902 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1903 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1904 struct nouveau_encoder *nv_encoder;
1905 struct drm_encoder *encoder;
1908 switch (dcbe->type) {
1909 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1910 case DCB_OUTPUT_TMDS:
1913 type = DRM_MODE_ENCODER_TMDS;
1917 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1920 nv_encoder->dcb = dcbe;
1921 nv_encoder->or = ffs(dcbe->or) - 1;
1922 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1923 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1925 encoder = to_drm_encoder(nv_encoder);
1926 encoder->possible_crtcs = dcbe->heads;
1927 encoder->possible_clones = 0;
1928 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
1929 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
1931 drm_mode_connector_attach_encoder(connector, encoder);
1935 /******************************************************************************
1937 *****************************************************************************/
1940 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
1942 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1943 struct nv50_disp *disp = nv50_disp(encoder->dev);
1944 u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or;
1945 u32 ctrl = (mode == DRM_MODE_DPMS_ON);
1946 nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl);
1950 nv50_pior_mode_fixup(struct drm_encoder *encoder,
1951 const struct drm_display_mode *mode,
1952 struct drm_display_mode *adjusted_mode)
1954 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1955 struct nouveau_connector *nv_connector;
1957 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1958 if (nv_connector && nv_connector->native_mode) {
1959 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1960 int id = adjusted_mode->base.id;
1961 *adjusted_mode = *nv_connector->native_mode;
1962 adjusted_mode->base.id = id;
1966 adjusted_mode->clock *= 2;
1971 nv50_pior_commit(struct drm_encoder *encoder)
1976 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1977 struct drm_display_mode *adjusted_mode)
1979 struct nv50_mast *mast = nv50_mast(encoder->dev);
1980 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1981 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1982 struct nouveau_connector *nv_connector;
1983 u8 owner = 1 << nv_crtc->index;
1987 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1988 switch (nv_connector->base.display_info.bpc) {
1989 case 10: depth = 0x6; break;
1990 case 8: depth = 0x5; break;
1991 case 6: depth = 0x2; break;
1992 default: depth = 0x0; break;
1995 switch (nv_encoder->dcb->type) {
1996 case DCB_OUTPUT_TMDS:
2005 nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2007 push = evo_wait(mast, 8);
2009 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2010 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2011 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2013 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2015 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2016 evo_data(push, ctrl);
2019 evo_kick(push, mast);
2022 nv_encoder->crtc = encoder->crtc;
2026 nv50_pior_disconnect(struct drm_encoder *encoder)
2028 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2029 struct nv50_mast *mast = nv50_mast(encoder->dev);
2030 const int or = nv_encoder->or;
2033 if (nv_encoder->crtc) {
2034 nv50_crtc_prepare(nv_encoder->crtc);
2036 push = evo_wait(mast, 4);
2038 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2039 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2040 evo_data(push, 0x00000000);
2043 evo_mthd(push, 0x0080, 1);
2044 evo_data(push, 0x00000000);
2045 evo_kick(push, mast);
2049 nv_encoder->crtc = NULL;
2053 nv50_pior_destroy(struct drm_encoder *encoder)
2055 drm_encoder_cleanup(encoder);
2059 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2060 .dpms = nv50_pior_dpms,
2061 .mode_fixup = nv50_pior_mode_fixup,
2062 .prepare = nv50_pior_disconnect,
2063 .commit = nv50_pior_commit,
2064 .mode_set = nv50_pior_mode_set,
2065 .disable = nv50_pior_disconnect,
2066 .get_crtc = nv50_display_crtc_get,
2069 static const struct drm_encoder_funcs nv50_pior_func = {
2070 .destroy = nv50_pior_destroy,
2074 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2076 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2077 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
2078 struct nouveau_i2c_port *ddc = NULL;
2079 struct nouveau_encoder *nv_encoder;
2080 struct drm_encoder *encoder;
2083 switch (dcbe->type) {
2084 case DCB_OUTPUT_TMDS:
2085 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2086 type = DRM_MODE_ENCODER_TMDS;
2089 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2090 type = DRM_MODE_ENCODER_TMDS;
2096 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2099 nv_encoder->dcb = dcbe;
2100 nv_encoder->or = ffs(dcbe->or) - 1;
2101 nv_encoder->i2c = ddc;
2103 encoder = to_drm_encoder(nv_encoder);
2104 encoder->possible_crtcs = dcbe->heads;
2105 encoder->possible_clones = 0;
2106 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2107 drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2109 drm_mode_connector_attach_encoder(connector, encoder);
2113 /******************************************************************************
2115 *****************************************************************************/
2117 nv50_display_fini(struct drm_device *dev)
2122 nv50_display_init(struct drm_device *dev)
2124 u32 *push = evo_wait(nv50_mast(dev), 32);
2126 evo_mthd(push, 0x0088, 1);
2127 evo_data(push, NvEvoSync);
2128 evo_kick(push, nv50_mast(dev));
2136 nv50_display_destroy(struct drm_device *dev)
2138 struct nv50_disp *disp = nv50_disp(dev);
2140 nv50_dmac_destroy(disp->core, &disp->mast.base);
2142 nouveau_bo_unmap(disp->sync);
2144 nouveau_bo_unpin(disp->sync);
2145 nouveau_bo_ref(NULL, &disp->sync);
2147 nouveau_display(dev)->priv = NULL;
2152 nv50_display_create(struct drm_device *dev)
2154 static const u16 oclass[] = {
2163 struct nouveau_device *device = nouveau_dev(dev);
2164 struct nouveau_drm *drm = nouveau_drm(dev);
2165 struct dcb_table *dcb = &drm->vbios.dcb;
2166 struct drm_connector *connector, *tmp;
2167 struct nv50_disp *disp;
2168 struct dcb_output *dcbe;
2171 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2175 nouveau_display(dev)->priv = disp;
2176 nouveau_display(dev)->dtor = nv50_display_destroy;
2177 nouveau_display(dev)->init = nv50_display_init;
2178 nouveau_display(dev)->fini = nv50_display_fini;
2180 /* small shared memory area we use for notifiers and semaphores */
2181 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2182 0, 0x0000, NULL, &disp->sync);
2184 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2186 ret = nouveau_bo_map(disp->sync);
2188 nouveau_bo_unpin(disp->sync);
2191 nouveau_bo_ref(NULL, &disp->sync);
2197 /* attempt to allocate a supported evo display class */
2199 for (i = 0; ret && i < ARRAY_SIZE(oclass); i++) {
2200 ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE,
2201 0xd1500000, oclass[i], NULL, 0,
2208 /* allocate master evo channel */
2209 ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0,
2210 &(struct nv50_display_mast_class) {
2211 .pushbuf = EVO_PUSH_HANDLE(MAST, 0),
2212 }, sizeof(struct nv50_display_mast_class),
2213 disp->sync->bo.offset, &disp->mast.base);
2217 /* create crtc objects to represent the hw heads */
2218 if (nv_mclass(disp->core) >= NVD0_DISP_CLASS)
2219 crtcs = nv_rd32(device, 0x022448);
2223 for (i = 0; i < crtcs; i++) {
2224 ret = nv50_crtc_create(dev, disp->core, i);
2229 /* create encoder/connector objects based on VBIOS DCB table */
2230 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2231 connector = nouveau_connector_create(dev, dcbe->connector);
2232 if (IS_ERR(connector))
2235 if (dcbe->location == DCB_LOC_ON_CHIP) {
2236 switch (dcbe->type) {
2237 case DCB_OUTPUT_TMDS:
2238 case DCB_OUTPUT_LVDS:
2240 ret = nv50_sor_create(connector, dcbe);
2242 case DCB_OUTPUT_ANALOG:
2243 ret = nv50_dac_create(connector, dcbe);
2250 ret = nv50_pior_create(connector, dcbe);
2254 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2255 dcbe->location, dcbe->type,
2256 ffs(dcbe->or) - 1, ret);
2260 /* cull any connectors we created that don't have an encoder */
2261 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2262 if (connector->encoder_ids[0])
2265 NV_WARN(drm, "%s has no encoders, removing\n",
2266 drm_get_connector_name(connector));
2267 connector->funcs->destroy(connector);
2272 nv50_display_destroy(dev);