drivers/gpu/drm/nouveau/nv17_tv.c

   1 /*
   2  * Copyright (C) 2009 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_encoder.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_crtc.h"
  33 #include "nouveau_hw.h"
  34 #include "nv17_tv.h"
  35
  36 static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
  37 {
  38         struct drm_device *dev = encoder->dev;
  39         struct drm_nouveau_private *dev_priv = dev->dev_private;
  40         uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
  41         uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
  42                 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
  43         uint32_t sample = 0;
  44         int head;
  45
  46 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
  47         testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
  48         if (dev_priv->vbios.tvdactestval)
  49                 testval = dev_priv->vbios.tvdactestval;
  50
  51         dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
  52         head = (dacclk & 0x100) >> 8;
  53
  54         /* Save the previous state. */
  55         gpio1 = nv17_gpio_get(dev, DCB_GPIO_TVDAC1);
  56         gpio0 = nv17_gpio_get(dev, DCB_GPIO_TVDAC0);
  57         fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
  58         fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
  59         fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
  60         fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
  61         test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
  62         ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
  63         ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
  64         ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
  65
  66         /* Prepare the DAC for load detection.  */
  67         nv17_gpio_set(dev, DCB_GPIO_TVDAC1, true);
  68         nv17_gpio_set(dev, DCB_GPIO_TVDAC0, true);
  69
  70         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
  71         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
  72         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
  73         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
  74                       NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
  75                       NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
  76                       NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
  77                       NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
  78                       NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
  79
  80         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
  81
  82         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
  83                       (dacclk & ~0xff) | 0x22);
  84         msleep(1);
  85         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
  86                       (dacclk & ~0xff) | 0x21);
  87
  88         NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
  89         NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
  90
  91         /* Sample pin 0x4 (usually S-video luma). */
  92         NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
  93         msleep(20);
  94         sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
  95                 & 0x4 << 28;
  96
  97         /* Sample the remaining pins. */
  98         NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
  99         msleep(20);
 100         sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
 101                 & 0xa << 28;
 102
 103         /* Restore the previous state. */
 104         NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
 105         NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
 106         NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
 107         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
 108         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
 109         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
 110         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
 111         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
 112         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
 113         nv17_gpio_set(dev, DCB_GPIO_TVDAC1, gpio1);
 114         nv17_gpio_set(dev, DCB_GPIO_TVDAC0, gpio0);
 115
 116         return sample;
 117 }
 118
 119 static bool
 120 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
 121 {
 122         /* Zotac FX5200 */
 123         if (dev->pdev->device == 0x0322 &&
 124             dev->pdev->subsystem_vendor == 0x19da &&
 125             (dev->pdev->subsystem_device == 0x1035 ||
 126              dev->pdev->subsystem_device == 0x2035)) {
 127                 *pin_mask = 0xc;
 128                 return false;
 129         }
 130
 131         return true;
 132 }
 133
 134 static enum drm_connector_status
 135 nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 136 {
 137         struct drm_device *dev = encoder->dev;
 138         struct drm_nouveau_private *dev_priv = dev->dev_private;
 139         struct drm_mode_config *conf = &dev->mode_config;
 140         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 141         struct dcb_entry *dcb = tv_enc->base.dcb;
 142         bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
 143
 144         if (nv04_dac_in_use(encoder))
 145                 return connector_status_disconnected;
 146
 147         if (reliable) {
 148                 if (dev_priv->chipset == 0x42 ||
 149                     dev_priv->chipset == 0x43)
 150                         tv_enc->pin_mask =
 151                                 nv42_tv_sample_load(encoder) >> 28 & 0xe;
 152                 else
 153                         tv_enc->pin_mask =
 154                                 nv17_dac_sample_load(encoder) >> 28 & 0xe;
 155         }
 156
 157         switch (tv_enc->pin_mask) {
 158         case 0x2:
 159         case 0x4:
 160                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
 161                 break;
 162         case 0xc:
 163                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
 164                 break;
 165         case 0xe:
 166                 if (dcb->tvconf.has_component_output)
 167                         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
 168                 else
 169                         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
 170                 break;
 171         default:
 172                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 173                 break;
 174         }
 175
 176         drm_connector_property_set_value(connector,
 177                                          conf->tv_subconnector_property,
 178                                          tv_enc->subconnector);
 179
 180         if (!reliable) {
 181                 return connector_status_unknown;
 182         } else if (tv_enc->subconnector) {
 183                 NV_INFO(dev, "Load detected on output %c\n",
 184                         '@' + ffs(dcb->or));
 185                 return connector_status_connected;
 186         } else {
 187                 return connector_status_disconnected;
 188         }
 189 }
 190
 191 static const struct {
 192         int hdisplay;
 193         int vdisplay;
 194 } modes[] = {
 195         { 640, 400 },
 196         { 640, 480 },
 197         { 720, 480 },
 198         { 720, 576 },
 199         { 800, 600 },
 200         { 1024, 768 },
 201         { 1280, 720 },
 202         { 1280, 1024 },
 203         { 1920, 1080 }
 204 };
 205
 206 static int nv17_tv_get_modes(struct drm_encoder *encoder,
 207                              struct drm_connector *connector)
 208 {
 209         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 210         struct drm_display_mode *mode;
 211         struct drm_display_mode *output_mode;
 212         int n = 0;
 213         int i;
 214
 215         if (tv_norm->kind != CTV_ENC_MODE) {
 216                 struct drm_display_mode *tv_mode;
 217
 218                 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
 219                         mode = drm_mode_duplicate(encoder->dev, tv_mode);
 220
 221                         mode->clock = tv_norm->tv_enc_mode.vrefresh *
 222                                                 mode->htotal / 1000 *
 223                                                 mode->vtotal / 1000;
 224
 225                         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 226                                 mode->clock *= 2;
 227
 228                         if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
 229                             mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
 230                                 mode->type |= DRM_MODE_TYPE_PREFERRED;
 231
 232                         drm_mode_probed_add(connector, mode);
 233                         n++;
 234                 }
 235                 return n;
 236         }
 237
 238         /* tv_norm->kind == CTV_ENC_MODE */
 239         output_mode = &tv_norm->ctv_enc_mode.mode;
 240         for (i = 0; i < ARRAY_SIZE(modes); i++) {
 241                 if (modes[i].hdisplay > output_mode->hdisplay ||
 242                     modes[i].vdisplay > output_mode->vdisplay)
 243                         continue;
 244
 245                 if (modes[i].hdisplay == output_mode->hdisplay &&
 246                     modes[i].vdisplay == output_mode->vdisplay) {
 247                         mode = drm_mode_duplicate(encoder->dev, output_mode);
 248                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 249                 } else {
 250                         mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
 251                                 modes[i].vdisplay, 60, false,
 252                                 output_mode->flags & DRM_MODE_FLAG_INTERLACE,
 253                                 false);
 254                 }
 255
 256                 /* CVT modes are sometimes unsuitable... */
 257                 if (output_mode->hdisplay <= 720
 258                     || output_mode->hdisplay >= 1920) {
 259                         mode->htotal = output_mode->htotal;
 260                         mode->hsync_start = (mode->hdisplay + (mode->htotal
 261                                              - mode->hdisplay) * 9 / 10) & ~7;
 262                         mode->hsync_end = mode->hsync_start + 8;
 263                 }
 264                 if (output_mode->vdisplay >= 1024) {
 265                         mode->vtotal = output_mode->vtotal;
 266                         mode->vsync_start = output_mode->vsync_start;
 267                         mode->vsync_end = output_mode->vsync_end;
 268                 }
 269
 270                 mode->type |= DRM_MODE_TYPE_DRIVER;
 271                 drm_mode_probed_add(connector, mode);
 272                 n++;
 273         }
 274         return n;
 275 }
 276
 277 static int nv17_tv_mode_valid(struct drm_encoder *encoder,
 278                               struct drm_display_mode *mode)
 279 {
 280         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 281
 282         if (tv_norm->kind == CTV_ENC_MODE) {
 283                 struct drm_display_mode *output_mode =
 284                                                 &tv_norm->ctv_enc_mode.mode;
 285
 286                 if (mode->clock > 400000)
 287                         return MODE_CLOCK_HIGH;
 288
 289                 if (mode->hdisplay > output_mode->hdisplay ||
 290                     mode->vdisplay > output_mode->vdisplay)
 291                         return MODE_BAD;
 292
 293                 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
 294                     (output_mode->flags & DRM_MODE_FLAG_INTERLACE))
 295                         return MODE_NO_INTERLACE;
 296
 297                 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 298                         return MODE_NO_DBLESCAN;
 299
 300         } else {
 301                 const int vsync_tolerance = 600;
 302
 303                 if (mode->clock > 70000)
 304                         return MODE_CLOCK_HIGH;
 305
 306                 if (abs(drm_mode_vrefresh(mode) * 1000 -
 307                         tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
 308                         return MODE_VSYNC;
 309
 310                 /* The encoder takes care of the actual interlacing */
 311                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 312                         return MODE_NO_INTERLACE;
 313         }
 314
 315         return MODE_OK;
 316 }
 317
 318 static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
 319                                struct drm_display_mode *mode,
 320                                struct drm_display_mode *adjusted_mode)
 321 {
 322         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 323
 324         if (nv04_dac_in_use(encoder))
 325                 return false;
 326
 327         if (tv_norm->kind == CTV_ENC_MODE)
 328                 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
 329         else
 330                 adjusted_mode->clock = 90000;
 331
 332         return true;
 333 }
 334
 335 static void  nv17_tv_dpms(struct drm_encoder *encoder, int mode)
 336 {
 337         struct drm_device *dev = encoder->dev;
 338         struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
 339         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 340
 341         if (nouveau_encoder(encoder)->last_dpms == mode)
 342                 return;
 343         nouveau_encoder(encoder)->last_dpms = mode;
 344
 345         NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
 346                  mode, nouveau_encoder(encoder)->dcb->index);
 347
 348         regs->ptv_200 &= ~1;
 349
 350         if (tv_norm->kind == CTV_ENC_MODE) {
 351                 nv04_dfp_update_fp_control(encoder, mode);
 352
 353         } else {
 354                 nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
 355
 356                 if (mode == DRM_MODE_DPMS_ON)
 357                         regs->ptv_200 |= 1;
 358         }
 359
 360         nv_load_ptv(dev, regs, 200);
 361
 362         nv17_gpio_set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON);
 363         nv17_gpio_set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON);
 364
 365         nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
 366 }
 367
 368 static void nv17_tv_prepare(struct drm_encoder *encoder)
 369 {
 370         struct drm_device *dev = encoder->dev;
 371         struct drm_nouveau_private *dev_priv = dev->dev_private;
 372         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 373         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 374         int head = nouveau_crtc(encoder->crtc)->index;
 375         uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[
 376                                                         NV_CIO_CRE_LCD__INDEX];
 377         uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
 378                                         nv04_dac_output_offset(encoder);
 379         uint32_t dacclk;
 380
 381         helper->dpms(encoder, DRM_MODE_DPMS_OFF);
 382
 383         nv04_dfp_disable(dev, head);
 384
 385         /* Unbind any FP encoders from this head if we need the FP
 386          * stuff enabled. */
 387         if (tv_norm->kind == CTV_ENC_MODE) {
 388                 struct drm_encoder *enc;
 389
 390                 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
 391                         struct dcb_entry *dcb = nouveau_encoder(enc)->dcb;
 392
 393                         if ((dcb->type == OUTPUT_TMDS ||
 394                              dcb->type == OUTPUT_LVDS) &&
 395                              !enc->crtc &&
 396                              nv04_dfp_get_bound_head(dev, dcb) == head) {
 397                                 nv04_dfp_bind_head(dev, dcb, head ^ 1,
 398                                                 dev_priv->vbios.fp.dual_link);
 399                         }
 400                 }
 401
 402         }
 403
 404         /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
 405          * at LCD__INDEX which we don't alter
 406          */
 407         if (!(*cr_lcd & 0x44)) {
 408                 if (tv_norm->kind == CTV_ENC_MODE)
 409                         *cr_lcd = 0x1 | (head ? 0x0 : 0x8);
 410                 else
 411                         *cr_lcd = 0;
 412         }
 413
 414         /* Set the DACCLK register */
 415         dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
 416
 417         if (dev_priv->card_type == NV_40)
 418                 dacclk |= 0x1a << 16;
 419
 420         if (tv_norm->kind == CTV_ENC_MODE) {
 421                 dacclk |=  0x20;
 422
 423                 if (head)
 424                         dacclk |= 0x100;
 425                 else
 426                         dacclk &= ~0x100;
 427
 428         } else {
 429                 dacclk |= 0x10;
 430
 431         }
 432
 433         NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
 434 }
 435
 436 static void nv17_tv_mode_set(struct drm_encoder *encoder,
 437                              struct drm_display_mode *drm_mode,
 438                              struct drm_display_mode *adjusted_mode)
 439 {
 440         struct drm_device *dev = encoder->dev;
 441         struct drm_nouveau_private *dev_priv = dev->dev_private;
 442         int head = nouveau_crtc(encoder->crtc)->index;
 443         struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head];
 444         struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
 445         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 446         int i;
 447
 448         regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
 449         regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
 450         regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
 451         regs->tv_setup = 1;
 452         regs->ramdac_8c0 = 0x0;
 453
 454         if (tv_norm->kind == TV_ENC_MODE) {
 455                 tv_regs->ptv_200 = 0x13111100;
 456                 if (head)
 457                         tv_regs->ptv_200 |= 0x10;
 458
 459                 tv_regs->ptv_20c = 0x808010;
 460                 tv_regs->ptv_304 = 0x2d00000;
 461                 tv_regs->ptv_600 = 0x0;
 462                 tv_regs->ptv_60c = 0x0;
 463                 tv_regs->ptv_610 = 0x1e00000;
 464
 465                 if (tv_norm->tv_enc_mode.vdisplay == 576) {
 466                         tv_regs->ptv_508 = 0x1200000;
 467                         tv_regs->ptv_614 = 0x33;
 468
 469                 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
 470                         tv_regs->ptv_508 = 0xf00000;
 471                         tv_regs->ptv_614 = 0x13;
 472                 }
 473
 474                 if (dev_priv->card_type >= NV_30) {
 475                         tv_regs->ptv_500 = 0xe8e0;
 476                         tv_regs->ptv_504 = 0x1710;
 477                         tv_regs->ptv_604 = 0x0;
 478                         tv_regs->ptv_608 = 0x0;
 479                 } else {
 480                         if (tv_norm->tv_enc_mode.vdisplay == 576) {
 481                                 tv_regs->ptv_604 = 0x20;
 482                                 tv_regs->ptv_608 = 0x10;
 483                                 tv_regs->ptv_500 = 0x19710;
 484                                 tv_regs->ptv_504 = 0x68f0;
 485
 486                         } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
 487                                 tv_regs->ptv_604 = 0x10;
 488                                 tv_regs->ptv_608 = 0x20;
 489                                 tv_regs->ptv_500 = 0x4b90;
 490                                 tv_regs->ptv_504 = 0x1b480;
 491                         }
 492                 }
 493
 494                 for (i = 0; i < 0x40; i++)
 495                         tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
 496
 497         } else {
 498                 struct drm_display_mode *output_mode =
 499                                                 &tv_norm->ctv_enc_mode.mode;
 500
 501                 /* The registers in PRAMDAC+0xc00 control some timings and CSC
 502                  * parameters for the CTV encoder (It's only used for "HD" TV
 503                  * modes, I don't think I have enough working to guess what
 504                  * they exactly mean...), it's probably connected at the
 505                  * output of the FP encoder, but it also needs the analog
 506                  * encoder in its OR enabled and routed to the head it's
 507                  * using. It's enabled with the DACCLK register, bits [5:4].
 508                  */
 509                 for (i = 0; i < 38; i++)
 510                         regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
 511
 512                 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
 513                 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
 514                 regs->fp_horiz_regs[FP_SYNC_START] =
 515                                                 output_mode->hsync_start - 1;
 516                 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
 517                 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
 518                         max((output_mode->hdisplay-600)/40 - 1, 1);
 519
 520                 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
 521                 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
 522                 regs->fp_vert_regs[FP_SYNC_START] =
 523                                                 output_mode->vsync_start - 1;
 524                 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
 525                 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
 526
 527                 regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
 528                         NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
 529                         NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
 530
 531                 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
 532                         regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
 533                 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
 534                         regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
 535
 536                 regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
 537                         NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
 538                         NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
 539                         NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
 540                         NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
 541                         NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
 542                         NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
 543
 544                 regs->fp_debug_2 = 0;
 545
 546                 regs->fp_margin_color = 0x801080;
 547
 548         }
 549 }
 550
 551 static void nv17_tv_commit(struct drm_encoder *encoder)
 552 {
 553         struct drm_device *dev = encoder->dev;
 554         struct drm_nouveau_private *dev_priv = dev->dev_private;
 555         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 556         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 557         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 558
 559         if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
 560                 nv17_tv_update_rescaler(encoder);
 561                 nv17_tv_update_properties(encoder);
 562         } else {
 563                 nv17_ctv_update_rescaler(encoder);
 564         }
 565
 566         nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
 567
 568         /* This could use refinement for flatpanels, but it should work */
 569         if (dev_priv->chipset < 0x44)
 570                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
 571                                         nv04_dac_output_offset(encoder),
 572                                         0xf0000000);
 573         else
 574                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
 575                                         nv04_dac_output_offset(encoder),
 576                                         0x00100000);
 577
 578         helper->dpms(encoder, DRM_MODE_DPMS_ON);
 579
 580         NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
 581                 drm_get_connector_name(
 582                         &nouveau_encoder_connector_get(nv_encoder)->base),
 583                 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
 584 }
 585
 586 static void nv17_tv_save(struct drm_encoder *encoder)
 587 {
 588         struct drm_device *dev = encoder->dev;
 589         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 590
 591         nouveau_encoder(encoder)->restore.output =
 592                                         NVReadRAMDAC(dev, 0,
 593                                         NV_PRAMDAC_DACCLK +
 594                                         nv04_dac_output_offset(encoder));
 595
 596         nv17_tv_state_save(dev, &tv_enc->saved_state);
 597
 598         tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
 599 }
 600
 601 static void nv17_tv_restore(struct drm_encoder *encoder)
 602 {
 603         struct drm_device *dev = encoder->dev;
 604
 605         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
 606                                 nv04_dac_output_offset(encoder),
 607                                 nouveau_encoder(encoder)->restore.output);
 608
 609         nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
 610
 611         nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
 612 }
 613
 614 static int nv17_tv_create_resources(struct drm_encoder *encoder,
 615                                     struct drm_connector *connector)
 616 {
 617         struct drm_device *dev = encoder->dev;
 618         struct drm_mode_config *conf = &dev->mode_config;
 619         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 620         struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
 621         int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
 622                                                         NUM_LD_TV_NORMS;
 623         int i;
 624
 625         if (nouveau_tv_norm) {
 626                 for (i = 0; i < num_tv_norms; i++) {
 627                         if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) {
 628                                 tv_enc->tv_norm = i;
 629                                 break;
 630                         }
 631                 }
 632
 633                 if (i == num_tv_norms)
 634                         NV_WARN(dev, "Invalid TV norm setting \"%s\"\n",
 635                                 nouveau_tv_norm);
 636         }
 637
 638         drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
 639
 640         drm_connector_attach_property(connector,
 641                                         conf->tv_select_subconnector_property,
 642                                         tv_enc->select_subconnector);
 643         drm_connector_attach_property(connector,
 644                                         conf->tv_subconnector_property,
 645                                         tv_enc->subconnector);
 646         drm_connector_attach_property(connector,
 647                                         conf->tv_mode_property,
 648                                         tv_enc->tv_norm);
 649         drm_connector_attach_property(connector,
 650                                         conf->tv_flicker_reduction_property,
 651                                         tv_enc->flicker);
 652         drm_connector_attach_property(connector,
 653                                         conf->tv_saturation_property,
 654                                         tv_enc->saturation);
 655         drm_connector_attach_property(connector,
 656                                         conf->tv_hue_property,
 657                                         tv_enc->hue);
 658         drm_connector_attach_property(connector,
 659                                         conf->tv_overscan_property,
 660                                         tv_enc->overscan);
 661
 662         return 0;
 663 }
 664
 665 static int nv17_tv_set_property(struct drm_encoder *encoder,
 666                                 struct drm_connector *connector,
 667                                 struct drm_property *property,
 668                                 uint64_t val)
 669 {
 670         struct drm_mode_config *conf = &encoder->dev->mode_config;
 671         struct drm_crtc *crtc = encoder->crtc;
 672         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 673         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 674         bool modes_changed = false;
 675
 676         if (property == conf->tv_overscan_property) {
 677                 tv_enc->overscan = val;
 678                 if (encoder->crtc) {
 679                         if (tv_norm->kind == CTV_ENC_MODE)
 680                                 nv17_ctv_update_rescaler(encoder);
 681                         else
 682                                 nv17_tv_update_rescaler(encoder);
 683                 }
 684
 685         } else if (property == conf->tv_saturation_property) {
 686                 if (tv_norm->kind != TV_ENC_MODE)
 687                         return -EINVAL;
 688
 689                 tv_enc->saturation = val;
 690                 nv17_tv_update_properties(encoder);
 691
 692         } else if (property == conf->tv_hue_property) {
 693                 if (tv_norm->kind != TV_ENC_MODE)
 694                         return -EINVAL;
 695
 696                 tv_enc->hue = val;
 697                 nv17_tv_update_properties(encoder);
 698
 699         } else if (property == conf->tv_flicker_reduction_property) {
 700                 if (tv_norm->kind != TV_ENC_MODE)
 701                         return -EINVAL;
 702
 703                 tv_enc->flicker = val;
 704                 if (encoder->crtc)
 705                         nv17_tv_update_rescaler(encoder);
 706
 707         } else if (property == conf->tv_mode_property) {
 708                 if (connector->dpms != DRM_MODE_DPMS_OFF)
 709                         return -EINVAL;
 710
 711                 tv_enc->tv_norm = val;
 712
 713                 modes_changed = true;
 714
 715         } else if (property == conf->tv_select_subconnector_property) {
 716                 if (tv_norm->kind != TV_ENC_MODE)
 717                         return -EINVAL;
 718
 719                 tv_enc->select_subconnector = val;
 720                 nv17_tv_update_properties(encoder);
 721
 722         } else {
 723                 return -EINVAL;
 724         }
 725
 726         if (modes_changed) {
 727                 drm_helper_probe_single_connector_modes(connector, 0, 0);
 728
 729                 /* Disable the crtc to ensure a full modeset is
 730                  * performed whenever it's turned on again. */
 731                 if (crtc) {
 732                         struct drm_mode_set modeset = {
 733                                 .crtc = crtc,
 734                         };
 735
 736                         crtc->funcs->set_config(&modeset);
 737                 }
 738         }
 739
 740         return 0;
 741 }
 742
 743 static void nv17_tv_destroy(struct drm_encoder *encoder)
 744 {
 745         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 746
 747         NV_DEBUG_KMS(encoder->dev, "\n");
 748
 749         drm_encoder_cleanup(encoder);
 750         kfree(tv_enc);
 751 }
 752
 753 static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
 754         .dpms = nv17_tv_dpms,
 755         .save = nv17_tv_save,
 756         .restore = nv17_tv_restore,
 757         .mode_fixup = nv17_tv_mode_fixup,
 758         .prepare = nv17_tv_prepare,
 759         .commit = nv17_tv_commit,
 760         .mode_set = nv17_tv_mode_set,
 761         .detect = nv17_tv_detect,
 762 };
 763
 764 static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
 765         .get_modes = nv17_tv_get_modes,
 766         .mode_valid = nv17_tv_mode_valid,
 767         .create_resources = nv17_tv_create_resources,
 768         .set_property = nv17_tv_set_property,
 769 };
 770
 771 static struct drm_encoder_funcs nv17_tv_funcs = {
 772         .destroy = nv17_tv_destroy,
 773 };
 774
 775 int
 776 nv17_tv_create(struct drm_connector *connector, struct dcb_entry *entry)
 777 {
 778         struct drm_device *dev = connector->dev;
 779         struct drm_encoder *encoder;
 780         struct nv17_tv_encoder *tv_enc = NULL;
 781
 782         tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
 783         if (!tv_enc)
 784                 return -ENOMEM;
 785
 786         tv_enc->overscan = 50;
 787         tv_enc->flicker = 50;
 788         tv_enc->saturation = 50;
 789         tv_enc->hue = 0;
 790         tv_enc->tv_norm = TV_NORM_PAL;
 791         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 792         tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
 793         tv_enc->pin_mask = 0;
 794
 795         encoder = to_drm_encoder(&tv_enc->base);
 796
 797         tv_enc->base.dcb = entry;
 798         tv_enc->base.or = ffs(entry->or) - 1;
 799
 800         drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC);
 801         drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
 802         to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
 803
 804         encoder->possible_crtcs = entry->heads;
 805         encoder->possible_clones = 0;
 806
 807         nv17_tv_create_resources(encoder, connector);
 808         drm_mode_connector_attach_encoder(connector, encoder);
 809         return 0;
 810 }