2 * Copyright (C) 2009 Francisco Jerez.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "drm_crtc_helper.h"
29 #include "nouveau_drv.h"
30 #include "nouveau_encoder.h"
31 #include "nouveau_connector.h"
32 #include "nouveau_crtc.h"
33 #include "nouveau_hw.h"
36 static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
38 struct drm_device *dev = encoder->dev;
39 struct drm_nouveau_private *dev_priv = dev->dev_private;
40 struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
41 uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
42 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
43 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
47 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
48 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
49 if (dev_priv->vbios.tvdactestval)
50 testval = dev_priv->vbios.tvdactestval;
52 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
53 head = (dacclk & 0x100) >> 8;
55 /* Save the previous state. */
56 gpio1 = gpio->get(dev, DCB_GPIO_TVDAC1);
57 gpio0 = gpio->get(dev, DCB_GPIO_TVDAC0);
58 fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
59 fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
60 fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
61 fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
62 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
63 ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
64 ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
65 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
67 /* Prepare the DAC for load detection. */
68 gpio->set(dev, DCB_GPIO_TVDAC1, true);
69 gpio->set(dev, DCB_GPIO_TVDAC0, true);
71 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
72 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
73 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
74 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
75 NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
76 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
77 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
78 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
79 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
81 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
83 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
84 (dacclk & ~0xff) | 0x22);
86 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
87 (dacclk & ~0xff) | 0x21);
89 NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
90 NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
92 /* Sample pin 0x4 (usually S-video luma). */
93 NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
95 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
98 /* Sample the remaining pins. */
99 NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
101 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
104 /* Restore the previous state. */
105 NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
106 NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
107 NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
108 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
109 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
110 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
111 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
112 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
113 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
114 gpio->set(dev, DCB_GPIO_TVDAC1, gpio1);
115 gpio->set(dev, DCB_GPIO_TVDAC0, gpio0);
121 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
124 if (nv_match_device(dev, 0x0322, 0x19da, 0x1035) ||
125 nv_match_device(dev, 0x0322, 0x19da, 0x2035)) {
130 /* MSI nForce2 IGP */
131 if (nv_match_device(dev, 0x01f0, 0x1462, 0x5710)) {
139 static enum drm_connector_status
140 nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
142 struct drm_device *dev = encoder->dev;
143 struct drm_nouveau_private *dev_priv = dev->dev_private;
144 struct drm_mode_config *conf = &dev->mode_config;
145 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
146 struct dcb_entry *dcb = tv_enc->base.dcb;
147 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
149 if (nv04_dac_in_use(encoder))
150 return connector_status_disconnected;
153 if (dev_priv->chipset == 0x42 ||
154 dev_priv->chipset == 0x43)
156 nv42_tv_sample_load(encoder) >> 28 & 0xe;
159 nv17_dac_sample_load(encoder) >> 28 & 0xe;
162 switch (tv_enc->pin_mask) {
165 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
168 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
171 if (dcb->tvconf.has_component_output)
172 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
174 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
177 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
181 drm_connector_property_set_value(connector,
182 conf->tv_subconnector_property,
183 tv_enc->subconnector);
186 return connector_status_unknown;
187 } else if (tv_enc->subconnector) {
188 NV_INFO(dev, "Load detected on output %c\n",
190 return connector_status_connected;
192 return connector_status_disconnected;
196 static const struct {
211 static int nv17_tv_get_modes(struct drm_encoder *encoder,
212 struct drm_connector *connector)
214 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
215 struct drm_display_mode *mode;
216 struct drm_display_mode *output_mode;
220 if (tv_norm->kind != CTV_ENC_MODE) {
221 struct drm_display_mode *tv_mode;
223 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
224 mode = drm_mode_duplicate(encoder->dev, tv_mode);
226 mode->clock = tv_norm->tv_enc_mode.vrefresh *
227 mode->htotal / 1000 *
230 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
233 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
234 mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
235 mode->type |= DRM_MODE_TYPE_PREFERRED;
237 drm_mode_probed_add(connector, mode);
243 /* tv_norm->kind == CTV_ENC_MODE */
244 output_mode = &tv_norm->ctv_enc_mode.mode;
245 for (i = 0; i < ARRAY_SIZE(modes); i++) {
246 if (modes[i].hdisplay > output_mode->hdisplay ||
247 modes[i].vdisplay > output_mode->vdisplay)
250 if (modes[i].hdisplay == output_mode->hdisplay &&
251 modes[i].vdisplay == output_mode->vdisplay) {
252 mode = drm_mode_duplicate(encoder->dev, output_mode);
253 mode->type |= DRM_MODE_TYPE_PREFERRED;
255 mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
256 modes[i].vdisplay, 60, false,
257 output_mode->flags & DRM_MODE_FLAG_INTERLACE,
261 /* CVT modes are sometimes unsuitable... */
262 if (output_mode->hdisplay <= 720
263 || output_mode->hdisplay >= 1920) {
264 mode->htotal = output_mode->htotal;
265 mode->hsync_start = (mode->hdisplay + (mode->htotal
266 - mode->hdisplay) * 9 / 10) & ~7;
267 mode->hsync_end = mode->hsync_start + 8;
269 if (output_mode->vdisplay >= 1024) {
270 mode->vtotal = output_mode->vtotal;
271 mode->vsync_start = output_mode->vsync_start;
272 mode->vsync_end = output_mode->vsync_end;
275 mode->type |= DRM_MODE_TYPE_DRIVER;
276 drm_mode_probed_add(connector, mode);
282 static int nv17_tv_mode_valid(struct drm_encoder *encoder,
283 struct drm_display_mode *mode)
285 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
287 if (tv_norm->kind == CTV_ENC_MODE) {
288 struct drm_display_mode *output_mode =
289 &tv_norm->ctv_enc_mode.mode;
291 if (mode->clock > 400000)
292 return MODE_CLOCK_HIGH;
294 if (mode->hdisplay > output_mode->hdisplay ||
295 mode->vdisplay > output_mode->vdisplay)
298 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
299 (output_mode->flags & DRM_MODE_FLAG_INTERLACE))
300 return MODE_NO_INTERLACE;
302 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
303 return MODE_NO_DBLESCAN;
306 const int vsync_tolerance = 600;
308 if (mode->clock > 70000)
309 return MODE_CLOCK_HIGH;
311 if (abs(drm_mode_vrefresh(mode) * 1000 -
312 tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
315 /* The encoder takes care of the actual interlacing */
316 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
317 return MODE_NO_INTERLACE;
323 static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
324 struct drm_display_mode *mode,
325 struct drm_display_mode *adjusted_mode)
327 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
329 if (nv04_dac_in_use(encoder))
332 if (tv_norm->kind == CTV_ENC_MODE)
333 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
335 adjusted_mode->clock = 90000;
340 static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
342 struct drm_device *dev = encoder->dev;
343 struct drm_nouveau_private *dev_priv = dev->dev_private;
344 struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
345 struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
346 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
348 if (nouveau_encoder(encoder)->last_dpms == mode)
350 nouveau_encoder(encoder)->last_dpms = mode;
352 NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
353 mode, nouveau_encoder(encoder)->dcb->index);
357 if (tv_norm->kind == CTV_ENC_MODE) {
358 nv04_dfp_update_fp_control(encoder, mode);
361 nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
363 if (mode == DRM_MODE_DPMS_ON)
367 nv_load_ptv(dev, regs, 200);
369 gpio->set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON);
370 gpio->set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON);
372 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
375 static void nv17_tv_prepare(struct drm_encoder *encoder)
377 struct drm_device *dev = encoder->dev;
378 struct drm_nouveau_private *dev_priv = dev->dev_private;
379 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
380 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
381 int head = nouveau_crtc(encoder->crtc)->index;
382 uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[
383 NV_CIO_CRE_LCD__INDEX];
384 uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
385 nv04_dac_output_offset(encoder);
388 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
390 nv04_dfp_disable(dev, head);
392 /* Unbind any FP encoders from this head if we need the FP
394 if (tv_norm->kind == CTV_ENC_MODE) {
395 struct drm_encoder *enc;
397 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
398 struct dcb_entry *dcb = nouveau_encoder(enc)->dcb;
400 if ((dcb->type == OUTPUT_TMDS ||
401 dcb->type == OUTPUT_LVDS) &&
403 nv04_dfp_get_bound_head(dev, dcb) == head) {
404 nv04_dfp_bind_head(dev, dcb, head ^ 1,
405 dev_priv->vbios.fp.dual_link);
411 if (tv_norm->kind == CTV_ENC_MODE)
412 *cr_lcd = 0x1 | (head ? 0x0 : 0x8);
416 /* Set the DACCLK register */
417 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
419 if (dev_priv->card_type == NV_40)
420 dacclk |= 0x1a << 16;
422 if (tv_norm->kind == CTV_ENC_MODE) {
435 NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
438 static void nv17_tv_mode_set(struct drm_encoder *encoder,
439 struct drm_display_mode *drm_mode,
440 struct drm_display_mode *adjusted_mode)
442 struct drm_device *dev = encoder->dev;
443 struct drm_nouveau_private *dev_priv = dev->dev_private;
444 int head = nouveau_crtc(encoder->crtc)->index;
445 struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head];
446 struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
447 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
450 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
451 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
452 regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
454 regs->ramdac_8c0 = 0x0;
456 if (tv_norm->kind == TV_ENC_MODE) {
457 tv_regs->ptv_200 = 0x13111100;
459 tv_regs->ptv_200 |= 0x10;
461 tv_regs->ptv_20c = 0x808010;
462 tv_regs->ptv_304 = 0x2d00000;
463 tv_regs->ptv_600 = 0x0;
464 tv_regs->ptv_60c = 0x0;
465 tv_regs->ptv_610 = 0x1e00000;
467 if (tv_norm->tv_enc_mode.vdisplay == 576) {
468 tv_regs->ptv_508 = 0x1200000;
469 tv_regs->ptv_614 = 0x33;
471 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
472 tv_regs->ptv_508 = 0xf00000;
473 tv_regs->ptv_614 = 0x13;
476 if (dev_priv->card_type >= NV_30) {
477 tv_regs->ptv_500 = 0xe8e0;
478 tv_regs->ptv_504 = 0x1710;
479 tv_regs->ptv_604 = 0x0;
480 tv_regs->ptv_608 = 0x0;
482 if (tv_norm->tv_enc_mode.vdisplay == 576) {
483 tv_regs->ptv_604 = 0x20;
484 tv_regs->ptv_608 = 0x10;
485 tv_regs->ptv_500 = 0x19710;
486 tv_regs->ptv_504 = 0x68f0;
488 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
489 tv_regs->ptv_604 = 0x10;
490 tv_regs->ptv_608 = 0x20;
491 tv_regs->ptv_500 = 0x4b90;
492 tv_regs->ptv_504 = 0x1b480;
496 for (i = 0; i < 0x40; i++)
497 tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
500 struct drm_display_mode *output_mode =
501 &tv_norm->ctv_enc_mode.mode;
503 /* The registers in PRAMDAC+0xc00 control some timings and CSC
504 * parameters for the CTV encoder (It's only used for "HD" TV
505 * modes, I don't think I have enough working to guess what
506 * they exactly mean...), it's probably connected at the
507 * output of the FP encoder, but it also needs the analog
508 * encoder in its OR enabled and routed to the head it's
509 * using. It's enabled with the DACCLK register, bits [5:4].
511 for (i = 0; i < 38; i++)
512 regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
514 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
515 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
516 regs->fp_horiz_regs[FP_SYNC_START] =
517 output_mode->hsync_start - 1;
518 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
519 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
520 max((output_mode->hdisplay-600)/40 - 1, 1);
522 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
523 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
524 regs->fp_vert_regs[FP_SYNC_START] =
525 output_mode->vsync_start - 1;
526 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
527 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
529 regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
530 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
531 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
533 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
534 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
535 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
536 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
538 regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
539 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
540 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
541 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
542 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
543 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
544 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
546 regs->fp_debug_2 = 0;
548 regs->fp_margin_color = 0x801080;
553 static void nv17_tv_commit(struct drm_encoder *encoder)
555 struct drm_device *dev = encoder->dev;
556 struct drm_nouveau_private *dev_priv = dev->dev_private;
557 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
558 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
559 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
561 if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
562 nv17_tv_update_rescaler(encoder);
563 nv17_tv_update_properties(encoder);
565 nv17_ctv_update_rescaler(encoder);
568 nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
570 /* This could use refinement for flatpanels, but it should work */
571 if (dev_priv->chipset < 0x44)
572 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
573 nv04_dac_output_offset(encoder),
576 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
577 nv04_dac_output_offset(encoder),
580 helper->dpms(encoder, DRM_MODE_DPMS_ON);
582 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
583 drm_get_connector_name(
584 &nouveau_encoder_connector_get(nv_encoder)->base),
585 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
588 static void nv17_tv_save(struct drm_encoder *encoder)
590 struct drm_device *dev = encoder->dev;
591 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
593 nouveau_encoder(encoder)->restore.output =
596 nv04_dac_output_offset(encoder));
598 nv17_tv_state_save(dev, &tv_enc->saved_state);
600 tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
603 static void nv17_tv_restore(struct drm_encoder *encoder)
605 struct drm_device *dev = encoder->dev;
607 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
608 nv04_dac_output_offset(encoder),
609 nouveau_encoder(encoder)->restore.output);
611 nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
613 nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
616 static int nv17_tv_create_resources(struct drm_encoder *encoder,
617 struct drm_connector *connector)
619 struct drm_device *dev = encoder->dev;
620 struct drm_mode_config *conf = &dev->mode_config;
621 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
622 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
623 int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
627 if (nouveau_tv_norm) {
628 for (i = 0; i < num_tv_norms; i++) {
629 if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) {
635 if (i == num_tv_norms)
636 NV_WARN(dev, "Invalid TV norm setting \"%s\"\n",
640 drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
642 drm_connector_attach_property(connector,
643 conf->tv_select_subconnector_property,
644 tv_enc->select_subconnector);
645 drm_connector_attach_property(connector,
646 conf->tv_subconnector_property,
647 tv_enc->subconnector);
648 drm_connector_attach_property(connector,
649 conf->tv_mode_property,
651 drm_connector_attach_property(connector,
652 conf->tv_flicker_reduction_property,
654 drm_connector_attach_property(connector,
655 conf->tv_saturation_property,
657 drm_connector_attach_property(connector,
658 conf->tv_hue_property,
660 drm_connector_attach_property(connector,
661 conf->tv_overscan_property,
667 static int nv17_tv_set_property(struct drm_encoder *encoder,
668 struct drm_connector *connector,
669 struct drm_property *property,
672 struct drm_mode_config *conf = &encoder->dev->mode_config;
673 struct drm_crtc *crtc = encoder->crtc;
674 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
675 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
676 bool modes_changed = false;
678 if (property == conf->tv_overscan_property) {
679 tv_enc->overscan = val;
681 if (tv_norm->kind == CTV_ENC_MODE)
682 nv17_ctv_update_rescaler(encoder);
684 nv17_tv_update_rescaler(encoder);
687 } else if (property == conf->tv_saturation_property) {
688 if (tv_norm->kind != TV_ENC_MODE)
691 tv_enc->saturation = val;
692 nv17_tv_update_properties(encoder);
694 } else if (property == conf->tv_hue_property) {
695 if (tv_norm->kind != TV_ENC_MODE)
699 nv17_tv_update_properties(encoder);
701 } else if (property == conf->tv_flicker_reduction_property) {
702 if (tv_norm->kind != TV_ENC_MODE)
705 tv_enc->flicker = val;
707 nv17_tv_update_rescaler(encoder);
709 } else if (property == conf->tv_mode_property) {
710 if (connector->dpms != DRM_MODE_DPMS_OFF)
713 tv_enc->tv_norm = val;
715 modes_changed = true;
717 } else if (property == conf->tv_select_subconnector_property) {
718 if (tv_norm->kind != TV_ENC_MODE)
721 tv_enc->select_subconnector = val;
722 nv17_tv_update_properties(encoder);
729 drm_helper_probe_single_connector_modes(connector, 0, 0);
731 /* Disable the crtc to ensure a full modeset is
732 * performed whenever it's turned on again. */
734 struct drm_mode_set modeset = {
738 crtc->funcs->set_config(&modeset);
745 static void nv17_tv_destroy(struct drm_encoder *encoder)
747 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
749 NV_DEBUG_KMS(encoder->dev, "\n");
751 drm_encoder_cleanup(encoder);
755 static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
756 .dpms = nv17_tv_dpms,
757 .save = nv17_tv_save,
758 .restore = nv17_tv_restore,
759 .mode_fixup = nv17_tv_mode_fixup,
760 .prepare = nv17_tv_prepare,
761 .commit = nv17_tv_commit,
762 .mode_set = nv17_tv_mode_set,
763 .detect = nv17_tv_detect,
766 static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
767 .get_modes = nv17_tv_get_modes,
768 .mode_valid = nv17_tv_mode_valid,
769 .create_resources = nv17_tv_create_resources,
770 .set_property = nv17_tv_set_property,
773 static struct drm_encoder_funcs nv17_tv_funcs = {
774 .destroy = nv17_tv_destroy,
778 nv17_tv_create(struct drm_connector *connector, struct dcb_entry *entry)
780 struct drm_device *dev = connector->dev;
781 struct drm_encoder *encoder;
782 struct nv17_tv_encoder *tv_enc = NULL;
784 tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
788 tv_enc->overscan = 50;
789 tv_enc->flicker = 50;
790 tv_enc->saturation = 50;
792 tv_enc->tv_norm = TV_NORM_PAL;
793 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
794 tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
795 tv_enc->pin_mask = 0;
797 encoder = to_drm_encoder(&tv_enc->base);
799 tv_enc->base.dcb = entry;
800 tv_enc->base.or = ffs(entry->or) - 1;
802 drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC);
803 drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
804 to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
806 encoder->possible_crtcs = entry->heads;
807 encoder->possible_clones = 0;
809 nv17_tv_create_resources(encoder, connector);
810 drm_mode_connector_attach_encoder(connector, encoder);