drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_gpio.h"
  40 #include "nouveau_pm.h"
  41 #include "nv50_display.h"
  42
  43 static void nouveau_stub_takedown(struct drm_device *dev) {}
  44 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  45
  46 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  47 {
  48         struct drm_nouveau_private *dev_priv = dev->dev_private;
  49         struct nouveau_engine *engine = &dev_priv->engine;
  50
  51         switch (dev_priv->chipset & 0xf0) {
  52         case 0x00:
  53                 engine->instmem.init            = nv04_instmem_init;
  54                 engine->instmem.takedown        = nv04_instmem_takedown;
  55                 engine->instmem.suspend         = nv04_instmem_suspend;
  56                 engine->instmem.resume          = nv04_instmem_resume;
  57                 engine->instmem.get             = nv04_instmem_get;
  58                 engine->instmem.put             = nv04_instmem_put;
  59                 engine->instmem.map             = nv04_instmem_map;
  60                 engine->instmem.unmap           = nv04_instmem_unmap;
  61                 engine->instmem.flush           = nv04_instmem_flush;
  62                 engine->mc.init                 = nv04_mc_init;
  63                 engine->mc.takedown             = nv04_mc_takedown;
  64                 engine->timer.init              = nv04_timer_init;
  65                 engine->timer.read              = nv04_timer_read;
  66                 engine->timer.takedown          = nv04_timer_takedown;
  67                 engine->fb.init                 = nv04_fb_init;
  68                 engine->fb.takedown             = nv04_fb_takedown;
  69                 engine->fifo.channels           = 16;
  70                 engine->fifo.init               = nv04_fifo_init;
  71                 engine->fifo.takedown           = nv04_fifo_fini;
  72                 engine->fifo.disable            = nv04_fifo_disable;
  73                 engine->fifo.enable             = nv04_fifo_enable;
  74                 engine->fifo.reassign           = nv04_fifo_reassign;
  75                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  76                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  77                 engine->fifo.create_context     = nv04_fifo_create_context;
  78                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  79                 engine->fifo.load_context       = nv04_fifo_load_context;
  80                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  81                 engine->display.early_init      = nv04_display_early_init;
  82                 engine->display.late_takedown   = nv04_display_late_takedown;
  83                 engine->display.create          = nv04_display_create;
  84                 engine->display.destroy         = nv04_display_destroy;
  85                 engine->display.init            = nv04_display_init;
  86                 engine->display.fini            = nv04_display_fini;
  87                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  88                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  89                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  90                 engine->vram.init               = nv04_fb_vram_init;
  91                 engine->vram.takedown           = nouveau_stub_takedown;
  92                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  93                 break;
  94         case 0x10:
  95                 engine->instmem.init            = nv04_instmem_init;
  96                 engine->instmem.takedown        = nv04_instmem_takedown;
  97                 engine->instmem.suspend         = nv04_instmem_suspend;
  98                 engine->instmem.resume          = nv04_instmem_resume;
  99                 engine->instmem.get             = nv04_instmem_get;
 100                 engine->instmem.put             = nv04_instmem_put;
 101                 engine->instmem.map             = nv04_instmem_map;
 102                 engine->instmem.unmap           = nv04_instmem_unmap;
 103                 engine->instmem.flush           = nv04_instmem_flush;
 104                 engine->mc.init                 = nv04_mc_init;
 105                 engine->mc.takedown             = nv04_mc_takedown;
 106                 engine->timer.init              = nv04_timer_init;
 107                 engine->timer.read              = nv04_timer_read;
 108                 engine->timer.takedown          = nv04_timer_takedown;
 109                 engine->fb.init                 = nv10_fb_init;
 110                 engine->fb.takedown             = nv10_fb_takedown;
 111                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 112                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 113                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 114                 engine->fifo.channels           = 32;
 115                 engine->fifo.init               = nv10_fifo_init;
 116                 engine->fifo.takedown           = nv04_fifo_fini;
 117                 engine->fifo.disable            = nv04_fifo_disable;
 118                 engine->fifo.enable             = nv04_fifo_enable;
 119                 engine->fifo.reassign           = nv04_fifo_reassign;
 120                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 121                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 122                 engine->fifo.create_context     = nv10_fifo_create_context;
 123                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 124                 engine->fifo.load_context       = nv10_fifo_load_context;
 125                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 126                 engine->display.early_init      = nv04_display_early_init;
 127                 engine->display.late_takedown   = nv04_display_late_takedown;
 128                 engine->display.create          = nv04_display_create;
 129                 engine->display.destroy         = nv04_display_destroy;
 130                 engine->display.init            = nv04_display_init;
 131                 engine->display.fini            = nv04_display_fini;
 132                 engine->gpio.drive              = nv10_gpio_drive;
 133                 engine->gpio.sense              = nv10_gpio_sense;
 134                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 135                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 136                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 137                 if (dev_priv->chipset == 0x1a ||
 138                     dev_priv->chipset == 0x1f)
 139                         engine->vram.init       = nv1a_fb_vram_init;
 140                 else
 141                         engine->vram.init       = nv10_fb_vram_init;
 142                 engine->vram.takedown           = nouveau_stub_takedown;
 143                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 144                 break;
 145         case 0x20:
 146                 engine->instmem.init            = nv04_instmem_init;
 147                 engine->instmem.takedown        = nv04_instmem_takedown;
 148                 engine->instmem.suspend         = nv04_instmem_suspend;
 149                 engine->instmem.resume          = nv04_instmem_resume;
 150                 engine->instmem.get             = nv04_instmem_get;
 151                 engine->instmem.put             = nv04_instmem_put;
 152                 engine->instmem.map             = nv04_instmem_map;
 153                 engine->instmem.unmap           = nv04_instmem_unmap;
 154                 engine->instmem.flush           = nv04_instmem_flush;
 155                 engine->mc.init                 = nv04_mc_init;
 156                 engine->mc.takedown             = nv04_mc_takedown;
 157                 engine->timer.init              = nv04_timer_init;
 158                 engine->timer.read              = nv04_timer_read;
 159                 engine->timer.takedown          = nv04_timer_takedown;
 160                 engine->fb.init                 = nv20_fb_init;
 161                 engine->fb.takedown             = nv20_fb_takedown;
 162                 engine->fb.init_tile_region     = nv20_fb_init_tile_region;
 163                 engine->fb.set_tile_region      = nv20_fb_set_tile_region;
 164                 engine->fb.free_tile_region     = nv20_fb_free_tile_region;
 165                 engine->fifo.channels           = 32;
 166                 engine->fifo.init               = nv10_fifo_init;
 167                 engine->fifo.takedown           = nv04_fifo_fini;
 168                 engine->fifo.disable            = nv04_fifo_disable;
 169                 engine->fifo.enable             = nv04_fifo_enable;
 170                 engine->fifo.reassign           = nv04_fifo_reassign;
 171                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 172                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 173                 engine->fifo.create_context     = nv10_fifo_create_context;
 174                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 175                 engine->fifo.load_context       = nv10_fifo_load_context;
 176                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 177                 engine->display.early_init      = nv04_display_early_init;
 178                 engine->display.late_takedown   = nv04_display_late_takedown;
 179                 engine->display.create          = nv04_display_create;
 180                 engine->display.destroy         = nv04_display_destroy;
 181                 engine->display.init            = nv04_display_init;
 182                 engine->display.fini            = nv04_display_fini;
 183                 engine->gpio.drive              = nv10_gpio_drive;
 184                 engine->gpio.sense              = nv10_gpio_sense;
 185                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 186                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 187                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 188                 engine->vram.init               = nv20_fb_vram_init;
 189                 engine->vram.takedown           = nouveau_stub_takedown;
 190                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 191                 break;
 192         case 0x30:
 193                 engine->instmem.init            = nv04_instmem_init;
 194                 engine->instmem.takedown        = nv04_instmem_takedown;
 195                 engine->instmem.suspend         = nv04_instmem_suspend;
 196                 engine->instmem.resume          = nv04_instmem_resume;
 197                 engine->instmem.get             = nv04_instmem_get;
 198                 engine->instmem.put             = nv04_instmem_put;
 199                 engine->instmem.map             = nv04_instmem_map;
 200                 engine->instmem.unmap           = nv04_instmem_unmap;
 201                 engine->instmem.flush           = nv04_instmem_flush;
 202                 engine->mc.init                 = nv04_mc_init;
 203                 engine->mc.takedown             = nv04_mc_takedown;
 204                 engine->timer.init              = nv04_timer_init;
 205                 engine->timer.read              = nv04_timer_read;
 206                 engine->timer.takedown          = nv04_timer_takedown;
 207                 engine->fb.init                 = nv30_fb_init;
 208                 engine->fb.takedown             = nv30_fb_takedown;
 209                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 210                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 211                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 212                 engine->fifo.channels           = 32;
 213                 engine->fifo.init               = nv10_fifo_init;
 214                 engine->fifo.takedown           = nv04_fifo_fini;
 215                 engine->fifo.disable            = nv04_fifo_disable;
 216                 engine->fifo.enable             = nv04_fifo_enable;
 217                 engine->fifo.reassign           = nv04_fifo_reassign;
 218                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 219                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 220                 engine->fifo.create_context     = nv10_fifo_create_context;
 221                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 222                 engine->fifo.load_context       = nv10_fifo_load_context;
 223                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 224                 engine->display.early_init      = nv04_display_early_init;
 225                 engine->display.late_takedown   = nv04_display_late_takedown;
 226                 engine->display.create          = nv04_display_create;
 227                 engine->display.destroy         = nv04_display_destroy;
 228                 engine->display.init            = nv04_display_init;
 229                 engine->display.fini            = nv04_display_fini;
 230                 engine->gpio.drive              = nv10_gpio_drive;
 231                 engine->gpio.sense              = nv10_gpio_sense;
 232                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 233                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 234                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 235                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 236                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 237                 engine->vram.init               = nv20_fb_vram_init;
 238                 engine->vram.takedown           = nouveau_stub_takedown;
 239                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 240                 break;
 241         case 0x40:
 242         case 0x60:
 243                 engine->instmem.init            = nv04_instmem_init;
 244                 engine->instmem.takedown        = nv04_instmem_takedown;
 245                 engine->instmem.suspend         = nv04_instmem_suspend;
 246                 engine->instmem.resume          = nv04_instmem_resume;
 247                 engine->instmem.get             = nv04_instmem_get;
 248                 engine->instmem.put             = nv04_instmem_put;
 249                 engine->instmem.map             = nv04_instmem_map;
 250                 engine->instmem.unmap           = nv04_instmem_unmap;
 251                 engine->instmem.flush           = nv04_instmem_flush;
 252                 engine->mc.init                 = nv40_mc_init;
 253                 engine->mc.takedown             = nv40_mc_takedown;
 254                 engine->timer.init              = nv04_timer_init;
 255                 engine->timer.read              = nv04_timer_read;
 256                 engine->timer.takedown          = nv04_timer_takedown;
 257                 engine->fb.init                 = nv40_fb_init;
 258                 engine->fb.takedown             = nv40_fb_takedown;
 259                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 260                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 261                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 262                 engine->fifo.channels           = 32;
 263                 engine->fifo.init               = nv40_fifo_init;
 264                 engine->fifo.takedown           = nv04_fifo_fini;
 265                 engine->fifo.disable            = nv04_fifo_disable;
 266                 engine->fifo.enable             = nv04_fifo_enable;
 267                 engine->fifo.reassign           = nv04_fifo_reassign;
 268                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 269                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 270                 engine->fifo.create_context     = nv40_fifo_create_context;
 271                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 272                 engine->fifo.load_context       = nv40_fifo_load_context;
 273                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 274                 engine->display.early_init      = nv04_display_early_init;
 275                 engine->display.late_takedown   = nv04_display_late_takedown;
 276                 engine->display.create          = nv04_display_create;
 277                 engine->display.destroy         = nv04_display_destroy;
 278                 engine->display.init            = nv04_display_init;
 279                 engine->display.fini            = nv04_display_fini;
 280                 engine->gpio.init               = nv10_gpio_init;
 281                 engine->gpio.fini               = nv10_gpio_fini;
 282                 engine->gpio.drive              = nv10_gpio_drive;
 283                 engine->gpio.sense              = nv10_gpio_sense;
 284                 engine->gpio.irq_enable         = nv10_gpio_irq_enable;
 285                 engine->pm.clocks_get           = nv40_pm_clocks_get;
 286                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
 287                 engine->pm.clocks_set           = nv40_pm_clocks_set;
 288                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 289                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 290                 engine->pm.temp_get             = nv40_temp_get;
 291                 engine->pm.pwm_get              = nv40_pm_pwm_get;
 292                 engine->pm.pwm_set              = nv40_pm_pwm_set;
 293                 engine->vram.init               = nv40_fb_vram_init;
 294                 engine->vram.takedown           = nouveau_stub_takedown;
 295                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 296                 break;
 297         case 0x50:
 298         case 0x80: /* gotta love NVIDIA's consistency.. */
 299         case 0x90:
 300         case 0xa0:
 301                 engine->instmem.init            = nv50_instmem_init;
 302                 engine->instmem.takedown        = nv50_instmem_takedown;
 303                 engine->instmem.suspend         = nv50_instmem_suspend;
 304                 engine->instmem.resume          = nv50_instmem_resume;
 305                 engine->instmem.get             = nv50_instmem_get;
 306                 engine->instmem.put             = nv50_instmem_put;
 307                 engine->instmem.map             = nv50_instmem_map;
 308                 engine->instmem.unmap           = nv50_instmem_unmap;
 309                 if (dev_priv->chipset == 0x50)
 310                         engine->instmem.flush   = nv50_instmem_flush;
 311                 else
 312                         engine->instmem.flush   = nv84_instmem_flush;
 313                 engine->mc.init                 = nv50_mc_init;
 314                 engine->mc.takedown             = nv50_mc_takedown;
 315                 engine->timer.init              = nv04_timer_init;
 316                 engine->timer.read              = nv04_timer_read;
 317                 engine->timer.takedown          = nv04_timer_takedown;
 318                 engine->fb.init                 = nv50_fb_init;
 319                 engine->fb.takedown             = nv50_fb_takedown;
 320                 engine->fifo.channels           = 128;
 321                 engine->fifo.init               = nv50_fifo_init;
 322                 engine->fifo.takedown           = nv50_fifo_takedown;
 323                 engine->fifo.disable            = nv04_fifo_disable;
 324                 engine->fifo.enable             = nv04_fifo_enable;
 325                 engine->fifo.reassign           = nv04_fifo_reassign;
 326                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 327                 engine->fifo.create_context     = nv50_fifo_create_context;
 328                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 329                 engine->fifo.load_context       = nv50_fifo_load_context;
 330                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 331                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 332                 engine->display.early_init      = nv50_display_early_init;
 333                 engine->display.late_takedown   = nv50_display_late_takedown;
 334                 engine->display.create          = nv50_display_create;
 335                 engine->display.destroy         = nv50_display_destroy;
 336                 engine->display.init            = nv50_display_init;
 337                 engine->display.fini            = nv50_display_fini;
 338                 engine->gpio.init               = nv50_gpio_init;
 339                 engine->gpio.fini               = nv50_gpio_fini;
 340                 engine->gpio.drive              = nv50_gpio_drive;
 341                 engine->gpio.sense              = nv50_gpio_sense;
 342                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 343                 switch (dev_priv->chipset) {
 344                 case 0x84:
 345                 case 0x86:
 346                 case 0x92:
 347                 case 0x94:
 348                 case 0x96:
 349                 case 0x98:
 350                 case 0xa0:
 351                 case 0xaa:
 352                 case 0xac:
 353                 case 0x50:
 354                         engine->pm.clocks_get   = nv50_pm_clocks_get;
 355                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
 356                         engine->pm.clocks_set   = nv50_pm_clocks_set;
 357                         break;
 358                 default:
 359                         engine->pm.clocks_get   = nva3_pm_clocks_get;
 360                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
 361                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 362                         break;
 363                 }
 364                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 365                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 366                 if (dev_priv->chipset >= 0x84)
 367                         engine->pm.temp_get     = nv84_temp_get;
 368                 else
 369                         engine->pm.temp_get     = nv40_temp_get;
 370                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 371                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 372                 engine->vram.init               = nv50_vram_init;
 373                 engine->vram.takedown           = nv50_vram_fini;
 374                 engine->vram.get                = nv50_vram_new;
 375                 engine->vram.put                = nv50_vram_del;
 376                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 377                 break;
 378         case 0xc0:
 379                 engine->instmem.init            = nvc0_instmem_init;
 380                 engine->instmem.takedown        = nvc0_instmem_takedown;
 381                 engine->instmem.suspend         = nvc0_instmem_suspend;
 382                 engine->instmem.resume          = nvc0_instmem_resume;
 383                 engine->instmem.get             = nv50_instmem_get;
 384                 engine->instmem.put             = nv50_instmem_put;
 385                 engine->instmem.map             = nv50_instmem_map;
 386                 engine->instmem.unmap           = nv50_instmem_unmap;
 387                 engine->instmem.flush           = nv84_instmem_flush;
 388                 engine->mc.init                 = nv50_mc_init;
 389                 engine->mc.takedown             = nv50_mc_takedown;
 390                 engine->timer.init              = nv04_timer_init;
 391                 engine->timer.read              = nv04_timer_read;
 392                 engine->timer.takedown          = nv04_timer_takedown;
 393                 engine->fb.init                 = nvc0_fb_init;
 394                 engine->fb.takedown             = nvc0_fb_takedown;
 395                 engine->fifo.channels           = 128;
 396                 engine->fifo.init               = nvc0_fifo_init;
 397                 engine->fifo.takedown           = nvc0_fifo_takedown;
 398                 engine->fifo.disable            = nvc0_fifo_disable;
 399                 engine->fifo.enable             = nvc0_fifo_enable;
 400                 engine->fifo.reassign           = nvc0_fifo_reassign;
 401                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 402                 engine->fifo.create_context     = nvc0_fifo_create_context;
 403                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 404                 engine->fifo.load_context       = nvc0_fifo_load_context;
 405                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 406                 engine->display.early_init      = nv50_display_early_init;
 407                 engine->display.late_takedown   = nv50_display_late_takedown;
 408                 engine->display.create          = nv50_display_create;
 409                 engine->display.destroy         = nv50_display_destroy;
 410                 engine->display.init            = nv50_display_init;
 411                 engine->display.fini            = nv50_display_fini;
 412                 engine->gpio.init               = nv50_gpio_init;
 413                 engine->gpio.fini               = nv50_gpio_fini;
 414                 engine->gpio.drive              = nv50_gpio_drive;
 415                 engine->gpio.sense              = nv50_gpio_sense;
 416                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 417                 engine->vram.init               = nvc0_vram_init;
 418                 engine->vram.takedown           = nv50_vram_fini;
 419                 engine->vram.get                = nvc0_vram_new;
 420                 engine->vram.put                = nv50_vram_del;
 421                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 422                 engine->pm.temp_get             = nv84_temp_get;
 423                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 424                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 425                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 426                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 427                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 428                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 429                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 430                 break;
 431         case 0xd0:
 432                 engine->instmem.init            = nvc0_instmem_init;
 433                 engine->instmem.takedown        = nvc0_instmem_takedown;
 434                 engine->instmem.suspend         = nvc0_instmem_suspend;
 435                 engine->instmem.resume          = nvc0_instmem_resume;
 436                 engine->instmem.get             = nv50_instmem_get;
 437                 engine->instmem.put             = nv50_instmem_put;
 438                 engine->instmem.map             = nv50_instmem_map;
 439                 engine->instmem.unmap           = nv50_instmem_unmap;
 440                 engine->instmem.flush           = nv84_instmem_flush;
 441                 engine->mc.init                 = nv50_mc_init;
 442                 engine->mc.takedown             = nv50_mc_takedown;
 443                 engine->timer.init              = nv04_timer_init;
 444                 engine->timer.read              = nv04_timer_read;
 445                 engine->timer.takedown          = nv04_timer_takedown;
 446                 engine->fb.init                 = nvc0_fb_init;
 447                 engine->fb.takedown             = nvc0_fb_takedown;
 448                 engine->fifo.channels           = 128;
 449                 engine->fifo.init               = nvc0_fifo_init;
 450                 engine->fifo.takedown           = nvc0_fifo_takedown;
 451                 engine->fifo.disable            = nvc0_fifo_disable;
 452                 engine->fifo.enable             = nvc0_fifo_enable;
 453                 engine->fifo.reassign           = nvc0_fifo_reassign;
 454                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 455                 engine->fifo.create_context     = nvc0_fifo_create_context;
 456                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 457                 engine->fifo.load_context       = nvc0_fifo_load_context;
 458                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 459                 engine->display.early_init      = nouveau_stub_init;
 460                 engine->display.late_takedown   = nouveau_stub_takedown;
 461                 engine->display.create          = nvd0_display_create;
 462                 engine->display.destroy         = nvd0_display_destroy;
 463                 engine->display.init            = nvd0_display_init;
 464                 engine->display.fini            = nvd0_display_fini;
 465                 engine->gpio.init               = nv50_gpio_init;
 466                 engine->gpio.fini               = nv50_gpio_fini;
 467                 engine->gpio.drive              = nvd0_gpio_drive;
 468                 engine->gpio.sense              = nvd0_gpio_sense;
 469                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 470                 engine->vram.init               = nvc0_vram_init;
 471                 engine->vram.takedown           = nv50_vram_fini;
 472                 engine->vram.get                = nvc0_vram_new;
 473                 engine->vram.put                = nv50_vram_del;
 474                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 475                 engine->pm.temp_get             = nv84_temp_get;
 476                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 477                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 478                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 479                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 480                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 481                 break;
 482         case 0xe0:
 483                 engine->instmem.init            = nvc0_instmem_init;
 484                 engine->instmem.takedown        = nvc0_instmem_takedown;
 485                 engine->instmem.suspend         = nvc0_instmem_suspend;
 486                 engine->instmem.resume          = nvc0_instmem_resume;
 487                 engine->instmem.get             = nv50_instmem_get;
 488                 engine->instmem.put             = nv50_instmem_put;
 489                 engine->instmem.map             = nv50_instmem_map;
 490                 engine->instmem.unmap           = nv50_instmem_unmap;
 491                 engine->instmem.flush           = nv84_instmem_flush;
 492                 engine->mc.init                 = nv50_mc_init;
 493                 engine->mc.takedown             = nv50_mc_takedown;
 494                 engine->timer.init              = nv04_timer_init;
 495                 engine->timer.read              = nv04_timer_read;
 496                 engine->timer.takedown          = nv04_timer_takedown;
 497                 engine->fb.init                 = nvc0_fb_init;
 498                 engine->fb.takedown             = nvc0_fb_takedown;
 499                 engine->fifo.channels           = 0;
 500                 engine->fifo.init               = nouveau_stub_init;
 501                 engine->fifo.takedown           = nouveau_stub_takedown;
 502                 engine->fifo.disable            = nvc0_fifo_disable;
 503                 engine->fifo.enable             = nvc0_fifo_enable;
 504                 engine->fifo.reassign           = nvc0_fifo_reassign;
 505                 engine->fifo.unload_context     = nouveau_stub_init;
 506                 engine->display.early_init      = nouveau_stub_init;
 507                 engine->display.late_takedown   = nouveau_stub_takedown;
 508                 engine->display.create          = nvd0_display_create;
 509                 engine->display.destroy         = nvd0_display_destroy;
 510                 engine->display.init            = nvd0_display_init;
 511                 engine->display.fini            = nvd0_display_fini;
 512                 engine->gpio.init               = nv50_gpio_init;
 513                 engine->gpio.fini               = nv50_gpio_fini;
 514                 engine->gpio.drive              = nvd0_gpio_drive;
 515                 engine->gpio.sense              = nvd0_gpio_sense;
 516                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 517                 engine->vram.init               = nvc0_vram_init;
 518                 engine->vram.takedown           = nv50_vram_fini;
 519                 engine->vram.get                = nvc0_vram_new;
 520                 engine->vram.put                = nv50_vram_del;
 521                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 522                 break;
 523         default:
 524                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 525                 return 1;
 526         }
 527
 528         /* headless mode */
 529         if (nouveau_modeset == 2) {
 530                 engine->display.early_init = nouveau_stub_init;
 531                 engine->display.late_takedown = nouveau_stub_takedown;
 532                 engine->display.create = nouveau_stub_init;
 533                 engine->display.init = nouveau_stub_init;
 534                 engine->display.destroy = nouveau_stub_takedown;
 535         }
 536
 537         return 0;
 538 }
 539
 540 static unsigned int
 541 nouveau_vga_set_decode(void *priv, bool state)
 542 {
 543         struct drm_device *dev = priv;
 544         struct drm_nouveau_private *dev_priv = dev->dev_private;
 545
 546         if (dev_priv->chipset >= 0x40)
 547                 nv_wr32(dev, 0x88054, state);
 548         else
 549                 nv_wr32(dev, 0x1854, state);
 550
 551         if (state)
 552                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 553                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 554         else
 555                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 556 }
 557
 558 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 559                                          enum vga_switcheroo_state state)
 560 {
 561         struct drm_device *dev = pci_get_drvdata(pdev);
 562         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 563         if (state == VGA_SWITCHEROO_ON) {
 564                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 565                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 566                 nouveau_pci_resume(pdev);
 567                 drm_kms_helper_poll_enable(dev);
 568                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 569         } else {
 570                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 571                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 572                 drm_kms_helper_poll_disable(dev);
 573                 nouveau_switcheroo_optimus_dsm();
 574                 nouveau_pci_suspend(pdev, pmm);
 575                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 576         }
 577 }
 578
 579 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 580 {
 581         struct drm_device *dev = pci_get_drvdata(pdev);
 582         nouveau_fbcon_output_poll_changed(dev);
 583 }
 584
 585 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 586 {
 587         struct drm_device *dev = pci_get_drvdata(pdev);
 588         bool can_switch;
 589
 590         spin_lock(&dev->count_lock);
 591         can_switch = (dev->open_count == 0);
 592         spin_unlock(&dev->count_lock);
 593         return can_switch;
 594 }
 595
 596 static void
 597 nouveau_card_channel_fini(struct drm_device *dev)
 598 {
 599         struct drm_nouveau_private *dev_priv = dev->dev_private;
 600
 601         if (dev_priv->channel)
 602                 nouveau_channel_put_unlocked(&dev_priv->channel);
 603 }
 604
 605 static int
 606 nouveau_card_channel_init(struct drm_device *dev)
 607 {
 608         struct drm_nouveau_private *dev_priv = dev->dev_private;
 609         struct nouveau_channel *chan;
 610         int ret, oclass;
 611
 612         ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT);
 613         dev_priv->channel = chan;
 614         if (ret)
 615                 return ret;
 616
 617         mutex_unlock(&dev_priv->channel->mutex);
 618
 619         if (dev_priv->card_type <= NV_50) {
 620                 if (dev_priv->card_type < NV_50)
 621                         oclass = 0x0039;
 622                 else
 623                         oclass = 0x5039;
 624
 625                 ret = nouveau_gpuobj_gr_new(chan, NvM2MF, oclass);
 626                 if (ret)
 627                         goto error;
 628
 629                 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
 630                                              &chan->m2mf_ntfy);
 631                 if (ret)
 632                         goto error;
 633
 634                 ret = RING_SPACE(chan, 6);
 635                 if (ret)
 636                         goto error;
 637
 638                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
 639                 OUT_RING  (chan, NvM2MF);
 640                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
 641                 OUT_RING  (chan, NvNotify0);
 642                 OUT_RING  (chan, chan->vram_handle);
 643                 OUT_RING  (chan, chan->gart_handle);
 644         } else
 645         if (dev_priv->card_type <= NV_D0) {
 646                 ret = nouveau_gpuobj_gr_new(chan, 0x9039, 0x9039);
 647                 if (ret)
 648                         goto error;
 649
 650                 ret = RING_SPACE(chan, 2);
 651                 if (ret)
 652                         goto error;
 653
 654                 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0000, 1);
 655                 OUT_RING  (chan, 0x00009039);
 656         }
 657
 658         FIRE_RING (chan);
 659 error:
 660         if (ret)
 661                 nouveau_card_channel_fini(dev);
 662         return ret;
 663 }
 664
 665 static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = {
 666         .set_gpu_state = nouveau_switcheroo_set_state,
 667         .reprobe = nouveau_switcheroo_reprobe,
 668         .can_switch = nouveau_switcheroo_can_switch,
 669 };
 670
 671 int
 672 nouveau_card_init(struct drm_device *dev)
 673 {
 674         struct drm_nouveau_private *dev_priv = dev->dev_private;
 675         struct nouveau_engine *engine;
 676         int ret, e = 0;
 677
 678         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 679         vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
 680
 681         /* Initialise internal driver API hooks */
 682         ret = nouveau_init_engine_ptrs(dev);
 683         if (ret)
 684                 goto out;
 685         engine = &dev_priv->engine;
 686         spin_lock_init(&dev_priv->channels.lock);
 687         spin_lock_init(&dev_priv->tile.lock);
 688         spin_lock_init(&dev_priv->context_switch_lock);
 689         spin_lock_init(&dev_priv->vm_lock);
 690
 691         /* Make the CRTCs and I2C buses accessible */
 692         ret = engine->display.early_init(dev);
 693         if (ret)
 694                 goto out;
 695
 696         /* Parse BIOS tables / Run init tables if card not POSTed */
 697         ret = nouveau_bios_init(dev);
 698         if (ret)
 699                 goto out_display_early;
 700
 701         /* workaround an odd issue on nvc1 by disabling the device's
 702          * nosnoop capability.  hopefully won't cause issues until a
 703          * better fix is found - assuming there is one...
 704          */
 705         if (dev_priv->chipset == 0xc1) {
 706                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 707         }
 708
 709         /* PMC */
 710         ret = engine->mc.init(dev);
 711         if (ret)
 712                 goto out_bios;
 713
 714         /* PTIMER */
 715         ret = engine->timer.init(dev);
 716         if (ret)
 717                 goto out_mc;
 718
 719         /* PFB */
 720         ret = engine->fb.init(dev);
 721         if (ret)
 722                 goto out_timer;
 723
 724         ret = engine->vram.init(dev);
 725         if (ret)
 726                 goto out_fb;
 727
 728         /* PGPIO */
 729         ret = nouveau_gpio_create(dev);
 730         if (ret)
 731                 goto out_vram;
 732
 733         ret = nouveau_gpuobj_init(dev);
 734         if (ret)
 735                 goto out_gpio;
 736
 737         ret = engine->instmem.init(dev);
 738         if (ret)
 739                 goto out_gpuobj;
 740
 741         ret = nouveau_mem_vram_init(dev);
 742         if (ret)
 743                 goto out_instmem;
 744
 745         ret = nouveau_mem_gart_init(dev);
 746         if (ret)
 747                 goto out_ttmvram;
 748
 749         if (!dev_priv->noaccel) {
 750                 switch (dev_priv->card_type) {
 751                 case NV_04:
 752                         nv04_graph_create(dev);
 753                         break;
 754                 case NV_10:
 755                         nv10_graph_create(dev);
 756                         break;
 757                 case NV_20:
 758                 case NV_30:
 759                         nv20_graph_create(dev);
 760                         break;
 761                 case NV_40:
 762                         nv40_graph_create(dev);
 763                         break;
 764                 case NV_50:
 765                         nv50_graph_create(dev);
 766                         break;
 767                 case NV_C0:
 768                 case NV_D0:
 769                         nvc0_graph_create(dev);
 770                         break;
 771                 default:
 772                         break;
 773                 }
 774
 775                 switch (dev_priv->chipset) {
 776                 case 0x84:
 777                 case 0x86:
 778                 case 0x92:
 779                 case 0x94:
 780                 case 0x96:
 781                 case 0xa0:
 782                         nv84_crypt_create(dev);
 783                         break;
 784                 case 0x98:
 785                 case 0xaa:
 786                 case 0xac:
 787                         nv98_crypt_create(dev);
 788                         break;
 789                 }
 790
 791                 switch (dev_priv->card_type) {
 792                 case NV_50:
 793                         switch (dev_priv->chipset) {
 794                         case 0xa3:
 795                         case 0xa5:
 796                         case 0xa8:
 797                         case 0xaf:
 798                                 nva3_copy_create(dev);
 799                                 break;
 800                         }
 801                         break;
 802                 case NV_C0:
 803                         nvc0_copy_create(dev, 0);
 804                         nvc0_copy_create(dev, 1);
 805                         break;
 806                 default:
 807                         break;
 808                 }
 809
 810                 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
 811                         nv84_bsp_create(dev);
 812                         nv84_vp_create(dev);
 813                         nv98_ppp_create(dev);
 814                 } else
 815                 if (dev_priv->chipset >= 0x84) {
 816                         nv50_mpeg_create(dev);
 817                         nv84_bsp_create(dev);
 818                         nv84_vp_create(dev);
 819                 } else
 820                 if (dev_priv->chipset >= 0x50) {
 821                         nv50_mpeg_create(dev);
 822                 } else
 823                 if (dev_priv->card_type == NV_40 ||
 824                     dev_priv->chipset == 0x31 ||
 825                     dev_priv->chipset == 0x34 ||
 826                     dev_priv->chipset == 0x36) {
 827                         nv31_mpeg_create(dev);
 828                 }
 829
 830                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 831                         if (dev_priv->eng[e]) {
 832                                 ret = dev_priv->eng[e]->init(dev, e);
 833                                 if (ret)
 834                                         goto out_engine;
 835                         }
 836                 }
 837
 838                 /* PFIFO */
 839                 ret = engine->fifo.init(dev);
 840                 if (ret)
 841                         goto out_engine;
 842         }
 843
 844         ret = nouveau_irq_init(dev);
 845         if (ret)
 846                 goto out_fifo;
 847
 848         ret = nouveau_display_create(dev);
 849         if (ret)
 850                 goto out_irq;
 851
 852         nouveau_backlight_init(dev);
 853         nouveau_pm_init(dev);
 854
 855         ret = nouveau_fence_init(dev);
 856         if (ret)
 857                 goto out_pm;
 858
 859         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 860                 ret = nouveau_card_channel_init(dev);
 861                 if (ret)
 862                         goto out_fence;
 863         }
 864
 865         if (dev->mode_config.num_crtc) {
 866                 ret = nouveau_display_init(dev);
 867                 if (ret)
 868                         goto out_chan;
 869
 870                 nouveau_fbcon_init(dev);
 871         }
 872
 873         return 0;
 874
 875 out_chan:
 876         nouveau_card_channel_fini(dev);
 877 out_fence:
 878         nouveau_fence_fini(dev);
 879 out_pm:
 880         nouveau_pm_fini(dev);
 881         nouveau_backlight_exit(dev);
 882         nouveau_display_destroy(dev);
 883 out_irq:
 884         nouveau_irq_fini(dev);
 885 out_fifo:
 886         if (!dev_priv->noaccel)
 887                 engine->fifo.takedown(dev);
 888 out_engine:
 889         if (!dev_priv->noaccel) {
 890                 for (e = e - 1; e >= 0; e--) {
 891                         if (!dev_priv->eng[e])
 892                                 continue;
 893                         dev_priv->eng[e]->fini(dev, e, false);
 894                         dev_priv->eng[e]->destroy(dev,e );
 895                 }
 896         }
 897         nouveau_mem_gart_fini(dev);
 898 out_ttmvram:
 899         nouveau_mem_vram_fini(dev);
 900 out_instmem:
 901         engine->instmem.takedown(dev);
 902 out_gpuobj:
 903         nouveau_gpuobj_takedown(dev);
 904 out_gpio:
 905         nouveau_gpio_destroy(dev);
 906 out_vram:
 907         engine->vram.takedown(dev);
 908 out_fb:
 909         engine->fb.takedown(dev);
 910 out_timer:
 911         engine->timer.takedown(dev);
 912 out_mc:
 913         engine->mc.takedown(dev);
 914 out_bios:
 915         nouveau_bios_takedown(dev);
 916 out_display_early:
 917         engine->display.late_takedown(dev);
 918 out:
 919         vga_client_register(dev->pdev, NULL, NULL, NULL);
 920         return ret;
 921 }
 922
 923 static void nouveau_card_takedown(struct drm_device *dev)
 924 {
 925         struct drm_nouveau_private *dev_priv = dev->dev_private;
 926         struct nouveau_engine *engine = &dev_priv->engine;
 927         int e;
 928
 929         if (dev->mode_config.num_crtc) {
 930                 nouveau_fbcon_fini(dev);
 931                 nouveau_display_fini(dev);
 932         }
 933
 934         nouveau_card_channel_fini(dev);
 935         nouveau_fence_fini(dev);
 936         nouveau_pm_fini(dev);
 937         nouveau_backlight_exit(dev);
 938         nouveau_display_destroy(dev);
 939
 940         if (!dev_priv->noaccel) {
 941                 engine->fifo.takedown(dev);
 942                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 943                         if (dev_priv->eng[e]) {
 944                                 dev_priv->eng[e]->fini(dev, e, false);
 945                                 dev_priv->eng[e]->destroy(dev,e );
 946                         }
 947                 }
 948         }
 949
 950         if (dev_priv->vga_ram) {
 951                 nouveau_bo_unpin(dev_priv->vga_ram);
 952                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 953         }
 954
 955         mutex_lock(&dev->struct_mutex);
 956         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 957         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 958         mutex_unlock(&dev->struct_mutex);
 959         nouveau_mem_gart_fini(dev);
 960         nouveau_mem_vram_fini(dev);
 961
 962         engine->instmem.takedown(dev);
 963         nouveau_gpuobj_takedown(dev);
 964
 965         nouveau_gpio_destroy(dev);
 966         engine->vram.takedown(dev);
 967         engine->fb.takedown(dev);
 968         engine->timer.takedown(dev);
 969         engine->mc.takedown(dev);
 970
 971         nouveau_bios_takedown(dev);
 972         engine->display.late_takedown(dev);
 973
 974         nouveau_irq_fini(dev);
 975
 976         vga_client_register(dev->pdev, NULL, NULL, NULL);
 977 }
 978
 979 int
 980 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
 981 {
 982         struct drm_nouveau_private *dev_priv = dev->dev_private;
 983         struct nouveau_fpriv *fpriv;
 984         int ret;
 985
 986         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 987         if (unlikely(!fpriv))
 988                 return -ENOMEM;
 989
 990         spin_lock_init(&fpriv->lock);
 991         INIT_LIST_HEAD(&fpriv->channels);
 992
 993         if (dev_priv->card_type == NV_50) {
 994                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
 995                                      &fpriv->vm);
 996                 if (ret) {
 997                         kfree(fpriv);
 998                         return ret;
 999                 }
1000         } else
1001         if (dev_priv->card_type >= NV_C0) {
1002                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
1003                                      &fpriv->vm);
1004                 if (ret) {
1005                         kfree(fpriv);
1006                         return ret;
1007                 }
1008         }
1009
1010         file_priv->driver_priv = fpriv;
1011         return 0;
1012 }
1013
1014 /* here a client dies, release the stuff that was allocated for its
1015  * file_priv */
1016 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
1017 {
1018         nouveau_channel_cleanup(dev, file_priv);
1019 }
1020
1021 void
1022 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
1023 {
1024         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
1025         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
1026         kfree(fpriv);
1027 }
1028
1029 /* first module load, setup the mmio/fb mapping */
1030 /* KMS: we need mmio at load time, not when the first drm client opens. */
1031 int nouveau_firstopen(struct drm_device *dev)
1032 {
1033         return 0;
1034 }
1035
1036 /* if we have an OF card, copy vbios to RAMIN */
1037 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
1038 {
1039 #if defined(__powerpc__)
1040         int size, i;
1041         const uint32_t *bios;
1042         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
1043         if (!dn) {
1044                 NV_INFO(dev, "Unable to get the OF node\n");
1045                 return;
1046         }
1047
1048         bios = of_get_property(dn, "NVDA,BMP", &size);
1049         if (bios) {
1050                 for (i = 0; i < size; i += 4)
1051                         nv_wi32(dev, i, bios[i/4]);
1052                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
1053         } else {
1054                 NV_INFO(dev, "Unable to get the OF bios\n");
1055         }
1056 #endif
1057 }
1058
1059 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
1060 {
1061         struct pci_dev *pdev = dev->pdev;
1062         struct apertures_struct *aper = alloc_apertures(3);
1063         if (!aper)
1064                 return NULL;
1065
1066         aper->ranges[0].base = pci_resource_start(pdev, 1);
1067         aper->ranges[0].size = pci_resource_len(pdev, 1);
1068         aper->count = 1;
1069
1070         if (pci_resource_len(pdev, 2)) {
1071                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
1072                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
1073                 aper->count++;
1074         }
1075
1076         if (pci_resource_len(pdev, 3)) {
1077                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
1078                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
1079                 aper->count++;
1080         }
1081
1082         return aper;
1083 }
1084
1085 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
1086 {
1087         struct drm_nouveau_private *dev_priv = dev->dev_private;
1088         bool primary = false;
1089         dev_priv->apertures = nouveau_get_apertures(dev);
1090         if (!dev_priv->apertures)
1091                 return -ENOMEM;
1092
1093 #ifdef CONFIG_X86
1094         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1095 #endif
1096
1097         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
1098         return 0;
1099 }
1100
1101 int nouveau_load(struct drm_device *dev, unsigned long flags)
1102 {
1103         struct drm_nouveau_private *dev_priv;
1104         unsigned long long offset, length;
1105         uint32_t reg0 = ~0, strap;
1106         int ret;
1107
1108         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1109         if (!dev_priv) {
1110                 ret = -ENOMEM;
1111                 goto err_out;
1112         }
1113         dev->dev_private = dev_priv;
1114         dev_priv->dev = dev;
1115
1116         pci_set_master(dev->pdev);
1117
1118         dev_priv->flags = flags & NOUVEAU_FLAGS;
1119
1120         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1121                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1122
1123         /* first up, map the start of mmio and determine the chipset */
1124         dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
1125         if (dev_priv->mmio) {
1126 #ifdef __BIG_ENDIAN
1127                 /* put the card into big-endian mode if it's not */
1128                 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1129                         nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1130                 DRM_MEMORYBARRIER();
1131 #endif
1132
1133                 /* determine chipset and derive architecture from it */
1134                 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1135                 if ((reg0 & 0x0f000000) > 0) {
1136                         dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1137                         switch (dev_priv->chipset & 0xf0) {
1138                         case 0x10:
1139                         case 0x20:
1140                         case 0x30:
1141                                 dev_priv->card_type = dev_priv->chipset & 0xf0;
1142                                 break;
1143                         case 0x40:
1144                         case 0x60:
1145                                 dev_priv->card_type = NV_40;
1146                                 break;
1147                         case 0x50:
1148                         case 0x80:
1149                         case 0x90:
1150                         case 0xa0:
1151                                 dev_priv->card_type = NV_50;
1152                                 break;
1153                         case 0xc0:
1154                                 dev_priv->card_type = NV_C0;
1155                                 break;
1156                         case 0xd0:
1157                                 dev_priv->card_type = NV_D0;
1158                                 break;
1159                         case 0xe0:
1160                                 dev_priv->card_type = NV_E0;
1161                                 break;
1162                         default:
1163                                 break;
1164                         }
1165                 } else
1166                 if ((reg0 & 0xff00fff0) == 0x20004000) {
1167                         if (reg0 & 0x00f00000)
1168                                 dev_priv->chipset = 0x05;
1169                         else
1170                                 dev_priv->chipset = 0x04;
1171                         dev_priv->card_type = NV_04;
1172                 }
1173
1174                 iounmap(dev_priv->mmio);
1175         }
1176
1177         if (!dev_priv->card_type) {
1178                 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1179                 ret = -EINVAL;
1180                 goto err_priv;
1181         }
1182
1183         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1184                      dev_priv->card_type, reg0);
1185
1186         /* map the mmio regs, limiting the amount to preserve vmap space */
1187         offset = pci_resource_start(dev->pdev, 0);
1188         length = pci_resource_len(dev->pdev, 0);
1189         if (dev_priv->card_type < NV_E0)
1190                 length = min(length, (unsigned long long)0x00800000);
1191
1192         dev_priv->mmio = ioremap(offset, length);
1193         if (!dev_priv->mmio) {
1194                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1195                          "Please report your setup to " DRIVER_EMAIL "\n");
1196                 ret = -EINVAL;
1197                 goto err_priv;
1198         }
1199         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", offset);
1200
1201         /* determine frequency of timing crystal */
1202         strap = nv_rd32(dev, 0x101000);
1203         if ( dev_priv->chipset < 0x17 ||
1204             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1205                 strap &= 0x00000040;
1206         else
1207                 strap &= 0x00400040;
1208
1209         switch (strap) {
1210         case 0x00000000: dev_priv->crystal = 13500; break;
1211         case 0x00000040: dev_priv->crystal = 14318; break;
1212         case 0x00400000: dev_priv->crystal = 27000; break;
1213         case 0x00400040: dev_priv->crystal = 25000; break;
1214         }
1215
1216         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1217
1218         /* Determine whether we'll attempt acceleration or not, some
1219          * cards are disabled by default here due to them being known
1220          * non-functional, or never been tested due to lack of hw.
1221          */
1222         dev_priv->noaccel = !!nouveau_noaccel;
1223         if (nouveau_noaccel == -1) {
1224                 switch (dev_priv->chipset) {
1225                 case 0xd9: /* known broken */
1226                         NV_INFO(dev, "acceleration disabled by default, pass "
1227                                      "noaccel=0 to force enable\n");
1228                         dev_priv->noaccel = true;
1229                         break;
1230                 default:
1231                         dev_priv->noaccel = false;
1232                         break;
1233                 }
1234         }
1235
1236         ret = nouveau_remove_conflicting_drivers(dev);
1237         if (ret)
1238                 goto err_mmio;
1239
1240         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1241         if (dev_priv->card_type >= NV_40) {
1242                 int ramin_bar = 2;
1243                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1244                         ramin_bar = 3;
1245
1246                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1247                 dev_priv->ramin =
1248                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1249                                 dev_priv->ramin_size);
1250                 if (!dev_priv->ramin) {
1251                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1252                         ret = -ENOMEM;
1253                         goto err_mmio;
1254                 }
1255         } else {
1256                 dev_priv->ramin_size = 1 * 1024 * 1024;
1257                 dev_priv->ramin = ioremap(offset + NV_RAMIN,
1258                                           dev_priv->ramin_size);
1259                 if (!dev_priv->ramin) {
1260                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1261                         ret = -ENOMEM;
1262                         goto err_mmio;
1263                 }
1264         }
1265
1266         nouveau_OF_copy_vbios_to_ramin(dev);
1267
1268         /* Special flags */
1269         if (dev->pci_device == 0x01a0)
1270                 dev_priv->flags |= NV_NFORCE;
1271         else if (dev->pci_device == 0x01f0)
1272                 dev_priv->flags |= NV_NFORCE2;
1273
1274         /* For kernel modesetting, init card now and bring up fbcon */
1275         ret = nouveau_card_init(dev);
1276         if (ret)
1277                 goto err_ramin;
1278
1279         return 0;
1280
1281 err_ramin:
1282         iounmap(dev_priv->ramin);
1283 err_mmio:
1284         iounmap(dev_priv->mmio);
1285 err_priv:
1286         kfree(dev_priv);
1287         dev->dev_private = NULL;
1288 err_out:
1289         return ret;
1290 }
1291
1292 void nouveau_lastclose(struct drm_device *dev)
1293 {
1294         vga_switcheroo_process_delayed_switch();
1295 }
1296
1297 int nouveau_unload(struct drm_device *dev)
1298 {
1299         struct drm_nouveau_private *dev_priv = dev->dev_private;
1300
1301         nouveau_card_takedown(dev);
1302
1303         iounmap(dev_priv->mmio);
1304         iounmap(dev_priv->ramin);
1305
1306         kfree(dev_priv);
1307         dev->dev_private = NULL;
1308         return 0;
1309 }
1310
1311 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1312                                                 struct drm_file *file_priv)
1313 {
1314         struct drm_nouveau_private *dev_priv = dev->dev_private;
1315         struct drm_nouveau_getparam *getparam = data;
1316
1317         switch (getparam->param) {
1318         case NOUVEAU_GETPARAM_CHIPSET_ID:
1319                 getparam->value = dev_priv->chipset;
1320                 break;
1321         case NOUVEAU_GETPARAM_PCI_VENDOR:
1322                 getparam->value = dev->pci_vendor;
1323                 break;
1324         case NOUVEAU_GETPARAM_PCI_DEVICE:
1325                 getparam->value = dev->pci_device;
1326                 break;
1327         case NOUVEAU_GETPARAM_BUS_TYPE:
1328                 if (drm_pci_device_is_agp(dev))
1329                         getparam->value = NV_AGP;
1330                 else if (pci_is_pcie(dev->pdev))
1331                         getparam->value = NV_PCIE;
1332                 else
1333                         getparam->value = NV_PCI;
1334                 break;
1335         case NOUVEAU_GETPARAM_FB_SIZE:
1336                 getparam->value = dev_priv->fb_available_size;
1337                 break;
1338         case NOUVEAU_GETPARAM_AGP_SIZE:
1339                 getparam->value = dev_priv->gart_info.aper_size;
1340                 break;
1341         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1342                 getparam->value = 0; /* deprecated */
1343                 break;
1344         case NOUVEAU_GETPARAM_PTIMER_TIME:
1345                 getparam->value = dev_priv->engine.timer.read(dev);
1346                 break;
1347         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1348                 getparam->value = 1;
1349                 break;
1350         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1351                 getparam->value = 1;
1352                 break;
1353         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1354                 /* NV40 and NV50 versions are quite different, but register
1355                  * address is the same. User is supposed to know the card
1356                  * family anyway... */
1357                 if (dev_priv->chipset >= 0x40) {
1358                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1359                         break;
1360                 }
1361                 /* FALLTHRU */
1362         default:
1363                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1364                 return -EINVAL;
1365         }
1366
1367         return 0;
1368 }
1369
1370 int
1371 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1372                        struct drm_file *file_priv)
1373 {
1374         struct drm_nouveau_setparam *setparam = data;
1375
1376         switch (setparam->param) {
1377         default:
1378                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1379                 return -EINVAL;
1380         }
1381
1382         return 0;
1383 }
1384
1385 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1386 bool
1387 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1388                 uint32_t reg, uint32_t mask, uint32_t val)
1389 {
1390         struct drm_nouveau_private *dev_priv = dev->dev_private;
1391         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1392         uint64_t start = ptimer->read(dev);
1393
1394         do {
1395                 if ((nv_rd32(dev, reg) & mask) == val)
1396                         return true;
1397         } while (ptimer->read(dev) - start < timeout);
1398
1399         return false;
1400 }
1401
1402 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1403 bool
1404 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1405                 uint32_t reg, uint32_t mask, uint32_t val)
1406 {
1407         struct drm_nouveau_private *dev_priv = dev->dev_private;
1408         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1409         uint64_t start = ptimer->read(dev);
1410
1411         do {
1412                 if ((nv_rd32(dev, reg) & mask) != val)
1413                         return true;
1414         } while (ptimer->read(dev) - start < timeout);
1415
1416         return false;
1417 }
1418
1419 /* Wait until cond(data) == true, up until timeout has hit */
1420 bool
1421 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1422                 bool (*cond)(void *), void *data)
1423 {
1424         struct drm_nouveau_private *dev_priv = dev->dev_private;
1425         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1426         u64 start = ptimer->read(dev);
1427
1428         do {
1429                 if (cond(data) == true)
1430                         return true;
1431         } while (ptimer->read(dev) - start < timeout);
1432
1433         return false;
1434 }
1435
1436 /* Waits for PGRAPH to go completely idle */
1437 bool nouveau_wait_for_idle(struct drm_device *dev)
1438 {
1439         struct drm_nouveau_private *dev_priv = dev->dev_private;
1440         uint32_t mask = ~0;
1441
1442         if (dev_priv->card_type == NV_40)
1443                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1444
1445         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1446                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1447                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1448                 return false;
1449         }
1450
1451         return true;
1452 }
1453