drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_gpio.h"
  40 #include "nouveau_pm.h"
  41 #include "nv50_display.h"
  42 #include "nouveau_fence.h"
  43 #include "nouveau_software.h"
  44
  45 static void nouveau_stub_takedown(struct drm_device *dev) {}
  46 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  47
  48 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  49 {
  50         struct drm_nouveau_private *dev_priv = dev->dev_private;
  51         struct nouveau_engine *engine = &dev_priv->engine;
  52
  53         switch (dev_priv->chipset & 0xf0) {
  54         case 0x00:
  55                 engine->instmem.init            = nv04_instmem_init;
  56                 engine->instmem.takedown        = nv04_instmem_takedown;
  57                 engine->instmem.suspend         = nv04_instmem_suspend;
  58                 engine->instmem.resume          = nv04_instmem_resume;
  59                 engine->instmem.get             = nv04_instmem_get;
  60                 engine->instmem.put             = nv04_instmem_put;
  61                 engine->instmem.map             = nv04_instmem_map;
  62                 engine->instmem.unmap           = nv04_instmem_unmap;
  63                 engine->instmem.flush           = nv04_instmem_flush;
  64                 engine->mc.init                 = nv04_mc_init;
  65                 engine->mc.takedown             = nv04_mc_takedown;
  66                 engine->timer.init              = nv04_timer_init;
  67                 engine->timer.read              = nv04_timer_read;
  68                 engine->timer.takedown          = nv04_timer_takedown;
  69                 engine->fb.init                 = nv04_fb_init;
  70                 engine->fb.takedown             = nv04_fb_takedown;
  71                 engine->fifo.channels           = 16;
  72                 engine->fifo.init               = nv04_fifo_init;
  73                 engine->fifo.takedown           = nv04_fifo_fini;
  74                 engine->fifo.create_context     = nv04_fifo_create_context;
  75                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  76                 engine->fifo.load_context       = nv04_fifo_load_context;
  77                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  78                 engine->display.early_init      = nv04_display_early_init;
  79                 engine->display.late_takedown   = nv04_display_late_takedown;
  80                 engine->display.create          = nv04_display_create;
  81                 engine->display.destroy         = nv04_display_destroy;
  82                 engine->display.init            = nv04_display_init;
  83                 engine->display.fini            = nv04_display_fini;
  84                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  85                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  86                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  87                 engine->vram.init               = nv04_fb_vram_init;
  88                 engine->vram.takedown           = nouveau_stub_takedown;
  89                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  90                 break;
  91         case 0x10:
  92                 engine->instmem.init            = nv04_instmem_init;
  93                 engine->instmem.takedown        = nv04_instmem_takedown;
  94                 engine->instmem.suspend         = nv04_instmem_suspend;
  95                 engine->instmem.resume          = nv04_instmem_resume;
  96                 engine->instmem.get             = nv04_instmem_get;
  97                 engine->instmem.put             = nv04_instmem_put;
  98                 engine->instmem.map             = nv04_instmem_map;
  99                 engine->instmem.unmap           = nv04_instmem_unmap;
 100                 engine->instmem.flush           = nv04_instmem_flush;
 101                 engine->mc.init                 = nv04_mc_init;
 102                 engine->mc.takedown             = nv04_mc_takedown;
 103                 engine->timer.init              = nv04_timer_init;
 104                 engine->timer.read              = nv04_timer_read;
 105                 engine->timer.takedown          = nv04_timer_takedown;
 106                 engine->fb.init                 = nv10_fb_init;
 107                 engine->fb.takedown             = nv10_fb_takedown;
 108                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 109                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 110                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 111                 engine->fifo.channels           = 32;
 112                 engine->fifo.init               = nv10_fifo_init;
 113                 engine->fifo.takedown           = nv04_fifo_fini;
 114                 engine->fifo.create_context     = nv10_fifo_create_context;
 115                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 116                 engine->fifo.load_context       = nv10_fifo_load_context;
 117                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 118                 engine->display.early_init      = nv04_display_early_init;
 119                 engine->display.late_takedown   = nv04_display_late_takedown;
 120                 engine->display.create          = nv04_display_create;
 121                 engine->display.destroy         = nv04_display_destroy;
 122                 engine->display.init            = nv04_display_init;
 123                 engine->display.fini            = nv04_display_fini;
 124                 engine->gpio.drive              = nv10_gpio_drive;
 125                 engine->gpio.sense              = nv10_gpio_sense;
 126                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 127                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 128                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 129                 if (dev_priv->chipset == 0x1a ||
 130                     dev_priv->chipset == 0x1f)
 131                         engine->vram.init       = nv1a_fb_vram_init;
 132                 else
 133                         engine->vram.init       = nv10_fb_vram_init;
 134                 engine->vram.takedown           = nouveau_stub_takedown;
 135                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 136                 break;
 137         case 0x20:
 138                 engine->instmem.init            = nv04_instmem_init;
 139                 engine->instmem.takedown        = nv04_instmem_takedown;
 140                 engine->instmem.suspend         = nv04_instmem_suspend;
 141                 engine->instmem.resume          = nv04_instmem_resume;
 142                 engine->instmem.get             = nv04_instmem_get;
 143                 engine->instmem.put             = nv04_instmem_put;
 144                 engine->instmem.map             = nv04_instmem_map;
 145                 engine->instmem.unmap           = nv04_instmem_unmap;
 146                 engine->instmem.flush           = nv04_instmem_flush;
 147                 engine->mc.init                 = nv04_mc_init;
 148                 engine->mc.takedown             = nv04_mc_takedown;
 149                 engine->timer.init              = nv04_timer_init;
 150                 engine->timer.read              = nv04_timer_read;
 151                 engine->timer.takedown          = nv04_timer_takedown;
 152                 engine->fb.init                 = nv20_fb_init;
 153                 engine->fb.takedown             = nv20_fb_takedown;
 154                 engine->fb.init_tile_region     = nv20_fb_init_tile_region;
 155                 engine->fb.set_tile_region      = nv20_fb_set_tile_region;
 156                 engine->fb.free_tile_region     = nv20_fb_free_tile_region;
 157                 engine->fifo.channels           = 32;
 158                 engine->fifo.init               = nv10_fifo_init;
 159                 engine->fifo.takedown           = nv04_fifo_fini;
 160                 engine->fifo.create_context     = nv10_fifo_create_context;
 161                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 162                 engine->fifo.load_context       = nv10_fifo_load_context;
 163                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 164                 engine->display.early_init      = nv04_display_early_init;
 165                 engine->display.late_takedown   = nv04_display_late_takedown;
 166                 engine->display.create          = nv04_display_create;
 167                 engine->display.destroy         = nv04_display_destroy;
 168                 engine->display.init            = nv04_display_init;
 169                 engine->display.fini            = nv04_display_fini;
 170                 engine->gpio.drive              = nv10_gpio_drive;
 171                 engine->gpio.sense              = nv10_gpio_sense;
 172                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 173                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 174                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 175                 engine->vram.init               = nv20_fb_vram_init;
 176                 engine->vram.takedown           = nouveau_stub_takedown;
 177                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 178                 break;
 179         case 0x30:
 180                 engine->instmem.init            = nv04_instmem_init;
 181                 engine->instmem.takedown        = nv04_instmem_takedown;
 182                 engine->instmem.suspend         = nv04_instmem_suspend;
 183                 engine->instmem.resume          = nv04_instmem_resume;
 184                 engine->instmem.get             = nv04_instmem_get;
 185                 engine->instmem.put             = nv04_instmem_put;
 186                 engine->instmem.map             = nv04_instmem_map;
 187                 engine->instmem.unmap           = nv04_instmem_unmap;
 188                 engine->instmem.flush           = nv04_instmem_flush;
 189                 engine->mc.init                 = nv04_mc_init;
 190                 engine->mc.takedown             = nv04_mc_takedown;
 191                 engine->timer.init              = nv04_timer_init;
 192                 engine->timer.read              = nv04_timer_read;
 193                 engine->timer.takedown          = nv04_timer_takedown;
 194                 engine->fb.init                 = nv30_fb_init;
 195                 engine->fb.takedown             = nv30_fb_takedown;
 196                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 197                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 198                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 199                 engine->fifo.channels           = 32;
 200                 engine->fifo.init               = nv10_fifo_init;
 201                 engine->fifo.takedown           = nv04_fifo_fini;
 202                 engine->fifo.create_context     = nv10_fifo_create_context;
 203                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 204                 engine->fifo.load_context       = nv10_fifo_load_context;
 205                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 206                 engine->display.early_init      = nv04_display_early_init;
 207                 engine->display.late_takedown   = nv04_display_late_takedown;
 208                 engine->display.create          = nv04_display_create;
 209                 engine->display.destroy         = nv04_display_destroy;
 210                 engine->display.init            = nv04_display_init;
 211                 engine->display.fini            = nv04_display_fini;
 212                 engine->gpio.drive              = nv10_gpio_drive;
 213                 engine->gpio.sense              = nv10_gpio_sense;
 214                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 215                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 216                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 217                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 218                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 219                 engine->vram.init               = nv20_fb_vram_init;
 220                 engine->vram.takedown           = nouveau_stub_takedown;
 221                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 222                 break;
 223         case 0x40:
 224         case 0x60:
 225                 engine->instmem.init            = nv04_instmem_init;
 226                 engine->instmem.takedown        = nv04_instmem_takedown;
 227                 engine->instmem.suspend         = nv04_instmem_suspend;
 228                 engine->instmem.resume          = nv04_instmem_resume;
 229                 engine->instmem.get             = nv04_instmem_get;
 230                 engine->instmem.put             = nv04_instmem_put;
 231                 engine->instmem.map             = nv04_instmem_map;
 232                 engine->instmem.unmap           = nv04_instmem_unmap;
 233                 engine->instmem.flush           = nv04_instmem_flush;
 234                 engine->mc.init                 = nv40_mc_init;
 235                 engine->mc.takedown             = nv40_mc_takedown;
 236                 engine->timer.init              = nv04_timer_init;
 237                 engine->timer.read              = nv04_timer_read;
 238                 engine->timer.takedown          = nv04_timer_takedown;
 239                 engine->fb.init                 = nv40_fb_init;
 240                 engine->fb.takedown             = nv40_fb_takedown;
 241                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 242                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 243                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 244                 engine->fifo.channels           = 32;
 245                 engine->fifo.init               = nv40_fifo_init;
 246                 engine->fifo.takedown           = nv04_fifo_fini;
 247                 engine->fifo.create_context     = nv40_fifo_create_context;
 248                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 249                 engine->fifo.load_context       = nv40_fifo_load_context;
 250                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 251                 engine->display.early_init      = nv04_display_early_init;
 252                 engine->display.late_takedown   = nv04_display_late_takedown;
 253                 engine->display.create          = nv04_display_create;
 254                 engine->display.destroy         = nv04_display_destroy;
 255                 engine->display.init            = nv04_display_init;
 256                 engine->display.fini            = nv04_display_fini;
 257                 engine->gpio.init               = nv10_gpio_init;
 258                 engine->gpio.fini               = nv10_gpio_fini;
 259                 engine->gpio.drive              = nv10_gpio_drive;
 260                 engine->gpio.sense              = nv10_gpio_sense;
 261                 engine->gpio.irq_enable         = nv10_gpio_irq_enable;
 262                 engine->pm.clocks_get           = nv40_pm_clocks_get;
 263                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
 264                 engine->pm.clocks_set           = nv40_pm_clocks_set;
 265                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 266                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 267                 engine->pm.temp_get             = nv40_temp_get;
 268                 engine->pm.pwm_get              = nv40_pm_pwm_get;
 269                 engine->pm.pwm_set              = nv40_pm_pwm_set;
 270                 engine->vram.init               = nv40_fb_vram_init;
 271                 engine->vram.takedown           = nouveau_stub_takedown;
 272                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 273                 break;
 274         case 0x50:
 275         case 0x80: /* gotta love NVIDIA's consistency.. */
 276         case 0x90:
 277         case 0xa0:
 278                 engine->instmem.init            = nv50_instmem_init;
 279                 engine->instmem.takedown        = nv50_instmem_takedown;
 280                 engine->instmem.suspend         = nv50_instmem_suspend;
 281                 engine->instmem.resume          = nv50_instmem_resume;
 282                 engine->instmem.get             = nv50_instmem_get;
 283                 engine->instmem.put             = nv50_instmem_put;
 284                 engine->instmem.map             = nv50_instmem_map;
 285                 engine->instmem.unmap           = nv50_instmem_unmap;
 286                 if (dev_priv->chipset == 0x50)
 287                         engine->instmem.flush   = nv50_instmem_flush;
 288                 else
 289                         engine->instmem.flush   = nv84_instmem_flush;
 290                 engine->mc.init                 = nv50_mc_init;
 291                 engine->mc.takedown             = nv50_mc_takedown;
 292                 engine->timer.init              = nv04_timer_init;
 293                 engine->timer.read              = nv04_timer_read;
 294                 engine->timer.takedown          = nv04_timer_takedown;
 295                 engine->fb.init                 = nv50_fb_init;
 296                 engine->fb.takedown             = nv50_fb_takedown;
 297                 engine->fifo.channels           = 128;
 298                 engine->fifo.init               = nv50_fifo_init;
 299                 engine->fifo.takedown           = nv50_fifo_takedown;
 300                 engine->fifo.create_context     = nv50_fifo_create_context;
 301                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 302                 engine->fifo.load_context       = nv50_fifo_load_context;
 303                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 304                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 305                 engine->display.early_init      = nv50_display_early_init;
 306                 engine->display.late_takedown   = nv50_display_late_takedown;
 307                 engine->display.create          = nv50_display_create;
 308                 engine->display.destroy         = nv50_display_destroy;
 309                 engine->display.init            = nv50_display_init;
 310                 engine->display.fini            = nv50_display_fini;
 311                 engine->gpio.init               = nv50_gpio_init;
 312                 engine->gpio.fini               = nv50_gpio_fini;
 313                 engine->gpio.drive              = nv50_gpio_drive;
 314                 engine->gpio.sense              = nv50_gpio_sense;
 315                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 316                 switch (dev_priv->chipset) {
 317                 case 0x84:
 318                 case 0x86:
 319                 case 0x92:
 320                 case 0x94:
 321                 case 0x96:
 322                 case 0x98:
 323                 case 0xa0:
 324                 case 0xaa:
 325                 case 0xac:
 326                 case 0x50:
 327                         engine->pm.clocks_get   = nv50_pm_clocks_get;
 328                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
 329                         engine->pm.clocks_set   = nv50_pm_clocks_set;
 330                         break;
 331                 default:
 332                         engine->pm.clocks_get   = nva3_pm_clocks_get;
 333                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
 334                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 335                         break;
 336                 }
 337                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 338                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 339                 if (dev_priv->chipset >= 0x84)
 340                         engine->pm.temp_get     = nv84_temp_get;
 341                 else
 342                         engine->pm.temp_get     = nv40_temp_get;
 343                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 344                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 345                 engine->vram.init               = nv50_vram_init;
 346                 engine->vram.takedown           = nv50_vram_fini;
 347                 engine->vram.get                = nv50_vram_new;
 348                 engine->vram.put                = nv50_vram_del;
 349                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 350                 break;
 351         case 0xc0:
 352                 engine->instmem.init            = nvc0_instmem_init;
 353                 engine->instmem.takedown        = nvc0_instmem_takedown;
 354                 engine->instmem.suspend         = nvc0_instmem_suspend;
 355                 engine->instmem.resume          = nvc0_instmem_resume;
 356                 engine->instmem.get             = nv50_instmem_get;
 357                 engine->instmem.put             = nv50_instmem_put;
 358                 engine->instmem.map             = nv50_instmem_map;
 359                 engine->instmem.unmap           = nv50_instmem_unmap;
 360                 engine->instmem.flush           = nv84_instmem_flush;
 361                 engine->mc.init                 = nv50_mc_init;
 362                 engine->mc.takedown             = nv50_mc_takedown;
 363                 engine->timer.init              = nv04_timer_init;
 364                 engine->timer.read              = nv04_timer_read;
 365                 engine->timer.takedown          = nv04_timer_takedown;
 366                 engine->fb.init                 = nvc0_fb_init;
 367                 engine->fb.takedown             = nvc0_fb_takedown;
 368                 engine->fifo.channels           = 128;
 369                 engine->fifo.init               = nvc0_fifo_init;
 370                 engine->fifo.takedown           = nvc0_fifo_takedown;
 371                 engine->fifo.create_context     = nvc0_fifo_create_context;
 372                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 373                 engine->fifo.load_context       = nvc0_fifo_load_context;
 374                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 375                 engine->display.early_init      = nv50_display_early_init;
 376                 engine->display.late_takedown   = nv50_display_late_takedown;
 377                 engine->display.create          = nv50_display_create;
 378                 engine->display.destroy         = nv50_display_destroy;
 379                 engine->display.init            = nv50_display_init;
 380                 engine->display.fini            = nv50_display_fini;
 381                 engine->gpio.init               = nv50_gpio_init;
 382                 engine->gpio.fini               = nv50_gpio_fini;
 383                 engine->gpio.drive              = nv50_gpio_drive;
 384                 engine->gpio.sense              = nv50_gpio_sense;
 385                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 386                 engine->vram.init               = nvc0_vram_init;
 387                 engine->vram.takedown           = nv50_vram_fini;
 388                 engine->vram.get                = nvc0_vram_new;
 389                 engine->vram.put                = nv50_vram_del;
 390                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 391                 engine->pm.temp_get             = nv84_temp_get;
 392                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 393                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 394                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 395                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 396                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 397                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 398                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 399                 break;
 400         case 0xd0:
 401                 engine->instmem.init            = nvc0_instmem_init;
 402                 engine->instmem.takedown        = nvc0_instmem_takedown;
 403                 engine->instmem.suspend         = nvc0_instmem_suspend;
 404                 engine->instmem.resume          = nvc0_instmem_resume;
 405                 engine->instmem.get             = nv50_instmem_get;
 406                 engine->instmem.put             = nv50_instmem_put;
 407                 engine->instmem.map             = nv50_instmem_map;
 408                 engine->instmem.unmap           = nv50_instmem_unmap;
 409                 engine->instmem.flush           = nv84_instmem_flush;
 410                 engine->mc.init                 = nv50_mc_init;
 411                 engine->mc.takedown             = nv50_mc_takedown;
 412                 engine->timer.init              = nv04_timer_init;
 413                 engine->timer.read              = nv04_timer_read;
 414                 engine->timer.takedown          = nv04_timer_takedown;
 415                 engine->fb.init                 = nvc0_fb_init;
 416                 engine->fb.takedown             = nvc0_fb_takedown;
 417                 engine->fifo.channels           = 128;
 418                 engine->fifo.init               = nvc0_fifo_init;
 419                 engine->fifo.takedown           = nvc0_fifo_takedown;
 420                 engine->fifo.create_context     = nvc0_fifo_create_context;
 421                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 422                 engine->fifo.load_context       = nvc0_fifo_load_context;
 423                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 424                 engine->display.early_init      = nouveau_stub_init;
 425                 engine->display.late_takedown   = nouveau_stub_takedown;
 426                 engine->display.create          = nvd0_display_create;
 427                 engine->display.destroy         = nvd0_display_destroy;
 428                 engine->display.init            = nvd0_display_init;
 429                 engine->display.fini            = nvd0_display_fini;
 430                 engine->gpio.init               = nv50_gpio_init;
 431                 engine->gpio.fini               = nv50_gpio_fini;
 432                 engine->gpio.drive              = nvd0_gpio_drive;
 433                 engine->gpio.sense              = nvd0_gpio_sense;
 434                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 435                 engine->vram.init               = nvc0_vram_init;
 436                 engine->vram.takedown           = nv50_vram_fini;
 437                 engine->vram.get                = nvc0_vram_new;
 438                 engine->vram.put                = nv50_vram_del;
 439                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 440                 engine->pm.temp_get             = nv84_temp_get;
 441                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 442                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 443                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 444                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 445                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 446                 break;
 447         case 0xe0:
 448                 engine->instmem.init            = nvc0_instmem_init;
 449                 engine->instmem.takedown        = nvc0_instmem_takedown;
 450                 engine->instmem.suspend         = nvc0_instmem_suspend;
 451                 engine->instmem.resume          = nvc0_instmem_resume;
 452                 engine->instmem.get             = nv50_instmem_get;
 453                 engine->instmem.put             = nv50_instmem_put;
 454                 engine->instmem.map             = nv50_instmem_map;
 455                 engine->instmem.unmap           = nv50_instmem_unmap;
 456                 engine->instmem.flush           = nv84_instmem_flush;
 457                 engine->mc.init                 = nv50_mc_init;
 458                 engine->mc.takedown             = nv50_mc_takedown;
 459                 engine->timer.init              = nv04_timer_init;
 460                 engine->timer.read              = nv04_timer_read;
 461                 engine->timer.takedown          = nv04_timer_takedown;
 462                 engine->fb.init                 = nvc0_fb_init;
 463                 engine->fb.takedown             = nvc0_fb_takedown;
 464                 engine->fifo.channels           = 4096;
 465                 engine->fifo.init               = nve0_fifo_init;
 466                 engine->fifo.takedown           = nve0_fifo_takedown;
 467                 engine->fifo.create_context     = nve0_fifo_create_context;
 468                 engine->fifo.destroy_context    = nve0_fifo_destroy_context;
 469                 engine->fifo.load_context       = nvc0_fifo_load_context;
 470                 engine->fifo.unload_context     = nve0_fifo_unload_context;
 471                 engine->display.early_init      = nouveau_stub_init;
 472                 engine->display.late_takedown   = nouveau_stub_takedown;
 473                 engine->display.create          = nvd0_display_create;
 474                 engine->display.destroy         = nvd0_display_destroy;
 475                 engine->display.init            = nvd0_display_init;
 476                 engine->display.fini            = nvd0_display_fini;
 477                 engine->gpio.init               = nv50_gpio_init;
 478                 engine->gpio.fini               = nv50_gpio_fini;
 479                 engine->gpio.drive              = nvd0_gpio_drive;
 480                 engine->gpio.sense              = nvd0_gpio_sense;
 481                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 482                 engine->vram.init               = nvc0_vram_init;
 483                 engine->vram.takedown           = nv50_vram_fini;
 484                 engine->vram.get                = nvc0_vram_new;
 485                 engine->vram.put                = nv50_vram_del;
 486                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 487                 break;
 488         default:
 489                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 490                 return 1;
 491         }
 492
 493         /* headless mode */
 494         if (nouveau_modeset == 2) {
 495                 engine->display.early_init = nouveau_stub_init;
 496                 engine->display.late_takedown = nouveau_stub_takedown;
 497                 engine->display.create = nouveau_stub_init;
 498                 engine->display.init = nouveau_stub_init;
 499                 engine->display.destroy = nouveau_stub_takedown;
 500         }
 501
 502         return 0;
 503 }
 504
 505 static unsigned int
 506 nouveau_vga_set_decode(void *priv, bool state)
 507 {
 508         struct drm_device *dev = priv;
 509         struct drm_nouveau_private *dev_priv = dev->dev_private;
 510
 511         if (dev_priv->chipset >= 0x40)
 512                 nv_wr32(dev, 0x88054, state);
 513         else
 514                 nv_wr32(dev, 0x1854, state);
 515
 516         if (state)
 517                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 518                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 519         else
 520                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 521 }
 522
 523 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 524                                          enum vga_switcheroo_state state)
 525 {
 526         struct drm_device *dev = pci_get_drvdata(pdev);
 527         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 528         if (state == VGA_SWITCHEROO_ON) {
 529                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 530                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 531                 nouveau_pci_resume(pdev);
 532                 drm_kms_helper_poll_enable(dev);
 533                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 534         } else {
 535                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 536                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 537                 drm_kms_helper_poll_disable(dev);
 538                 nouveau_switcheroo_optimus_dsm();
 539                 nouveau_pci_suspend(pdev, pmm);
 540                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 541         }
 542 }
 543
 544 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 545 {
 546         struct drm_device *dev = pci_get_drvdata(pdev);
 547         nouveau_fbcon_output_poll_changed(dev);
 548 }
 549
 550 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 551 {
 552         struct drm_device *dev = pci_get_drvdata(pdev);
 553         bool can_switch;
 554
 555         spin_lock(&dev->count_lock);
 556         can_switch = (dev->open_count == 0);
 557         spin_unlock(&dev->count_lock);
 558         return can_switch;
 559 }
 560
 561 static void
 562 nouveau_card_channel_fini(struct drm_device *dev)
 563 {
 564         struct drm_nouveau_private *dev_priv = dev->dev_private;
 565
 566         if (dev_priv->channel)
 567                 nouveau_channel_put_unlocked(&dev_priv->channel);
 568 }
 569
 570 static int
 571 nouveau_card_channel_init(struct drm_device *dev)
 572 {
 573         struct drm_nouveau_private *dev_priv = dev->dev_private;
 574         struct nouveau_channel *chan;
 575         int ret, oclass;
 576
 577         ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT);
 578         dev_priv->channel = chan;
 579         if (ret)
 580                 return ret;
 581
 582         mutex_unlock(&dev_priv->channel->mutex);
 583
 584         if (dev_priv->card_type <= NV_50) {
 585                 if (dev_priv->card_type < NV_50)
 586                         oclass = 0x0039;
 587                 else
 588                         oclass = 0x5039;
 589
 590                 ret = nouveau_gpuobj_gr_new(chan, NvM2MF, oclass);
 591                 if (ret)
 592                         goto error;
 593
 594                 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
 595                                              &chan->m2mf_ntfy);
 596                 if (ret)
 597                         goto error;
 598
 599                 ret = RING_SPACE(chan, 6);
 600                 if (ret)
 601                         goto error;
 602
 603                 BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
 604                 OUT_RING  (chan, NvM2MF);
 605                 BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
 606                 OUT_RING  (chan, NvNotify0);
 607                 OUT_RING  (chan, chan->vram_handle);
 608                 OUT_RING  (chan, chan->gart_handle);
 609         } else
 610         if (dev_priv->card_type <= NV_D0) {
 611                 ret = nouveau_gpuobj_gr_new(chan, 0x9039, 0x9039);
 612                 if (ret)
 613                         goto error;
 614
 615                 ret = RING_SPACE(chan, 2);
 616                 if (ret)
 617                         goto error;
 618
 619                 BEGIN_NVC0(chan, NvSubM2MF, 0x0000, 1);
 620                 OUT_RING  (chan, 0x00009039);
 621         } else
 622         if (dev_priv->card_type <= NV_E0) {
 623                 /* not used, but created to get a graph context */
 624                 ret = nouveau_gpuobj_gr_new(chan, 0xa040, 0xa040);
 625                 if (ret)
 626                         goto error;
 627
 628                 /* bind strange copy engine to subchannel 4 (fixed...) */
 629                 ret = RING_SPACE(chan, 2);
 630                 if (ret)
 631                         goto error;
 632
 633                 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
 634                 OUT_RING  (chan, 0x0000a0b5);
 635         }
 636
 637         FIRE_RING (chan);
 638 error:
 639         if (ret)
 640                 nouveau_card_channel_fini(dev);
 641         return ret;
 642 }
 643
 644 static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = {
 645         .set_gpu_state = nouveau_switcheroo_set_state,
 646         .reprobe = nouveau_switcheroo_reprobe,
 647         .can_switch = nouveau_switcheroo_can_switch,
 648 };
 649
 650 int
 651 nouveau_card_init(struct drm_device *dev)
 652 {
 653         struct drm_nouveau_private *dev_priv = dev->dev_private;
 654         struct nouveau_engine *engine;
 655         int ret, e = 0;
 656
 657         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 658         vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
 659
 660         /* Initialise internal driver API hooks */
 661         ret = nouveau_init_engine_ptrs(dev);
 662         if (ret)
 663                 goto out;
 664         engine = &dev_priv->engine;
 665         spin_lock_init(&dev_priv->channels.lock);
 666         spin_lock_init(&dev_priv->tile.lock);
 667         spin_lock_init(&dev_priv->context_switch_lock);
 668         spin_lock_init(&dev_priv->vm_lock);
 669
 670         /* Make the CRTCs and I2C buses accessible */
 671         ret = engine->display.early_init(dev);
 672         if (ret)
 673                 goto out;
 674
 675         /* Parse BIOS tables / Run init tables if card not POSTed */
 676         ret = nouveau_bios_init(dev);
 677         if (ret)
 678                 goto out_display_early;
 679
 680         /* workaround an odd issue on nvc1 by disabling the device's
 681          * nosnoop capability.  hopefully won't cause issues until a
 682          * better fix is found - assuming there is one...
 683          */
 684         if (dev_priv->chipset == 0xc1) {
 685                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 686         }
 687
 688         /* PMC */
 689         ret = engine->mc.init(dev);
 690         if (ret)
 691                 goto out_bios;
 692
 693         /* PTIMER */
 694         ret = engine->timer.init(dev);
 695         if (ret)
 696                 goto out_mc;
 697
 698         /* PFB */
 699         ret = engine->fb.init(dev);
 700         if (ret)
 701                 goto out_timer;
 702
 703         ret = engine->vram.init(dev);
 704         if (ret)
 705                 goto out_fb;
 706
 707         /* PGPIO */
 708         ret = nouveau_gpio_create(dev);
 709         if (ret)
 710                 goto out_vram;
 711
 712         ret = nouveau_gpuobj_init(dev);
 713         if (ret)
 714                 goto out_gpio;
 715
 716         ret = engine->instmem.init(dev);
 717         if (ret)
 718                 goto out_gpuobj;
 719
 720         ret = nouveau_mem_vram_init(dev);
 721         if (ret)
 722                 goto out_instmem;
 723
 724         ret = nouveau_mem_gart_init(dev);
 725         if (ret)
 726                 goto out_ttmvram;
 727
 728         if (!dev_priv->noaccel) {
 729                 switch (dev_priv->card_type) {
 730                 case NV_04:
 731                         nv04_fence_create(dev);
 732                         break;
 733                 case NV_10:
 734                 case NV_20:
 735                 case NV_30:
 736                 case NV_40:
 737                 case NV_50:
 738                         if (dev_priv->chipset < 0x84)
 739                                 nv10_fence_create(dev);
 740                         else
 741                                 nv84_fence_create(dev);
 742                         break;
 743                 case NV_C0:
 744                 case NV_D0:
 745                 case NV_E0:
 746                         nvc0_fence_create(dev);
 747                         break;
 748                 default:
 749                         break;
 750                 }
 751
 752                 switch (dev_priv->card_type) {
 753                 case NV_04:
 754                 case NV_10:
 755                 case NV_20:
 756                 case NV_30:
 757                 case NV_40:
 758                         nv04_software_create(dev);
 759                         break;
 760                 case NV_50:
 761                         nv50_software_create(dev);
 762                         break;
 763                 case NV_C0:
 764                 case NV_D0:
 765                 case NV_E0:
 766                         nvc0_software_create(dev);
 767                         break;
 768                 default:
 769                         break;
 770                 }
 771
 772                 switch (dev_priv->card_type) {
 773                 case NV_04:
 774                         nv04_graph_create(dev);
 775                         break;
 776                 case NV_10:
 777                         nv10_graph_create(dev);
 778                         break;
 779                 case NV_20:
 780                 case NV_30:
 781                         nv20_graph_create(dev);
 782                         break;
 783                 case NV_40:
 784                         nv40_graph_create(dev);
 785                         break;
 786                 case NV_50:
 787                         nv50_graph_create(dev);
 788                         break;
 789                 case NV_C0:
 790                 case NV_D0:
 791                         nvc0_graph_create(dev);
 792                         break;
 793                 case NV_E0:
 794                         nve0_graph_create(dev);
 795                         break;
 796                 default:
 797                         break;
 798                 }
 799
 800                 switch (dev_priv->chipset) {
 801                 case 0x84:
 802                 case 0x86:
 803                 case 0x92:
 804                 case 0x94:
 805                 case 0x96:
 806                 case 0xa0:
 807                         nv84_crypt_create(dev);
 808                         break;
 809                 case 0x98:
 810                 case 0xaa:
 811                 case 0xac:
 812                         nv98_crypt_create(dev);
 813                         break;
 814                 }
 815
 816                 switch (dev_priv->card_type) {
 817                 case NV_50:
 818                         switch (dev_priv->chipset) {
 819                         case 0xa3:
 820                         case 0xa5:
 821                         case 0xa8:
 822                         case 0xaf:
 823                                 nva3_copy_create(dev);
 824                                 break;
 825                         }
 826                         break;
 827                 case NV_C0:
 828                         nvc0_copy_create(dev, 0);
 829                         nvc0_copy_create(dev, 1);
 830                         break;
 831                 default:
 832                         break;
 833                 }
 834
 835                 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
 836                         nv84_bsp_create(dev);
 837                         nv84_vp_create(dev);
 838                         nv98_ppp_create(dev);
 839                 } else
 840                 if (dev_priv->chipset >= 0x84) {
 841                         nv50_mpeg_create(dev);
 842                         nv84_bsp_create(dev);
 843                         nv84_vp_create(dev);
 844                 } else
 845                 if (dev_priv->chipset >= 0x50) {
 846                         nv50_mpeg_create(dev);
 847                 } else
 848                 if (dev_priv->card_type == NV_40 ||
 849                     dev_priv->chipset == 0x31 ||
 850                     dev_priv->chipset == 0x34 ||
 851                     dev_priv->chipset == 0x36) {
 852                         nv31_mpeg_create(dev);
 853                 }
 854
 855                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 856                         if (dev_priv->eng[e]) {
 857                                 ret = dev_priv->eng[e]->init(dev, e);
 858                                 if (ret)
 859                                         goto out_engine;
 860                         }
 861                 }
 862
 863                 /* PFIFO */
 864                 ret = engine->fifo.init(dev);
 865                 if (ret)
 866                         goto out_engine;
 867         }
 868
 869         ret = nouveau_irq_init(dev);
 870         if (ret)
 871                 goto out_fifo;
 872
 873         ret = nouveau_display_create(dev);
 874         if (ret)
 875                 goto out_irq;
 876
 877         nouveau_backlight_init(dev);
 878         nouveau_pm_init(dev);
 879
 880         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 881                 ret = nouveau_card_channel_init(dev);
 882                 if (ret)
 883                         goto out_pm;
 884         }
 885
 886         if (dev->mode_config.num_crtc) {
 887                 ret = nouveau_display_init(dev);
 888                 if (ret)
 889                         goto out_chan;
 890
 891                 nouveau_fbcon_init(dev);
 892         }
 893
 894         return 0;
 895
 896 out_chan:
 897         nouveau_card_channel_fini(dev);
 898 out_pm:
 899         nouveau_pm_fini(dev);
 900         nouveau_backlight_exit(dev);
 901         nouveau_display_destroy(dev);
 902 out_irq:
 903         nouveau_irq_fini(dev);
 904 out_fifo:
 905         if (!dev_priv->noaccel)
 906                 engine->fifo.takedown(dev);
 907 out_engine:
 908         if (!dev_priv->noaccel) {
 909                 for (e = e - 1; e >= 0; e--) {
 910                         if (!dev_priv->eng[e])
 911                                 continue;
 912                         dev_priv->eng[e]->fini(dev, e, false);
 913                         dev_priv->eng[e]->destroy(dev,e );
 914                 }
 915         }
 916         nouveau_mem_gart_fini(dev);
 917 out_ttmvram:
 918         nouveau_mem_vram_fini(dev);
 919 out_instmem:
 920         engine->instmem.takedown(dev);
 921 out_gpuobj:
 922         nouveau_gpuobj_takedown(dev);
 923 out_gpio:
 924         nouveau_gpio_destroy(dev);
 925 out_vram:
 926         engine->vram.takedown(dev);
 927 out_fb:
 928         engine->fb.takedown(dev);
 929 out_timer:
 930         engine->timer.takedown(dev);
 931 out_mc:
 932         engine->mc.takedown(dev);
 933 out_bios:
 934         nouveau_bios_takedown(dev);
 935 out_display_early:
 936         engine->display.late_takedown(dev);
 937 out:
 938         vga_client_register(dev->pdev, NULL, NULL, NULL);
 939         return ret;
 940 }
 941
 942 static void nouveau_card_takedown(struct drm_device *dev)
 943 {
 944         struct drm_nouveau_private *dev_priv = dev->dev_private;
 945         struct nouveau_engine *engine = &dev_priv->engine;
 946         int e;
 947
 948         if (dev->mode_config.num_crtc) {
 949                 nouveau_fbcon_fini(dev);
 950                 nouveau_display_fini(dev);
 951         }
 952
 953         nouveau_card_channel_fini(dev);
 954         nouveau_pm_fini(dev);
 955         nouveau_backlight_exit(dev);
 956         nouveau_display_destroy(dev);
 957
 958         if (!dev_priv->noaccel) {
 959                 engine->fifo.takedown(dev);
 960                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 961                         if (dev_priv->eng[e]) {
 962                                 dev_priv->eng[e]->fini(dev, e, false);
 963                                 dev_priv->eng[e]->destroy(dev,e );
 964                         }
 965                 }
 966         }
 967
 968         if (dev_priv->vga_ram) {
 969                 nouveau_bo_unpin(dev_priv->vga_ram);
 970                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 971         }
 972
 973         mutex_lock(&dev->struct_mutex);
 974         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 975         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 976         mutex_unlock(&dev->struct_mutex);
 977         nouveau_mem_gart_fini(dev);
 978         nouveau_mem_vram_fini(dev);
 979
 980         engine->instmem.takedown(dev);
 981         nouveau_gpuobj_takedown(dev);
 982
 983         nouveau_gpio_destroy(dev);
 984         engine->vram.takedown(dev);
 985         engine->fb.takedown(dev);
 986         engine->timer.takedown(dev);
 987         engine->mc.takedown(dev);
 988
 989         nouveau_bios_takedown(dev);
 990         engine->display.late_takedown(dev);
 991
 992         nouveau_irq_fini(dev);
 993
 994         vga_client_register(dev->pdev, NULL, NULL, NULL);
 995 }
 996
 997 int
 998 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
 999 {
1000         struct drm_nouveau_private *dev_priv = dev->dev_private;
1001         struct nouveau_fpriv *fpriv;
1002         int ret;
1003
1004         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1005         if (unlikely(!fpriv))
1006                 return -ENOMEM;
1007
1008         spin_lock_init(&fpriv->lock);
1009         INIT_LIST_HEAD(&fpriv->channels);
1010
1011         if (dev_priv->card_type == NV_50) {
1012                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
1013                                      &fpriv->vm);
1014                 if (ret) {
1015                         kfree(fpriv);
1016                         return ret;
1017                 }
1018         } else
1019         if (dev_priv->card_type >= NV_C0) {
1020                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
1021                                      &fpriv->vm);
1022                 if (ret) {
1023                         kfree(fpriv);
1024                         return ret;
1025                 }
1026         }
1027
1028         file_priv->driver_priv = fpriv;
1029         return 0;
1030 }
1031
1032 /* here a client dies, release the stuff that was allocated for its
1033  * file_priv */
1034 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
1035 {
1036         nouveau_channel_cleanup(dev, file_priv);
1037 }
1038
1039 void
1040 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
1041 {
1042         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
1043         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
1044         kfree(fpriv);
1045 }
1046
1047 /* first module load, setup the mmio/fb mapping */
1048 /* KMS: we need mmio at load time, not when the first drm client opens. */
1049 int nouveau_firstopen(struct drm_device *dev)
1050 {
1051         return 0;
1052 }
1053
1054 /* if we have an OF card, copy vbios to RAMIN */
1055 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
1056 {
1057 #if defined(__powerpc__)
1058         int size, i;
1059         const uint32_t *bios;
1060         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
1061         if (!dn) {
1062                 NV_INFO(dev, "Unable to get the OF node\n");
1063                 return;
1064         }
1065
1066         bios = of_get_property(dn, "NVDA,BMP", &size);
1067         if (bios) {
1068                 for (i = 0; i < size; i += 4)
1069                         nv_wi32(dev, i, bios[i/4]);
1070                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
1071         } else {
1072                 NV_INFO(dev, "Unable to get the OF bios\n");
1073         }
1074 #endif
1075 }
1076
1077 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
1078 {
1079         struct pci_dev *pdev = dev->pdev;
1080         struct apertures_struct *aper = alloc_apertures(3);
1081         if (!aper)
1082                 return NULL;
1083
1084         aper->ranges[0].base = pci_resource_start(pdev, 1);
1085         aper->ranges[0].size = pci_resource_len(pdev, 1);
1086         aper->count = 1;
1087
1088         if (pci_resource_len(pdev, 2)) {
1089                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
1090                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
1091                 aper->count++;
1092         }
1093
1094         if (pci_resource_len(pdev, 3)) {
1095                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
1096                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
1097                 aper->count++;
1098         }
1099
1100         return aper;
1101 }
1102
1103 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
1104 {
1105         struct drm_nouveau_private *dev_priv = dev->dev_private;
1106         bool primary = false;
1107         dev_priv->apertures = nouveau_get_apertures(dev);
1108         if (!dev_priv->apertures)
1109                 return -ENOMEM;
1110
1111 #ifdef CONFIG_X86
1112         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1113 #endif
1114
1115         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
1116         return 0;
1117 }
1118
1119 int nouveau_load(struct drm_device *dev, unsigned long flags)
1120 {
1121         struct drm_nouveau_private *dev_priv;
1122         unsigned long long offset, length;
1123         uint32_t reg0 = ~0, strap;
1124         int ret;
1125
1126         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1127         if (!dev_priv) {
1128                 ret = -ENOMEM;
1129                 goto err_out;
1130         }
1131         dev->dev_private = dev_priv;
1132         dev_priv->dev = dev;
1133
1134         pci_set_master(dev->pdev);
1135
1136         dev_priv->flags = flags & NOUVEAU_FLAGS;
1137
1138         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1139                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1140
1141         /* first up, map the start of mmio and determine the chipset */
1142         dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
1143         if (dev_priv->mmio) {
1144 #ifdef __BIG_ENDIAN
1145                 /* put the card into big-endian mode if it's not */
1146                 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1147                         nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1148                 DRM_MEMORYBARRIER();
1149 #endif
1150
1151                 /* determine chipset and derive architecture from it */
1152                 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1153                 if ((reg0 & 0x0f000000) > 0) {
1154                         dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1155                         switch (dev_priv->chipset & 0xf0) {
1156                         case 0x10:
1157                         case 0x20:
1158                         case 0x30:
1159                                 dev_priv->card_type = dev_priv->chipset & 0xf0;
1160                                 break;
1161                         case 0x40:
1162                         case 0x60:
1163                                 dev_priv->card_type = NV_40;
1164                                 break;
1165                         case 0x50:
1166                         case 0x80:
1167                         case 0x90:
1168                         case 0xa0:
1169                                 dev_priv->card_type = NV_50;
1170                                 break;
1171                         case 0xc0:
1172                                 dev_priv->card_type = NV_C0;
1173                                 break;
1174                         case 0xd0:
1175                                 dev_priv->card_type = NV_D0;
1176                                 break;
1177                         case 0xe0:
1178                                 dev_priv->card_type = NV_E0;
1179                                 break;
1180                         default:
1181                                 break;
1182                         }
1183                 } else
1184                 if ((reg0 & 0xff00fff0) == 0x20004000) {
1185                         if (reg0 & 0x00f00000)
1186                                 dev_priv->chipset = 0x05;
1187                         else
1188                                 dev_priv->chipset = 0x04;
1189                         dev_priv->card_type = NV_04;
1190                 }
1191
1192                 iounmap(dev_priv->mmio);
1193         }
1194
1195         if (!dev_priv->card_type) {
1196                 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1197                 ret = -EINVAL;
1198                 goto err_priv;
1199         }
1200
1201         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1202                      dev_priv->card_type, reg0);
1203
1204         /* map the mmio regs, limiting the amount to preserve vmap space */
1205         offset = pci_resource_start(dev->pdev, 0);
1206         length = pci_resource_len(dev->pdev, 0);
1207         if (dev_priv->card_type < NV_E0)
1208                 length = min(length, (unsigned long long)0x00800000);
1209
1210         dev_priv->mmio = ioremap(offset, length);
1211         if (!dev_priv->mmio) {
1212                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1213                          "Please report your setup to " DRIVER_EMAIL "\n");
1214                 ret = -EINVAL;
1215                 goto err_priv;
1216         }
1217         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", offset);
1218
1219         /* determine frequency of timing crystal */
1220         strap = nv_rd32(dev, 0x101000);
1221         if ( dev_priv->chipset < 0x17 ||
1222             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1223                 strap &= 0x00000040;
1224         else
1225                 strap &= 0x00400040;
1226
1227         switch (strap) {
1228         case 0x00000000: dev_priv->crystal = 13500; break;
1229         case 0x00000040: dev_priv->crystal = 14318; break;
1230         case 0x00400000: dev_priv->crystal = 27000; break;
1231         case 0x00400040: dev_priv->crystal = 25000; break;
1232         }
1233
1234         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1235
1236         /* Determine whether we'll attempt acceleration or not, some
1237          * cards are disabled by default here due to them being known
1238          * non-functional, or never been tested due to lack of hw.
1239          */
1240         dev_priv->noaccel = !!nouveau_noaccel;
1241         if (nouveau_noaccel == -1) {
1242                 switch (dev_priv->chipset) {
1243                 case 0xd9: /* known broken */
1244                 case 0xe4: /* needs binary driver firmware */
1245                 case 0xe7: /* needs binary driver firmware */
1246                         NV_INFO(dev, "acceleration disabled by default, pass "
1247                                      "noaccel=0 to force enable\n");
1248                         dev_priv->noaccel = true;
1249                         break;
1250                 default:
1251                         dev_priv->noaccel = false;
1252                         break;
1253                 }
1254         }
1255
1256         ret = nouveau_remove_conflicting_drivers(dev);
1257         if (ret)
1258                 goto err_mmio;
1259
1260         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1261         if (dev_priv->card_type >= NV_40) {
1262                 int ramin_bar = 2;
1263                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1264                         ramin_bar = 3;
1265
1266                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1267                 dev_priv->ramin =
1268                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1269                                 dev_priv->ramin_size);
1270                 if (!dev_priv->ramin) {
1271                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1272                         ret = -ENOMEM;
1273                         goto err_mmio;
1274                 }
1275         } else {
1276                 dev_priv->ramin_size = 1 * 1024 * 1024;
1277                 dev_priv->ramin = ioremap(offset + NV_RAMIN,
1278                                           dev_priv->ramin_size);
1279                 if (!dev_priv->ramin) {
1280                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1281                         ret = -ENOMEM;
1282                         goto err_mmio;
1283                 }
1284         }
1285
1286         nouveau_OF_copy_vbios_to_ramin(dev);
1287
1288         /* Special flags */
1289         if (dev->pci_device == 0x01a0)
1290                 dev_priv->flags |= NV_NFORCE;
1291         else if (dev->pci_device == 0x01f0)
1292                 dev_priv->flags |= NV_NFORCE2;
1293
1294         /* For kernel modesetting, init card now and bring up fbcon */
1295         ret = nouveau_card_init(dev);
1296         if (ret)
1297                 goto err_ramin;
1298
1299         return 0;
1300
1301 err_ramin:
1302         iounmap(dev_priv->ramin);
1303 err_mmio:
1304         iounmap(dev_priv->mmio);
1305 err_priv:
1306         kfree(dev_priv);
1307         dev->dev_private = NULL;
1308 err_out:
1309         return ret;
1310 }
1311
1312 void nouveau_lastclose(struct drm_device *dev)
1313 {
1314         vga_switcheroo_process_delayed_switch();
1315 }
1316
1317 int nouveau_unload(struct drm_device *dev)
1318 {
1319         struct drm_nouveau_private *dev_priv = dev->dev_private;
1320
1321         nouveau_card_takedown(dev);
1322
1323         iounmap(dev_priv->mmio);
1324         iounmap(dev_priv->ramin);
1325
1326         kfree(dev_priv);
1327         dev->dev_private = NULL;
1328         return 0;
1329 }
1330
1331 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1332                                                 struct drm_file *file_priv)
1333 {
1334         struct drm_nouveau_private *dev_priv = dev->dev_private;
1335         struct drm_nouveau_getparam *getparam = data;
1336
1337         switch (getparam->param) {
1338         case NOUVEAU_GETPARAM_CHIPSET_ID:
1339                 getparam->value = dev_priv->chipset;
1340                 break;
1341         case NOUVEAU_GETPARAM_PCI_VENDOR:
1342                 getparam->value = dev->pci_vendor;
1343                 break;
1344         case NOUVEAU_GETPARAM_PCI_DEVICE:
1345                 getparam->value = dev->pci_device;
1346                 break;
1347         case NOUVEAU_GETPARAM_BUS_TYPE:
1348                 if (drm_pci_device_is_agp(dev))
1349                         getparam->value = NV_AGP;
1350                 else if (pci_is_pcie(dev->pdev))
1351                         getparam->value = NV_PCIE;
1352                 else
1353                         getparam->value = NV_PCI;
1354                 break;
1355         case NOUVEAU_GETPARAM_FB_SIZE:
1356                 getparam->value = dev_priv->fb_available_size;
1357                 break;
1358         case NOUVEAU_GETPARAM_AGP_SIZE:
1359                 getparam->value = dev_priv->gart_info.aper_size;
1360                 break;
1361         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1362                 getparam->value = 0; /* deprecated */
1363                 break;
1364         case NOUVEAU_GETPARAM_PTIMER_TIME:
1365                 getparam->value = dev_priv->engine.timer.read(dev);
1366                 break;
1367         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1368                 getparam->value = 1;
1369                 break;
1370         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1371                 getparam->value = 1;
1372                 break;
1373         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1374                 /* NV40 and NV50 versions are quite different, but register
1375                  * address is the same. User is supposed to know the card
1376                  * family anyway... */
1377                 if (dev_priv->chipset >= 0x40) {
1378                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1379                         break;
1380                 }
1381                 /* FALLTHRU */
1382         default:
1383                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1384                 return -EINVAL;
1385         }
1386
1387         return 0;
1388 }
1389
1390 int
1391 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1392                        struct drm_file *file_priv)
1393 {
1394         struct drm_nouveau_setparam *setparam = data;
1395
1396         switch (setparam->param) {
1397         default:
1398                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1399                 return -EINVAL;
1400         }
1401
1402         return 0;
1403 }
1404
1405 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1406 bool
1407 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1408                 uint32_t reg, uint32_t mask, uint32_t val)
1409 {
1410         struct drm_nouveau_private *dev_priv = dev->dev_private;
1411         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1412         uint64_t start = ptimer->read(dev);
1413
1414         do {
1415                 if ((nv_rd32(dev, reg) & mask) == val)
1416                         return true;
1417         } while (ptimer->read(dev) - start < timeout);
1418
1419         return false;
1420 }
1421
1422 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1423 bool
1424 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1425                 uint32_t reg, uint32_t mask, uint32_t val)
1426 {
1427         struct drm_nouveau_private *dev_priv = dev->dev_private;
1428         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1429         uint64_t start = ptimer->read(dev);
1430
1431         do {
1432                 if ((nv_rd32(dev, reg) & mask) != val)
1433                         return true;
1434         } while (ptimer->read(dev) - start < timeout);
1435
1436         return false;
1437 }
1438
1439 /* Wait until cond(data) == true, up until timeout has hit */
1440 bool
1441 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1442                 bool (*cond)(void *), void *data)
1443 {
1444         struct drm_nouveau_private *dev_priv = dev->dev_private;
1445         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1446         u64 start = ptimer->read(dev);
1447
1448         do {
1449                 if (cond(data) == true)
1450                         return true;
1451         } while (ptimer->read(dev) - start < timeout);
1452
1453         return false;
1454 }
1455
1456 /* Waits for PGRAPH to go completely idle */
1457 bool nouveau_wait_for_idle(struct drm_device *dev)
1458 {
1459         struct drm_nouveau_private *dev_priv = dev->dev_private;
1460         uint32_t mask = ~0;
1461
1462         if (dev_priv->card_type == NV_40)
1463                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1464
1465         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1466                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1467                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1468                 return false;
1469         }
1470
1471         return true;
1472 }
1473