drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_gpio.h"
  40 #include "nouveau_pm.h"
  41 #include "nv50_display.h"
  42 #include "nouveau_fence.h"
  43 #include "nouveau_software.h"
  44
  45 static void nouveau_stub_takedown(struct drm_device *dev) {}
  46 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  47
  48 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  49 {
  50         struct drm_nouveau_private *dev_priv = dev->dev_private;
  51         struct nouveau_engine *engine = &dev_priv->engine;
  52
  53         switch (dev_priv->chipset & 0xf0) {
  54         case 0x00:
  55                 engine->instmem.init            = nv04_instmem_init;
  56                 engine->instmem.takedown        = nv04_instmem_takedown;
  57                 engine->instmem.suspend         = nv04_instmem_suspend;
  58                 engine->instmem.resume          = nv04_instmem_resume;
  59                 engine->instmem.get             = nv04_instmem_get;
  60                 engine->instmem.put             = nv04_instmem_put;
  61                 engine->instmem.map             = nv04_instmem_map;
  62                 engine->instmem.unmap           = nv04_instmem_unmap;
  63                 engine->instmem.flush           = nv04_instmem_flush;
  64                 engine->mc.init                 = nv04_mc_init;
  65                 engine->mc.takedown             = nv04_mc_takedown;
  66                 engine->timer.init              = nv04_timer_init;
  67                 engine->timer.read              = nv04_timer_read;
  68                 engine->timer.takedown          = nv04_timer_takedown;
  69                 engine->fb.init                 = nv04_fb_init;
  70                 engine->fb.takedown             = nv04_fb_takedown;
  71                 engine->fifo.channels           = 16;
  72                 engine->fifo.init               = nv04_fifo_init;
  73                 engine->fifo.takedown           = nv04_fifo_fini;
  74                 engine->fifo.disable            = nv04_fifo_disable;
  75                 engine->fifo.enable             = nv04_fifo_enable;
  76                 engine->fifo.reassign           = nv04_fifo_reassign;
  77                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  78                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  79                 engine->fifo.create_context     = nv04_fifo_create_context;
  80                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  81                 engine->fifo.load_context       = nv04_fifo_load_context;
  82                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  83                 engine->display.early_init      = nv04_display_early_init;
  84                 engine->display.late_takedown   = nv04_display_late_takedown;
  85                 engine->display.create          = nv04_display_create;
  86                 engine->display.destroy         = nv04_display_destroy;
  87                 engine->display.init            = nv04_display_init;
  88                 engine->display.fini            = nv04_display_fini;
  89                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  90                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  91                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  92                 engine->vram.init               = nv04_fb_vram_init;
  93                 engine->vram.takedown           = nouveau_stub_takedown;
  94                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  95                 break;
  96         case 0x10:
  97                 engine->instmem.init            = nv04_instmem_init;
  98                 engine->instmem.takedown        = nv04_instmem_takedown;
  99                 engine->instmem.suspend         = nv04_instmem_suspend;
 100                 engine->instmem.resume          = nv04_instmem_resume;
 101                 engine->instmem.get             = nv04_instmem_get;
 102                 engine->instmem.put             = nv04_instmem_put;
 103                 engine->instmem.map             = nv04_instmem_map;
 104                 engine->instmem.unmap           = nv04_instmem_unmap;
 105                 engine->instmem.flush           = nv04_instmem_flush;
 106                 engine->mc.init                 = nv04_mc_init;
 107                 engine->mc.takedown             = nv04_mc_takedown;
 108                 engine->timer.init              = nv04_timer_init;
 109                 engine->timer.read              = nv04_timer_read;
 110                 engine->timer.takedown          = nv04_timer_takedown;
 111                 engine->fb.init                 = nv10_fb_init;
 112                 engine->fb.takedown             = nv10_fb_takedown;
 113                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 114                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 115                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 116                 engine->fifo.channels           = 32;
 117                 engine->fifo.init               = nv10_fifo_init;
 118                 engine->fifo.takedown           = nv04_fifo_fini;
 119                 engine->fifo.disable            = nv04_fifo_disable;
 120                 engine->fifo.enable             = nv04_fifo_enable;
 121                 engine->fifo.reassign           = nv04_fifo_reassign;
 122                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 123                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 124                 engine->fifo.create_context     = nv10_fifo_create_context;
 125                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 126                 engine->fifo.load_context       = nv10_fifo_load_context;
 127                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 128                 engine->display.early_init      = nv04_display_early_init;
 129                 engine->display.late_takedown   = nv04_display_late_takedown;
 130                 engine->display.create          = nv04_display_create;
 131                 engine->display.destroy         = nv04_display_destroy;
 132                 engine->display.init            = nv04_display_init;
 133                 engine->display.fini            = nv04_display_fini;
 134                 engine->gpio.drive              = nv10_gpio_drive;
 135                 engine->gpio.sense              = nv10_gpio_sense;
 136                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 137                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 138                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 139                 if (dev_priv->chipset == 0x1a ||
 140                     dev_priv->chipset == 0x1f)
 141                         engine->vram.init       = nv1a_fb_vram_init;
 142                 else
 143                         engine->vram.init       = nv10_fb_vram_init;
 144                 engine->vram.takedown           = nouveau_stub_takedown;
 145                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 146                 break;
 147         case 0x20:
 148                 engine->instmem.init            = nv04_instmem_init;
 149                 engine->instmem.takedown        = nv04_instmem_takedown;
 150                 engine->instmem.suspend         = nv04_instmem_suspend;
 151                 engine->instmem.resume          = nv04_instmem_resume;
 152                 engine->instmem.get             = nv04_instmem_get;
 153                 engine->instmem.put             = nv04_instmem_put;
 154                 engine->instmem.map             = nv04_instmem_map;
 155                 engine->instmem.unmap           = nv04_instmem_unmap;
 156                 engine->instmem.flush           = nv04_instmem_flush;
 157                 engine->mc.init                 = nv04_mc_init;
 158                 engine->mc.takedown             = nv04_mc_takedown;
 159                 engine->timer.init              = nv04_timer_init;
 160                 engine->timer.read              = nv04_timer_read;
 161                 engine->timer.takedown          = nv04_timer_takedown;
 162                 engine->fb.init                 = nv20_fb_init;
 163                 engine->fb.takedown             = nv20_fb_takedown;
 164                 engine->fb.init_tile_region     = nv20_fb_init_tile_region;
 165                 engine->fb.set_tile_region      = nv20_fb_set_tile_region;
 166                 engine->fb.free_tile_region     = nv20_fb_free_tile_region;
 167                 engine->fifo.channels           = 32;
 168                 engine->fifo.init               = nv10_fifo_init;
 169                 engine->fifo.takedown           = nv04_fifo_fini;
 170                 engine->fifo.disable            = nv04_fifo_disable;
 171                 engine->fifo.enable             = nv04_fifo_enable;
 172                 engine->fifo.reassign           = nv04_fifo_reassign;
 173                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 174                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 175                 engine->fifo.create_context     = nv10_fifo_create_context;
 176                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 177                 engine->fifo.load_context       = nv10_fifo_load_context;
 178                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 179                 engine->display.early_init      = nv04_display_early_init;
 180                 engine->display.late_takedown   = nv04_display_late_takedown;
 181                 engine->display.create          = nv04_display_create;
 182                 engine->display.destroy         = nv04_display_destroy;
 183                 engine->display.init            = nv04_display_init;
 184                 engine->display.fini            = nv04_display_fini;
 185                 engine->gpio.drive              = nv10_gpio_drive;
 186                 engine->gpio.sense              = nv10_gpio_sense;
 187                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 188                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 189                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 190                 engine->vram.init               = nv20_fb_vram_init;
 191                 engine->vram.takedown           = nouveau_stub_takedown;
 192                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 193                 break;
 194         case 0x30:
 195                 engine->instmem.init            = nv04_instmem_init;
 196                 engine->instmem.takedown        = nv04_instmem_takedown;
 197                 engine->instmem.suspend         = nv04_instmem_suspend;
 198                 engine->instmem.resume          = nv04_instmem_resume;
 199                 engine->instmem.get             = nv04_instmem_get;
 200                 engine->instmem.put             = nv04_instmem_put;
 201                 engine->instmem.map             = nv04_instmem_map;
 202                 engine->instmem.unmap           = nv04_instmem_unmap;
 203                 engine->instmem.flush           = nv04_instmem_flush;
 204                 engine->mc.init                 = nv04_mc_init;
 205                 engine->mc.takedown             = nv04_mc_takedown;
 206                 engine->timer.init              = nv04_timer_init;
 207                 engine->timer.read              = nv04_timer_read;
 208                 engine->timer.takedown          = nv04_timer_takedown;
 209                 engine->fb.init                 = nv30_fb_init;
 210                 engine->fb.takedown             = nv30_fb_takedown;
 211                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 212                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 213                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 214                 engine->fifo.channels           = 32;
 215                 engine->fifo.init               = nv10_fifo_init;
 216                 engine->fifo.takedown           = nv04_fifo_fini;
 217                 engine->fifo.disable            = nv04_fifo_disable;
 218                 engine->fifo.enable             = nv04_fifo_enable;
 219                 engine->fifo.reassign           = nv04_fifo_reassign;
 220                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 221                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 222                 engine->fifo.create_context     = nv10_fifo_create_context;
 223                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 224                 engine->fifo.load_context       = nv10_fifo_load_context;
 225                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 226                 engine->display.early_init      = nv04_display_early_init;
 227                 engine->display.late_takedown   = nv04_display_late_takedown;
 228                 engine->display.create          = nv04_display_create;
 229                 engine->display.destroy         = nv04_display_destroy;
 230                 engine->display.init            = nv04_display_init;
 231                 engine->display.fini            = nv04_display_fini;
 232                 engine->gpio.drive              = nv10_gpio_drive;
 233                 engine->gpio.sense              = nv10_gpio_sense;
 234                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 235                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 236                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 237                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 238                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 239                 engine->vram.init               = nv20_fb_vram_init;
 240                 engine->vram.takedown           = nouveau_stub_takedown;
 241                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 242                 break;
 243         case 0x40:
 244         case 0x60:
 245                 engine->instmem.init            = nv04_instmem_init;
 246                 engine->instmem.takedown        = nv04_instmem_takedown;
 247                 engine->instmem.suspend         = nv04_instmem_suspend;
 248                 engine->instmem.resume          = nv04_instmem_resume;
 249                 engine->instmem.get             = nv04_instmem_get;
 250                 engine->instmem.put             = nv04_instmem_put;
 251                 engine->instmem.map             = nv04_instmem_map;
 252                 engine->instmem.unmap           = nv04_instmem_unmap;
 253                 engine->instmem.flush           = nv04_instmem_flush;
 254                 engine->mc.init                 = nv40_mc_init;
 255                 engine->mc.takedown             = nv40_mc_takedown;
 256                 engine->timer.init              = nv04_timer_init;
 257                 engine->timer.read              = nv04_timer_read;
 258                 engine->timer.takedown          = nv04_timer_takedown;
 259                 engine->fb.init                 = nv40_fb_init;
 260                 engine->fb.takedown             = nv40_fb_takedown;
 261                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 262                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 263                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 264                 engine->fifo.channels           = 32;
 265                 engine->fifo.init               = nv40_fifo_init;
 266                 engine->fifo.takedown           = nv04_fifo_fini;
 267                 engine->fifo.disable            = nv04_fifo_disable;
 268                 engine->fifo.enable             = nv04_fifo_enable;
 269                 engine->fifo.reassign           = nv04_fifo_reassign;
 270                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 271                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 272                 engine->fifo.create_context     = nv40_fifo_create_context;
 273                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 274                 engine->fifo.load_context       = nv40_fifo_load_context;
 275                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 276                 engine->display.early_init      = nv04_display_early_init;
 277                 engine->display.late_takedown   = nv04_display_late_takedown;
 278                 engine->display.create          = nv04_display_create;
 279                 engine->display.destroy         = nv04_display_destroy;
 280                 engine->display.init            = nv04_display_init;
 281                 engine->display.fini            = nv04_display_fini;
 282                 engine->gpio.init               = nv10_gpio_init;
 283                 engine->gpio.fini               = nv10_gpio_fini;
 284                 engine->gpio.drive              = nv10_gpio_drive;
 285                 engine->gpio.sense              = nv10_gpio_sense;
 286                 engine->gpio.irq_enable         = nv10_gpio_irq_enable;
 287                 engine->pm.clocks_get           = nv40_pm_clocks_get;
 288                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
 289                 engine->pm.clocks_set           = nv40_pm_clocks_set;
 290                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 291                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 292                 engine->pm.temp_get             = nv40_temp_get;
 293                 engine->pm.pwm_get              = nv40_pm_pwm_get;
 294                 engine->pm.pwm_set              = nv40_pm_pwm_set;
 295                 engine->vram.init               = nv40_fb_vram_init;
 296                 engine->vram.takedown           = nouveau_stub_takedown;
 297                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 298                 break;
 299         case 0x50:
 300         case 0x80: /* gotta love NVIDIA's consistency.. */
 301         case 0x90:
 302         case 0xa0:
 303                 engine->instmem.init            = nv50_instmem_init;
 304                 engine->instmem.takedown        = nv50_instmem_takedown;
 305                 engine->instmem.suspend         = nv50_instmem_suspend;
 306                 engine->instmem.resume          = nv50_instmem_resume;
 307                 engine->instmem.get             = nv50_instmem_get;
 308                 engine->instmem.put             = nv50_instmem_put;
 309                 engine->instmem.map             = nv50_instmem_map;
 310                 engine->instmem.unmap           = nv50_instmem_unmap;
 311                 if (dev_priv->chipset == 0x50)
 312                         engine->instmem.flush   = nv50_instmem_flush;
 313                 else
 314                         engine->instmem.flush   = nv84_instmem_flush;
 315                 engine->mc.init                 = nv50_mc_init;
 316                 engine->mc.takedown             = nv50_mc_takedown;
 317                 engine->timer.init              = nv04_timer_init;
 318                 engine->timer.read              = nv04_timer_read;
 319                 engine->timer.takedown          = nv04_timer_takedown;
 320                 engine->fb.init                 = nv50_fb_init;
 321                 engine->fb.takedown             = nv50_fb_takedown;
 322                 engine->fifo.channels           = 128;
 323                 engine->fifo.init               = nv50_fifo_init;
 324                 engine->fifo.takedown           = nv50_fifo_takedown;
 325                 engine->fifo.disable            = nv04_fifo_disable;
 326                 engine->fifo.enable             = nv04_fifo_enable;
 327                 engine->fifo.reassign           = nv04_fifo_reassign;
 328                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 329                 engine->fifo.create_context     = nv50_fifo_create_context;
 330                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 331                 engine->fifo.load_context       = nv50_fifo_load_context;
 332                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 333                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 334                 engine->display.early_init      = nv50_display_early_init;
 335                 engine->display.late_takedown   = nv50_display_late_takedown;
 336                 engine->display.create          = nv50_display_create;
 337                 engine->display.destroy         = nv50_display_destroy;
 338                 engine->display.init            = nv50_display_init;
 339                 engine->display.fini            = nv50_display_fini;
 340                 engine->gpio.init               = nv50_gpio_init;
 341                 engine->gpio.fini               = nv50_gpio_fini;
 342                 engine->gpio.drive              = nv50_gpio_drive;
 343                 engine->gpio.sense              = nv50_gpio_sense;
 344                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 345                 switch (dev_priv->chipset) {
 346                 case 0x84:
 347                 case 0x86:
 348                 case 0x92:
 349                 case 0x94:
 350                 case 0x96:
 351                 case 0x98:
 352                 case 0xa0:
 353                 case 0xaa:
 354                 case 0xac:
 355                 case 0x50:
 356                         engine->pm.clocks_get   = nv50_pm_clocks_get;
 357                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
 358                         engine->pm.clocks_set   = nv50_pm_clocks_set;
 359                         break;
 360                 default:
 361                         engine->pm.clocks_get   = nva3_pm_clocks_get;
 362                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
 363                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 364                         break;
 365                 }
 366                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 367                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 368                 if (dev_priv->chipset >= 0x84)
 369                         engine->pm.temp_get     = nv84_temp_get;
 370                 else
 371                         engine->pm.temp_get     = nv40_temp_get;
 372                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 373                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 374                 engine->vram.init               = nv50_vram_init;
 375                 engine->vram.takedown           = nv50_vram_fini;
 376                 engine->vram.get                = nv50_vram_new;
 377                 engine->vram.put                = nv50_vram_del;
 378                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 379                 break;
 380         case 0xc0:
 381                 engine->instmem.init            = nvc0_instmem_init;
 382                 engine->instmem.takedown        = nvc0_instmem_takedown;
 383                 engine->instmem.suspend         = nvc0_instmem_suspend;
 384                 engine->instmem.resume          = nvc0_instmem_resume;
 385                 engine->instmem.get             = nv50_instmem_get;
 386                 engine->instmem.put             = nv50_instmem_put;
 387                 engine->instmem.map             = nv50_instmem_map;
 388                 engine->instmem.unmap           = nv50_instmem_unmap;
 389                 engine->instmem.flush           = nv84_instmem_flush;
 390                 engine->mc.init                 = nv50_mc_init;
 391                 engine->mc.takedown             = nv50_mc_takedown;
 392                 engine->timer.init              = nv04_timer_init;
 393                 engine->timer.read              = nv04_timer_read;
 394                 engine->timer.takedown          = nv04_timer_takedown;
 395                 engine->fb.init                 = nvc0_fb_init;
 396                 engine->fb.takedown             = nvc0_fb_takedown;
 397                 engine->fifo.channels           = 128;
 398                 engine->fifo.init               = nvc0_fifo_init;
 399                 engine->fifo.takedown           = nvc0_fifo_takedown;
 400                 engine->fifo.disable            = nvc0_fifo_disable;
 401                 engine->fifo.enable             = nvc0_fifo_enable;
 402                 engine->fifo.reassign           = nvc0_fifo_reassign;
 403                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 404                 engine->fifo.create_context     = nvc0_fifo_create_context;
 405                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 406                 engine->fifo.load_context       = nvc0_fifo_load_context;
 407                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 408                 engine->display.early_init      = nv50_display_early_init;
 409                 engine->display.late_takedown   = nv50_display_late_takedown;
 410                 engine->display.create          = nv50_display_create;
 411                 engine->display.destroy         = nv50_display_destroy;
 412                 engine->display.init            = nv50_display_init;
 413                 engine->display.fini            = nv50_display_fini;
 414                 engine->gpio.init               = nv50_gpio_init;
 415                 engine->gpio.fini               = nv50_gpio_fini;
 416                 engine->gpio.drive              = nv50_gpio_drive;
 417                 engine->gpio.sense              = nv50_gpio_sense;
 418                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 419                 engine->vram.init               = nvc0_vram_init;
 420                 engine->vram.takedown           = nv50_vram_fini;
 421                 engine->vram.get                = nvc0_vram_new;
 422                 engine->vram.put                = nv50_vram_del;
 423                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 424                 engine->pm.temp_get             = nv84_temp_get;
 425                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 426                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 427                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 428                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 429                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 430                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 431                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 432                 break;
 433         case 0xd0:
 434                 engine->instmem.init            = nvc0_instmem_init;
 435                 engine->instmem.takedown        = nvc0_instmem_takedown;
 436                 engine->instmem.suspend         = nvc0_instmem_suspend;
 437                 engine->instmem.resume          = nvc0_instmem_resume;
 438                 engine->instmem.get             = nv50_instmem_get;
 439                 engine->instmem.put             = nv50_instmem_put;
 440                 engine->instmem.map             = nv50_instmem_map;
 441                 engine->instmem.unmap           = nv50_instmem_unmap;
 442                 engine->instmem.flush           = nv84_instmem_flush;
 443                 engine->mc.init                 = nv50_mc_init;
 444                 engine->mc.takedown             = nv50_mc_takedown;
 445                 engine->timer.init              = nv04_timer_init;
 446                 engine->timer.read              = nv04_timer_read;
 447                 engine->timer.takedown          = nv04_timer_takedown;
 448                 engine->fb.init                 = nvc0_fb_init;
 449                 engine->fb.takedown             = nvc0_fb_takedown;
 450                 engine->fifo.channels           = 128;
 451                 engine->fifo.init               = nvc0_fifo_init;
 452                 engine->fifo.takedown           = nvc0_fifo_takedown;
 453                 engine->fifo.disable            = nvc0_fifo_disable;
 454                 engine->fifo.enable             = nvc0_fifo_enable;
 455                 engine->fifo.reassign           = nvc0_fifo_reassign;
 456                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 457                 engine->fifo.create_context     = nvc0_fifo_create_context;
 458                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 459                 engine->fifo.load_context       = nvc0_fifo_load_context;
 460                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 461                 engine->display.early_init      = nouveau_stub_init;
 462                 engine->display.late_takedown   = nouveau_stub_takedown;
 463                 engine->display.create          = nvd0_display_create;
 464                 engine->display.destroy         = nvd0_display_destroy;
 465                 engine->display.init            = nvd0_display_init;
 466                 engine->display.fini            = nvd0_display_fini;
 467                 engine->gpio.init               = nv50_gpio_init;
 468                 engine->gpio.fini               = nv50_gpio_fini;
 469                 engine->gpio.drive              = nvd0_gpio_drive;
 470                 engine->gpio.sense              = nvd0_gpio_sense;
 471                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 472                 engine->vram.init               = nvc0_vram_init;
 473                 engine->vram.takedown           = nv50_vram_fini;
 474                 engine->vram.get                = nvc0_vram_new;
 475                 engine->vram.put                = nv50_vram_del;
 476                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 477                 engine->pm.temp_get             = nv84_temp_get;
 478                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 479                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 480                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 481                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 482                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 483                 break;
 484         case 0xe0:
 485                 engine->instmem.init            = nvc0_instmem_init;
 486                 engine->instmem.takedown        = nvc0_instmem_takedown;
 487                 engine->instmem.suspend         = nvc0_instmem_suspend;
 488                 engine->instmem.resume          = nvc0_instmem_resume;
 489                 engine->instmem.get             = nv50_instmem_get;
 490                 engine->instmem.put             = nv50_instmem_put;
 491                 engine->instmem.map             = nv50_instmem_map;
 492                 engine->instmem.unmap           = nv50_instmem_unmap;
 493                 engine->instmem.flush           = nv84_instmem_flush;
 494                 engine->mc.init                 = nv50_mc_init;
 495                 engine->mc.takedown             = nv50_mc_takedown;
 496                 engine->timer.init              = nv04_timer_init;
 497                 engine->timer.read              = nv04_timer_read;
 498                 engine->timer.takedown          = nv04_timer_takedown;
 499                 engine->fb.init                 = nvc0_fb_init;
 500                 engine->fb.takedown             = nvc0_fb_takedown;
 501                 engine->fifo.channels           = 4096;
 502                 engine->fifo.init               = nve0_fifo_init;
 503                 engine->fifo.takedown           = nve0_fifo_takedown;
 504                 engine->fifo.disable            = nvc0_fifo_disable;
 505                 engine->fifo.enable             = nvc0_fifo_enable;
 506                 engine->fifo.reassign           = nvc0_fifo_reassign;
 507                 engine->fifo.channel_id         = nve0_fifo_channel_id;
 508                 engine->fifo.create_context     = nve0_fifo_create_context;
 509                 engine->fifo.destroy_context    = nve0_fifo_destroy_context;
 510                 engine->fifo.load_context       = nvc0_fifo_load_context;
 511                 engine->fifo.unload_context     = nve0_fifo_unload_context;
 512                 engine->display.early_init      = nouveau_stub_init;
 513                 engine->display.late_takedown   = nouveau_stub_takedown;
 514                 engine->display.create          = nvd0_display_create;
 515                 engine->display.destroy         = nvd0_display_destroy;
 516                 engine->display.init            = nvd0_display_init;
 517                 engine->display.fini            = nvd0_display_fini;
 518                 engine->gpio.init               = nv50_gpio_init;
 519                 engine->gpio.fini               = nv50_gpio_fini;
 520                 engine->gpio.drive              = nvd0_gpio_drive;
 521                 engine->gpio.sense              = nvd0_gpio_sense;
 522                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 523                 engine->vram.init               = nvc0_vram_init;
 524                 engine->vram.takedown           = nv50_vram_fini;
 525                 engine->vram.get                = nvc0_vram_new;
 526                 engine->vram.put                = nv50_vram_del;
 527                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 528                 break;
 529         default:
 530                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 531                 return 1;
 532         }
 533
 534         /* headless mode */
 535         if (nouveau_modeset == 2) {
 536                 engine->display.early_init = nouveau_stub_init;
 537                 engine->display.late_takedown = nouveau_stub_takedown;
 538                 engine->display.create = nouveau_stub_init;
 539                 engine->display.init = nouveau_stub_init;
 540                 engine->display.destroy = nouveau_stub_takedown;
 541         }
 542
 543         return 0;
 544 }
 545
 546 static unsigned int
 547 nouveau_vga_set_decode(void *priv, bool state)
 548 {
 549         struct drm_device *dev = priv;
 550         struct drm_nouveau_private *dev_priv = dev->dev_private;
 551
 552         if (dev_priv->chipset >= 0x40)
 553                 nv_wr32(dev, 0x88054, state);
 554         else
 555                 nv_wr32(dev, 0x1854, state);
 556
 557         if (state)
 558                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 559                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 560         else
 561                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 562 }
 563
 564 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 565                                          enum vga_switcheroo_state state)
 566 {
 567         struct drm_device *dev = pci_get_drvdata(pdev);
 568         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 569         if (state == VGA_SWITCHEROO_ON) {
 570                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 571                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 572                 nouveau_pci_resume(pdev);
 573                 drm_kms_helper_poll_enable(dev);
 574                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 575         } else {
 576                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 577                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 578                 drm_kms_helper_poll_disable(dev);
 579                 nouveau_switcheroo_optimus_dsm();
 580                 nouveau_pci_suspend(pdev, pmm);
 581                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 582         }
 583 }
 584
 585 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 586 {
 587         struct drm_device *dev = pci_get_drvdata(pdev);
 588         nouveau_fbcon_output_poll_changed(dev);
 589 }
 590
 591 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 592 {
 593         struct drm_device *dev = pci_get_drvdata(pdev);
 594         bool can_switch;
 595
 596         spin_lock(&dev->count_lock);
 597         can_switch = (dev->open_count == 0);
 598         spin_unlock(&dev->count_lock);
 599         return can_switch;
 600 }
 601
 602 static void
 603 nouveau_card_channel_fini(struct drm_device *dev)
 604 {
 605         struct drm_nouveau_private *dev_priv = dev->dev_private;
 606
 607         if (dev_priv->channel)
 608                 nouveau_channel_put_unlocked(&dev_priv->channel);
 609 }
 610
 611 static int
 612 nouveau_card_channel_init(struct drm_device *dev)
 613 {
 614         struct drm_nouveau_private *dev_priv = dev->dev_private;
 615         struct nouveau_channel *chan;
 616         int ret, oclass;
 617
 618         ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT);
 619         dev_priv->channel = chan;
 620         if (ret)
 621                 return ret;
 622
 623         mutex_unlock(&dev_priv->channel->mutex);
 624
 625         if (dev_priv->card_type <= NV_50) {
 626                 if (dev_priv->card_type < NV_50)
 627                         oclass = 0x0039;
 628                 else
 629                         oclass = 0x5039;
 630
 631                 ret = nouveau_gpuobj_gr_new(chan, NvM2MF, oclass);
 632                 if (ret)
 633                         goto error;
 634
 635                 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
 636                                              &chan->m2mf_ntfy);
 637                 if (ret)
 638                         goto error;
 639
 640                 ret = RING_SPACE(chan, 6);
 641                 if (ret)
 642                         goto error;
 643
 644                 BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
 645                 OUT_RING  (chan, NvM2MF);
 646                 BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
 647                 OUT_RING  (chan, NvNotify0);
 648                 OUT_RING  (chan, chan->vram_handle);
 649                 OUT_RING  (chan, chan->gart_handle);
 650         } else
 651         if (dev_priv->card_type <= NV_D0) {
 652                 ret = nouveau_gpuobj_gr_new(chan, 0x9039, 0x9039);
 653                 if (ret)
 654                         goto error;
 655
 656                 ret = RING_SPACE(chan, 2);
 657                 if (ret)
 658                         goto error;
 659
 660                 BEGIN_NVC0(chan, NvSubM2MF, 0x0000, 1);
 661                 OUT_RING  (chan, 0x00009039);
 662         } else
 663         if (dev_priv->card_type <= NV_E0) {
 664                 /* not used, but created to get a graph context */
 665                 ret = nouveau_gpuobj_gr_new(chan, 0xa040, 0xa040);
 666                 if (ret)
 667                         goto error;
 668
 669                 /* bind strange copy engine to subchannel 4 (fixed...) */
 670                 ret = RING_SPACE(chan, 2);
 671                 if (ret)
 672                         goto error;
 673
 674                 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
 675                 OUT_RING  (chan, 0x0000a0b5);
 676         }
 677
 678         FIRE_RING (chan);
 679 error:
 680         if (ret)
 681                 nouveau_card_channel_fini(dev);
 682         return ret;
 683 }
 684
 685 static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = {
 686         .set_gpu_state = nouveau_switcheroo_set_state,
 687         .reprobe = nouveau_switcheroo_reprobe,
 688         .can_switch = nouveau_switcheroo_can_switch,
 689 };
 690
 691 int
 692 nouveau_card_init(struct drm_device *dev)
 693 {
 694         struct drm_nouveau_private *dev_priv = dev->dev_private;
 695         struct nouveau_engine *engine;
 696         int ret, e = 0;
 697
 698         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 699         vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
 700
 701         /* Initialise internal driver API hooks */
 702         ret = nouveau_init_engine_ptrs(dev);
 703         if (ret)
 704                 goto out;
 705         engine = &dev_priv->engine;
 706         spin_lock_init(&dev_priv->channels.lock);
 707         spin_lock_init(&dev_priv->tile.lock);
 708         spin_lock_init(&dev_priv->context_switch_lock);
 709         spin_lock_init(&dev_priv->vm_lock);
 710
 711         /* Make the CRTCs and I2C buses accessible */
 712         ret = engine->display.early_init(dev);
 713         if (ret)
 714                 goto out;
 715
 716         /* Parse BIOS tables / Run init tables if card not POSTed */
 717         ret = nouveau_bios_init(dev);
 718         if (ret)
 719                 goto out_display_early;
 720
 721         /* workaround an odd issue on nvc1 by disabling the device's
 722          * nosnoop capability.  hopefully won't cause issues until a
 723          * better fix is found - assuming there is one...
 724          */
 725         if (dev_priv->chipset == 0xc1) {
 726                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 727         }
 728
 729         /* PMC */
 730         ret = engine->mc.init(dev);
 731         if (ret)
 732                 goto out_bios;
 733
 734         /* PTIMER */
 735         ret = engine->timer.init(dev);
 736         if (ret)
 737                 goto out_mc;
 738
 739         /* PFB */
 740         ret = engine->fb.init(dev);
 741         if (ret)
 742                 goto out_timer;
 743
 744         ret = engine->vram.init(dev);
 745         if (ret)
 746                 goto out_fb;
 747
 748         /* PGPIO */
 749         ret = nouveau_gpio_create(dev);
 750         if (ret)
 751                 goto out_vram;
 752
 753         ret = nouveau_gpuobj_init(dev);
 754         if (ret)
 755                 goto out_gpio;
 756
 757         ret = engine->instmem.init(dev);
 758         if (ret)
 759                 goto out_gpuobj;
 760
 761         ret = nouveau_mem_vram_init(dev);
 762         if (ret)
 763                 goto out_instmem;
 764
 765         ret = nouveau_mem_gart_init(dev);
 766         if (ret)
 767                 goto out_ttmvram;
 768
 769         if (!dev_priv->noaccel) {
 770                 switch (dev_priv->card_type) {
 771                 case NV_04:
 772                         nv04_fence_create(dev);
 773                         break;
 774                 case NV_10:
 775                 case NV_20:
 776                 case NV_30:
 777                 case NV_40:
 778                 case NV_50:
 779                         if (dev_priv->chipset < 0x84)
 780                                 nv10_fence_create(dev);
 781                         else
 782                                 nv84_fence_create(dev);
 783                         break;
 784                 case NV_C0:
 785                 case NV_D0:
 786                 case NV_E0:
 787                         nvc0_fence_create(dev);
 788                         break;
 789                 default:
 790                         break;
 791                 }
 792
 793                 switch (dev_priv->card_type) {
 794                 case NV_04:
 795                 case NV_10:
 796                 case NV_20:
 797                 case NV_30:
 798                 case NV_40:
 799                         nv04_software_create(dev);
 800                         break;
 801                 case NV_50:
 802                         nv50_software_create(dev);
 803                         break;
 804                 case NV_C0:
 805                 case NV_D0:
 806                 case NV_E0:
 807                         nvc0_software_create(dev);
 808                         break;
 809                 default:
 810                         break;
 811                 }
 812
 813                 switch (dev_priv->card_type) {
 814                 case NV_04:
 815                         nv04_graph_create(dev);
 816                         break;
 817                 case NV_10:
 818                         nv10_graph_create(dev);
 819                         break;
 820                 case NV_20:
 821                 case NV_30:
 822                         nv20_graph_create(dev);
 823                         break;
 824                 case NV_40:
 825                         nv40_graph_create(dev);
 826                         break;
 827                 case NV_50:
 828                         nv50_graph_create(dev);
 829                         break;
 830                 case NV_C0:
 831                 case NV_D0:
 832                         nvc0_graph_create(dev);
 833                         break;
 834                 case NV_E0:
 835                         nve0_graph_create(dev);
 836                         break;
 837                 default:
 838                         break;
 839                 }
 840
 841                 switch (dev_priv->chipset) {
 842                 case 0x84:
 843                 case 0x86:
 844                 case 0x92:
 845                 case 0x94:
 846                 case 0x96:
 847                 case 0xa0:
 848                         nv84_crypt_create(dev);
 849                         break;
 850                 case 0x98:
 851                 case 0xaa:
 852                 case 0xac:
 853                         nv98_crypt_create(dev);
 854                         break;
 855                 }
 856
 857                 switch (dev_priv->card_type) {
 858                 case NV_50:
 859                         switch (dev_priv->chipset) {
 860                         case 0xa3:
 861                         case 0xa5:
 862                         case 0xa8:
 863                         case 0xaf:
 864                                 nva3_copy_create(dev);
 865                                 break;
 866                         }
 867                         break;
 868                 case NV_C0:
 869                         nvc0_copy_create(dev, 0);
 870                         nvc0_copy_create(dev, 1);
 871                         break;
 872                 default:
 873                         break;
 874                 }
 875
 876                 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
 877                         nv84_bsp_create(dev);
 878                         nv84_vp_create(dev);
 879                         nv98_ppp_create(dev);
 880                 } else
 881                 if (dev_priv->chipset >= 0x84) {
 882                         nv50_mpeg_create(dev);
 883                         nv84_bsp_create(dev);
 884                         nv84_vp_create(dev);
 885                 } else
 886                 if (dev_priv->chipset >= 0x50) {
 887                         nv50_mpeg_create(dev);
 888                 } else
 889                 if (dev_priv->card_type == NV_40 ||
 890                     dev_priv->chipset == 0x31 ||
 891                     dev_priv->chipset == 0x34 ||
 892                     dev_priv->chipset == 0x36) {
 893                         nv31_mpeg_create(dev);
 894                 }
 895
 896                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 897                         if (dev_priv->eng[e]) {
 898                                 ret = dev_priv->eng[e]->init(dev, e);
 899                                 if (ret)
 900                                         goto out_engine;
 901                         }
 902                 }
 903
 904                 /* PFIFO */
 905                 ret = engine->fifo.init(dev);
 906                 if (ret)
 907                         goto out_engine;
 908         }
 909
 910         ret = nouveau_irq_init(dev);
 911         if (ret)
 912                 goto out_fifo;
 913
 914         ret = nouveau_display_create(dev);
 915         if (ret)
 916                 goto out_irq;
 917
 918         nouveau_backlight_init(dev);
 919         nouveau_pm_init(dev);
 920
 921         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 922                 ret = nouveau_card_channel_init(dev);
 923                 if (ret)
 924                         goto out_pm;
 925         }
 926
 927         if (dev->mode_config.num_crtc) {
 928                 ret = nouveau_display_init(dev);
 929                 if (ret)
 930                         goto out_chan;
 931
 932                 nouveau_fbcon_init(dev);
 933         }
 934
 935         return 0;
 936
 937 out_chan:
 938         nouveau_card_channel_fini(dev);
 939 out_pm:
 940         nouveau_pm_fini(dev);
 941         nouveau_backlight_exit(dev);
 942         nouveau_display_destroy(dev);
 943 out_irq:
 944         nouveau_irq_fini(dev);
 945 out_fifo:
 946         if (!dev_priv->noaccel)
 947                 engine->fifo.takedown(dev);
 948 out_engine:
 949         if (!dev_priv->noaccel) {
 950                 for (e = e - 1; e >= 0; e--) {
 951                         if (!dev_priv->eng[e])
 952                                 continue;
 953                         dev_priv->eng[e]->fini(dev, e, false);
 954                         dev_priv->eng[e]->destroy(dev,e );
 955                 }
 956         }
 957         nouveau_mem_gart_fini(dev);
 958 out_ttmvram:
 959         nouveau_mem_vram_fini(dev);
 960 out_instmem:
 961         engine->instmem.takedown(dev);
 962 out_gpuobj:
 963         nouveau_gpuobj_takedown(dev);
 964 out_gpio:
 965         nouveau_gpio_destroy(dev);
 966 out_vram:
 967         engine->vram.takedown(dev);
 968 out_fb:
 969         engine->fb.takedown(dev);
 970 out_timer:
 971         engine->timer.takedown(dev);
 972 out_mc:
 973         engine->mc.takedown(dev);
 974 out_bios:
 975         nouveau_bios_takedown(dev);
 976 out_display_early:
 977         engine->display.late_takedown(dev);
 978 out:
 979         vga_client_register(dev->pdev, NULL, NULL, NULL);
 980         return ret;
 981 }
 982
 983 static void nouveau_card_takedown(struct drm_device *dev)
 984 {
 985         struct drm_nouveau_private *dev_priv = dev->dev_private;
 986         struct nouveau_engine *engine = &dev_priv->engine;
 987         int e;
 988
 989         if (dev->mode_config.num_crtc) {
 990                 nouveau_fbcon_fini(dev);
 991                 nouveau_display_fini(dev);
 992         }
 993
 994         nouveau_card_channel_fini(dev);
 995         nouveau_pm_fini(dev);
 996         nouveau_backlight_exit(dev);
 997         nouveau_display_destroy(dev);
 998
 999         if (!dev_priv->noaccel) {
1000                 engine->fifo.takedown(dev);
1001                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
1002                         if (dev_priv->eng[e]) {
1003                                 dev_priv->eng[e]->fini(dev, e, false);
1004                                 dev_priv->eng[e]->destroy(dev,e );
1005                         }
1006                 }
1007         }
1008
1009         if (dev_priv->vga_ram) {
1010                 nouveau_bo_unpin(dev_priv->vga_ram);
1011                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
1012         }
1013
1014         mutex_lock(&dev->struct_mutex);
1015         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
1016         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
1017         mutex_unlock(&dev->struct_mutex);
1018         nouveau_mem_gart_fini(dev);
1019         nouveau_mem_vram_fini(dev);
1020
1021         engine->instmem.takedown(dev);
1022         nouveau_gpuobj_takedown(dev);
1023
1024         nouveau_gpio_destroy(dev);
1025         engine->vram.takedown(dev);
1026         engine->fb.takedown(dev);
1027         engine->timer.takedown(dev);
1028         engine->mc.takedown(dev);
1029
1030         nouveau_bios_takedown(dev);
1031         engine->display.late_takedown(dev);
1032
1033         nouveau_irq_fini(dev);
1034
1035         vga_client_register(dev->pdev, NULL, NULL, NULL);
1036 }
1037
1038 int
1039 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
1040 {
1041         struct drm_nouveau_private *dev_priv = dev->dev_private;
1042         struct nouveau_fpriv *fpriv;
1043         int ret;
1044
1045         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1046         if (unlikely(!fpriv))
1047                 return -ENOMEM;
1048
1049         spin_lock_init(&fpriv->lock);
1050         INIT_LIST_HEAD(&fpriv->channels);
1051
1052         if (dev_priv->card_type == NV_50) {
1053                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
1054                                      &fpriv->vm);
1055                 if (ret) {
1056                         kfree(fpriv);
1057                         return ret;
1058                 }
1059         } else
1060         if (dev_priv->card_type >= NV_C0) {
1061                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
1062                                      &fpriv->vm);
1063                 if (ret) {
1064                         kfree(fpriv);
1065                         return ret;
1066                 }
1067         }
1068
1069         file_priv->driver_priv = fpriv;
1070         return 0;
1071 }
1072
1073 /* here a client dies, release the stuff that was allocated for its
1074  * file_priv */
1075 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
1076 {
1077         nouveau_channel_cleanup(dev, file_priv);
1078 }
1079
1080 void
1081 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
1082 {
1083         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
1084         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
1085         kfree(fpriv);
1086 }
1087
1088 /* first module load, setup the mmio/fb mapping */
1089 /* KMS: we need mmio at load time, not when the first drm client opens. */
1090 int nouveau_firstopen(struct drm_device *dev)
1091 {
1092         return 0;
1093 }
1094
1095 /* if we have an OF card, copy vbios to RAMIN */
1096 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
1097 {
1098 #if defined(__powerpc__)
1099         int size, i;
1100         const uint32_t *bios;
1101         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
1102         if (!dn) {
1103                 NV_INFO(dev, "Unable to get the OF node\n");
1104                 return;
1105         }
1106
1107         bios = of_get_property(dn, "NVDA,BMP", &size);
1108         if (bios) {
1109                 for (i = 0; i < size; i += 4)
1110                         nv_wi32(dev, i, bios[i/4]);
1111                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
1112         } else {
1113                 NV_INFO(dev, "Unable to get the OF bios\n");
1114         }
1115 #endif
1116 }
1117
1118 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
1119 {
1120         struct pci_dev *pdev = dev->pdev;
1121         struct apertures_struct *aper = alloc_apertures(3);
1122         if (!aper)
1123                 return NULL;
1124
1125         aper->ranges[0].base = pci_resource_start(pdev, 1);
1126         aper->ranges[0].size = pci_resource_len(pdev, 1);
1127         aper->count = 1;
1128
1129         if (pci_resource_len(pdev, 2)) {
1130                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
1131                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
1132                 aper->count++;
1133         }
1134
1135         if (pci_resource_len(pdev, 3)) {
1136                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
1137                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
1138                 aper->count++;
1139         }
1140
1141         return aper;
1142 }
1143
1144 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
1145 {
1146         struct drm_nouveau_private *dev_priv = dev->dev_private;
1147         bool primary = false;
1148         dev_priv->apertures = nouveau_get_apertures(dev);
1149         if (!dev_priv->apertures)
1150                 return -ENOMEM;
1151
1152 #ifdef CONFIG_X86
1153         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1154 #endif
1155
1156         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
1157         return 0;
1158 }
1159
1160 int nouveau_load(struct drm_device *dev, unsigned long flags)
1161 {
1162         struct drm_nouveau_private *dev_priv;
1163         unsigned long long offset, length;
1164         uint32_t reg0 = ~0, strap;
1165         int ret;
1166
1167         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1168         if (!dev_priv) {
1169                 ret = -ENOMEM;
1170                 goto err_out;
1171         }
1172         dev->dev_private = dev_priv;
1173         dev_priv->dev = dev;
1174
1175         pci_set_master(dev->pdev);
1176
1177         dev_priv->flags = flags & NOUVEAU_FLAGS;
1178
1179         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1180                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1181
1182         /* first up, map the start of mmio and determine the chipset */
1183         dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
1184         if (dev_priv->mmio) {
1185 #ifdef __BIG_ENDIAN
1186                 /* put the card into big-endian mode if it's not */
1187                 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1188                         nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1189                 DRM_MEMORYBARRIER();
1190 #endif
1191
1192                 /* determine chipset and derive architecture from it */
1193                 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1194                 if ((reg0 & 0x0f000000) > 0) {
1195                         dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1196                         switch (dev_priv->chipset & 0xf0) {
1197                         case 0x10:
1198                         case 0x20:
1199                         case 0x30:
1200                                 dev_priv->card_type = dev_priv->chipset & 0xf0;
1201                                 break;
1202                         case 0x40:
1203                         case 0x60:
1204                                 dev_priv->card_type = NV_40;
1205                                 break;
1206                         case 0x50:
1207                         case 0x80:
1208                         case 0x90:
1209                         case 0xa0:
1210                                 dev_priv->card_type = NV_50;
1211                                 break;
1212                         case 0xc0:
1213                                 dev_priv->card_type = NV_C0;
1214                                 break;
1215                         case 0xd0:
1216                                 dev_priv->card_type = NV_D0;
1217                                 break;
1218                         case 0xe0:
1219                                 dev_priv->card_type = NV_E0;
1220                                 break;
1221                         default:
1222                                 break;
1223                         }
1224                 } else
1225                 if ((reg0 & 0xff00fff0) == 0x20004000) {
1226                         if (reg0 & 0x00f00000)
1227                                 dev_priv->chipset = 0x05;
1228                         else
1229                                 dev_priv->chipset = 0x04;
1230                         dev_priv->card_type = NV_04;
1231                 }
1232
1233                 iounmap(dev_priv->mmio);
1234         }
1235
1236         if (!dev_priv->card_type) {
1237                 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1238                 ret = -EINVAL;
1239                 goto err_priv;
1240         }
1241
1242         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1243                      dev_priv->card_type, reg0);
1244
1245         /* map the mmio regs, limiting the amount to preserve vmap space */
1246         offset = pci_resource_start(dev->pdev, 0);
1247         length = pci_resource_len(dev->pdev, 0);
1248         if (dev_priv->card_type < NV_E0)
1249                 length = min(length, (unsigned long long)0x00800000);
1250
1251         dev_priv->mmio = ioremap(offset, length);
1252         if (!dev_priv->mmio) {
1253                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1254                          "Please report your setup to " DRIVER_EMAIL "\n");
1255                 ret = -EINVAL;
1256                 goto err_priv;
1257         }
1258         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", offset);
1259
1260         /* determine frequency of timing crystal */
1261         strap = nv_rd32(dev, 0x101000);
1262         if ( dev_priv->chipset < 0x17 ||
1263             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1264                 strap &= 0x00000040;
1265         else
1266                 strap &= 0x00400040;
1267
1268         switch (strap) {
1269         case 0x00000000: dev_priv->crystal = 13500; break;
1270         case 0x00000040: dev_priv->crystal = 14318; break;
1271         case 0x00400000: dev_priv->crystal = 27000; break;
1272         case 0x00400040: dev_priv->crystal = 25000; break;
1273         }
1274
1275         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1276
1277         /* Determine whether we'll attempt acceleration or not, some
1278          * cards are disabled by default here due to them being known
1279          * non-functional, or never been tested due to lack of hw.
1280          */
1281         dev_priv->noaccel = !!nouveau_noaccel;
1282         if (nouveau_noaccel == -1) {
1283                 switch (dev_priv->chipset) {
1284                 case 0xd9: /* known broken */
1285                 case 0xe4: /* needs binary driver firmware */
1286                 case 0xe7: /* needs binary driver firmware */
1287                         NV_INFO(dev, "acceleration disabled by default, pass "
1288                                      "noaccel=0 to force enable\n");
1289                         dev_priv->noaccel = true;
1290                         break;
1291                 default:
1292                         dev_priv->noaccel = false;
1293                         break;
1294                 }
1295         }
1296
1297         ret = nouveau_remove_conflicting_drivers(dev);
1298         if (ret)
1299                 goto err_mmio;
1300
1301         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1302         if (dev_priv->card_type >= NV_40) {
1303                 int ramin_bar = 2;
1304                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1305                         ramin_bar = 3;
1306
1307                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1308                 dev_priv->ramin =
1309                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1310                                 dev_priv->ramin_size);
1311                 if (!dev_priv->ramin) {
1312                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1313                         ret = -ENOMEM;
1314                         goto err_mmio;
1315                 }
1316         } else {
1317                 dev_priv->ramin_size = 1 * 1024 * 1024;
1318                 dev_priv->ramin = ioremap(offset + NV_RAMIN,
1319                                           dev_priv->ramin_size);
1320                 if (!dev_priv->ramin) {
1321                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1322                         ret = -ENOMEM;
1323                         goto err_mmio;
1324                 }
1325         }
1326
1327         nouveau_OF_copy_vbios_to_ramin(dev);
1328
1329         /* Special flags */
1330         if (dev->pci_device == 0x01a0)
1331                 dev_priv->flags |= NV_NFORCE;
1332         else if (dev->pci_device == 0x01f0)
1333                 dev_priv->flags |= NV_NFORCE2;
1334
1335         /* For kernel modesetting, init card now and bring up fbcon */
1336         ret = nouveau_card_init(dev);
1337         if (ret)
1338                 goto err_ramin;
1339
1340         return 0;
1341
1342 err_ramin:
1343         iounmap(dev_priv->ramin);
1344 err_mmio:
1345         iounmap(dev_priv->mmio);
1346 err_priv:
1347         kfree(dev_priv);
1348         dev->dev_private = NULL;
1349 err_out:
1350         return ret;
1351 }
1352
1353 void nouveau_lastclose(struct drm_device *dev)
1354 {
1355         vga_switcheroo_process_delayed_switch();
1356 }
1357
1358 int nouveau_unload(struct drm_device *dev)
1359 {
1360         struct drm_nouveau_private *dev_priv = dev->dev_private;
1361
1362         nouveau_card_takedown(dev);
1363
1364         iounmap(dev_priv->mmio);
1365         iounmap(dev_priv->ramin);
1366
1367         kfree(dev_priv);
1368         dev->dev_private = NULL;
1369         return 0;
1370 }
1371
1372 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1373                                                 struct drm_file *file_priv)
1374 {
1375         struct drm_nouveau_private *dev_priv = dev->dev_private;
1376         struct drm_nouveau_getparam *getparam = data;
1377
1378         switch (getparam->param) {
1379         case NOUVEAU_GETPARAM_CHIPSET_ID:
1380                 getparam->value = dev_priv->chipset;
1381                 break;
1382         case NOUVEAU_GETPARAM_PCI_VENDOR:
1383                 getparam->value = dev->pci_vendor;
1384                 break;
1385         case NOUVEAU_GETPARAM_PCI_DEVICE:
1386                 getparam->value = dev->pci_device;
1387                 break;
1388         case NOUVEAU_GETPARAM_BUS_TYPE:
1389                 if (drm_pci_device_is_agp(dev))
1390                         getparam->value = NV_AGP;
1391                 else if (pci_is_pcie(dev->pdev))
1392                         getparam->value = NV_PCIE;
1393                 else
1394                         getparam->value = NV_PCI;
1395                 break;
1396         case NOUVEAU_GETPARAM_FB_SIZE:
1397                 getparam->value = dev_priv->fb_available_size;
1398                 break;
1399         case NOUVEAU_GETPARAM_AGP_SIZE:
1400                 getparam->value = dev_priv->gart_info.aper_size;
1401                 break;
1402         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1403                 getparam->value = 0; /* deprecated */
1404                 break;
1405         case NOUVEAU_GETPARAM_PTIMER_TIME:
1406                 getparam->value = dev_priv->engine.timer.read(dev);
1407                 break;
1408         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1409                 getparam->value = 1;
1410                 break;
1411         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1412                 getparam->value = 1;
1413                 break;
1414         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1415                 /* NV40 and NV50 versions are quite different, but register
1416                  * address is the same. User is supposed to know the card
1417                  * family anyway... */
1418                 if (dev_priv->chipset >= 0x40) {
1419                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1420                         break;
1421                 }
1422                 /* FALLTHRU */
1423         default:
1424                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1425                 return -EINVAL;
1426         }
1427
1428         return 0;
1429 }
1430
1431 int
1432 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1433                        struct drm_file *file_priv)
1434 {
1435         struct drm_nouveau_setparam *setparam = data;
1436
1437         switch (setparam->param) {
1438         default:
1439                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1440                 return -EINVAL;
1441         }
1442
1443         return 0;
1444 }
1445
1446 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1447 bool
1448 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1449                 uint32_t reg, uint32_t mask, uint32_t val)
1450 {
1451         struct drm_nouveau_private *dev_priv = dev->dev_private;
1452         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1453         uint64_t start = ptimer->read(dev);
1454
1455         do {
1456                 if ((nv_rd32(dev, reg) & mask) == val)
1457                         return true;
1458         } while (ptimer->read(dev) - start < timeout);
1459
1460         return false;
1461 }
1462
1463 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1464 bool
1465 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1466                 uint32_t reg, uint32_t mask, uint32_t val)
1467 {
1468         struct drm_nouveau_private *dev_priv = dev->dev_private;
1469         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1470         uint64_t start = ptimer->read(dev);
1471
1472         do {
1473                 if ((nv_rd32(dev, reg) & mask) != val)
1474                         return true;
1475         } while (ptimer->read(dev) - start < timeout);
1476
1477         return false;
1478 }
1479
1480 /* Wait until cond(data) == true, up until timeout has hit */
1481 bool
1482 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1483                 bool (*cond)(void *), void *data)
1484 {
1485         struct drm_nouveau_private *dev_priv = dev->dev_private;
1486         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1487         u64 start = ptimer->read(dev);
1488
1489         do {
1490                 if (cond(data) == true)
1491                         return true;
1492         } while (ptimer->read(dev) - start < timeout);
1493
1494         return false;
1495 }
1496
1497 /* Waits for PGRAPH to go completely idle */
1498 bool nouveau_wait_for_idle(struct drm_device *dev)
1499 {
1500         struct drm_nouveau_private *dev_priv = dev->dev_private;
1501         uint32_t mask = ~0;
1502
1503         if (dev_priv->card_type == NV_40)
1504                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1505
1506         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1507                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1508                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1509                 return false;
1510         }
1511
1512         return true;
1513 }
1514