drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nv50_display.h"
  39
  40 static void nouveau_stub_takedown(struct drm_device *dev) {}
  41
  42 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  43 {
  44         struct drm_nouveau_private *dev_priv = dev->dev_private;
  45         struct nouveau_engine *engine = &dev_priv->engine;
  46
  47         switch (dev_priv->chipset & 0xf0) {
  48         case 0x00:
  49                 engine->instmem.init            = nv04_instmem_init;
  50                 engine->instmem.takedown        = nv04_instmem_takedown;
  51                 engine->instmem.suspend         = nv04_instmem_suspend;
  52                 engine->instmem.resume          = nv04_instmem_resume;
  53                 engine->instmem.populate        = nv04_instmem_populate;
  54                 engine->instmem.clear           = nv04_instmem_clear;
  55                 engine->instmem.bind            = nv04_instmem_bind;
  56                 engine->instmem.unbind          = nv04_instmem_unbind;
  57                 engine->instmem.flush           = nv04_instmem_flush;
  58                 engine->mc.init                 = nv04_mc_init;
  59                 engine->mc.takedown             = nv04_mc_takedown;
  60                 engine->timer.init              = nv04_timer_init;
  61                 engine->timer.read              = nv04_timer_read;
  62                 engine->timer.takedown          = nv04_timer_takedown;
  63                 engine->fb.init                 = nv04_fb_init;
  64                 engine->fb.takedown             = nv04_fb_takedown;
  65                 engine->graph.grclass           = nv04_graph_grclass;
  66                 engine->graph.init              = nv04_graph_init;
  67                 engine->graph.takedown          = nv04_graph_takedown;
  68                 engine->graph.fifo_access       = nv04_graph_fifo_access;
  69                 engine->graph.channel           = nv04_graph_channel;
  70                 engine->graph.create_context    = nv04_graph_create_context;
  71                 engine->graph.destroy_context   = nv04_graph_destroy_context;
  72                 engine->graph.load_context      = nv04_graph_load_context;
  73                 engine->graph.unload_context    = nv04_graph_unload_context;
  74                 engine->fifo.channels           = 16;
  75                 engine->fifo.init               = nv04_fifo_init;
  76                 engine->fifo.takedown           = nouveau_stub_takedown;
  77                 engine->fifo.disable            = nv04_fifo_disable;
  78                 engine->fifo.enable             = nv04_fifo_enable;
  79                 engine->fifo.reassign           = nv04_fifo_reassign;
  80                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
  81                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  82                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  83                 engine->fifo.create_context     = nv04_fifo_create_context;
  84                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  85                 engine->fifo.load_context       = nv04_fifo_load_context;
  86                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  87                 break;
  88         case 0x10:
  89                 engine->instmem.init            = nv04_instmem_init;
  90                 engine->instmem.takedown        = nv04_instmem_takedown;
  91                 engine->instmem.suspend         = nv04_instmem_suspend;
  92                 engine->instmem.resume          = nv04_instmem_resume;
  93                 engine->instmem.populate        = nv04_instmem_populate;
  94                 engine->instmem.clear           = nv04_instmem_clear;
  95                 engine->instmem.bind            = nv04_instmem_bind;
  96                 engine->instmem.unbind          = nv04_instmem_unbind;
  97                 engine->instmem.flush           = nv04_instmem_flush;
  98                 engine->mc.init                 = nv04_mc_init;
  99                 engine->mc.takedown             = nv04_mc_takedown;
 100                 engine->timer.init              = nv04_timer_init;
 101                 engine->timer.read              = nv04_timer_read;
 102                 engine->timer.takedown          = nv04_timer_takedown;
 103                 engine->fb.init                 = nv10_fb_init;
 104                 engine->fb.takedown             = nv10_fb_takedown;
 105                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 106                 engine->graph.grclass           = nv10_graph_grclass;
 107                 engine->graph.init              = nv10_graph_init;
 108                 engine->graph.takedown          = nv10_graph_takedown;
 109                 engine->graph.channel           = nv10_graph_channel;
 110                 engine->graph.create_context    = nv10_graph_create_context;
 111                 engine->graph.destroy_context   = nv10_graph_destroy_context;
 112                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 113                 engine->graph.load_context      = nv10_graph_load_context;
 114                 engine->graph.unload_context    = nv10_graph_unload_context;
 115                 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
 116                 engine->fifo.channels           = 32;
 117                 engine->fifo.init               = nv10_fifo_init;
 118                 engine->fifo.takedown           = nouveau_stub_takedown;
 119                 engine->fifo.disable            = nv04_fifo_disable;
 120                 engine->fifo.enable             = nv04_fifo_enable;
 121                 engine->fifo.reassign           = nv04_fifo_reassign;
 122                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 123                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 124                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 125                 engine->fifo.create_context     = nv10_fifo_create_context;
 126                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 127                 engine->fifo.load_context       = nv10_fifo_load_context;
 128                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 129                 break;
 130         case 0x20:
 131                 engine->instmem.init            = nv04_instmem_init;
 132                 engine->instmem.takedown        = nv04_instmem_takedown;
 133                 engine->instmem.suspend         = nv04_instmem_suspend;
 134                 engine->instmem.resume          = nv04_instmem_resume;
 135                 engine->instmem.populate        = nv04_instmem_populate;
 136                 engine->instmem.clear           = nv04_instmem_clear;
 137                 engine->instmem.bind            = nv04_instmem_bind;
 138                 engine->instmem.unbind          = nv04_instmem_unbind;
 139                 engine->instmem.flush           = nv04_instmem_flush;
 140                 engine->mc.init                 = nv04_mc_init;
 141                 engine->mc.takedown             = nv04_mc_takedown;
 142                 engine->timer.init              = nv04_timer_init;
 143                 engine->timer.read              = nv04_timer_read;
 144                 engine->timer.takedown          = nv04_timer_takedown;
 145                 engine->fb.init                 = nv10_fb_init;
 146                 engine->fb.takedown             = nv10_fb_takedown;
 147                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 148                 engine->graph.grclass           = nv20_graph_grclass;
 149                 engine->graph.init              = nv20_graph_init;
 150                 engine->graph.takedown          = nv20_graph_takedown;
 151                 engine->graph.channel           = nv10_graph_channel;
 152                 engine->graph.create_context    = nv20_graph_create_context;
 153                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 154                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 155                 engine->graph.load_context      = nv20_graph_load_context;
 156                 engine->graph.unload_context    = nv20_graph_unload_context;
 157                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 158                 engine->fifo.channels           = 32;
 159                 engine->fifo.init               = nv10_fifo_init;
 160                 engine->fifo.takedown           = nouveau_stub_takedown;
 161                 engine->fifo.disable            = nv04_fifo_disable;
 162                 engine->fifo.enable             = nv04_fifo_enable;
 163                 engine->fifo.reassign           = nv04_fifo_reassign;
 164                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 165                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 166                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 167                 engine->fifo.create_context     = nv10_fifo_create_context;
 168                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 169                 engine->fifo.load_context       = nv10_fifo_load_context;
 170                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 171                 break;
 172         case 0x30:
 173                 engine->instmem.init            = nv04_instmem_init;
 174                 engine->instmem.takedown        = nv04_instmem_takedown;
 175                 engine->instmem.suspend         = nv04_instmem_suspend;
 176                 engine->instmem.resume          = nv04_instmem_resume;
 177                 engine->instmem.populate        = nv04_instmem_populate;
 178                 engine->instmem.clear           = nv04_instmem_clear;
 179                 engine->instmem.bind            = nv04_instmem_bind;
 180                 engine->instmem.unbind          = nv04_instmem_unbind;
 181                 engine->instmem.flush           = nv04_instmem_flush;
 182                 engine->mc.init                 = nv04_mc_init;
 183                 engine->mc.takedown             = nv04_mc_takedown;
 184                 engine->timer.init              = nv04_timer_init;
 185                 engine->timer.read              = nv04_timer_read;
 186                 engine->timer.takedown          = nv04_timer_takedown;
 187                 engine->fb.init                 = nv10_fb_init;
 188                 engine->fb.takedown             = nv10_fb_takedown;
 189                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 190                 engine->graph.grclass           = nv30_graph_grclass;
 191                 engine->graph.init              = nv30_graph_init;
 192                 engine->graph.takedown          = nv20_graph_takedown;
 193                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 194                 engine->graph.channel           = nv10_graph_channel;
 195                 engine->graph.create_context    = nv20_graph_create_context;
 196                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 197                 engine->graph.load_context      = nv20_graph_load_context;
 198                 engine->graph.unload_context    = nv20_graph_unload_context;
 199                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 200                 engine->fifo.channels           = 32;
 201                 engine->fifo.init               = nv10_fifo_init;
 202                 engine->fifo.takedown           = nouveau_stub_takedown;
 203                 engine->fifo.disable            = nv04_fifo_disable;
 204                 engine->fifo.enable             = nv04_fifo_enable;
 205                 engine->fifo.reassign           = nv04_fifo_reassign;
 206                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 207                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 208                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 209                 engine->fifo.create_context     = nv10_fifo_create_context;
 210                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 211                 engine->fifo.load_context       = nv10_fifo_load_context;
 212                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 213                 break;
 214         case 0x40:
 215         case 0x60:
 216                 engine->instmem.init            = nv04_instmem_init;
 217                 engine->instmem.takedown        = nv04_instmem_takedown;
 218                 engine->instmem.suspend         = nv04_instmem_suspend;
 219                 engine->instmem.resume          = nv04_instmem_resume;
 220                 engine->instmem.populate        = nv04_instmem_populate;
 221                 engine->instmem.clear           = nv04_instmem_clear;
 222                 engine->instmem.bind            = nv04_instmem_bind;
 223                 engine->instmem.unbind          = nv04_instmem_unbind;
 224                 engine->instmem.flush           = nv04_instmem_flush;
 225                 engine->mc.init                 = nv40_mc_init;
 226                 engine->mc.takedown             = nv40_mc_takedown;
 227                 engine->timer.init              = nv04_timer_init;
 228                 engine->timer.read              = nv04_timer_read;
 229                 engine->timer.takedown          = nv04_timer_takedown;
 230                 engine->fb.init                 = nv40_fb_init;
 231                 engine->fb.takedown             = nv40_fb_takedown;
 232                 engine->fb.set_region_tiling    = nv40_fb_set_region_tiling;
 233                 engine->graph.grclass           = nv40_graph_grclass;
 234                 engine->graph.init              = nv40_graph_init;
 235                 engine->graph.takedown          = nv40_graph_takedown;
 236                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 237                 engine->graph.channel           = nv40_graph_channel;
 238                 engine->graph.create_context    = nv40_graph_create_context;
 239                 engine->graph.destroy_context   = nv40_graph_destroy_context;
 240                 engine->graph.load_context      = nv40_graph_load_context;
 241                 engine->graph.unload_context    = nv40_graph_unload_context;
 242                 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
 243                 engine->fifo.channels           = 32;
 244                 engine->fifo.init               = nv40_fifo_init;
 245                 engine->fifo.takedown           = nouveau_stub_takedown;
 246                 engine->fifo.disable            = nv04_fifo_disable;
 247                 engine->fifo.enable             = nv04_fifo_enable;
 248                 engine->fifo.reassign           = nv04_fifo_reassign;
 249                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 250                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 251                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 252                 engine->fifo.create_context     = nv40_fifo_create_context;
 253                 engine->fifo.destroy_context    = nv40_fifo_destroy_context;
 254                 engine->fifo.load_context       = nv40_fifo_load_context;
 255                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 256                 break;
 257         case 0x50:
 258         case 0x80: /* gotta love NVIDIA's consistency.. */
 259         case 0x90:
 260         case 0xA0:
 261                 engine->instmem.init            = nv50_instmem_init;
 262                 engine->instmem.takedown        = nv50_instmem_takedown;
 263                 engine->instmem.suspend         = nv50_instmem_suspend;
 264                 engine->instmem.resume          = nv50_instmem_resume;
 265                 engine->instmem.populate        = nv50_instmem_populate;
 266                 engine->instmem.clear           = nv50_instmem_clear;
 267                 engine->instmem.bind            = nv50_instmem_bind;
 268                 engine->instmem.unbind          = nv50_instmem_unbind;
 269                 if (dev_priv->chipset == 0x50)
 270                         engine->instmem.flush   = nv50_instmem_flush;
 271                 else
 272                         engine->instmem.flush   = nv84_instmem_flush;
 273                 engine->mc.init                 = nv50_mc_init;
 274                 engine->mc.takedown             = nv50_mc_takedown;
 275                 engine->timer.init              = nv04_timer_init;
 276                 engine->timer.read              = nv04_timer_read;
 277                 engine->timer.takedown          = nv04_timer_takedown;
 278                 engine->fb.init                 = nv50_fb_init;
 279                 engine->fb.takedown             = nv50_fb_takedown;
 280                 engine->graph.grclass           = nv50_graph_grclass;
 281                 engine->graph.init              = nv50_graph_init;
 282                 engine->graph.takedown          = nv50_graph_takedown;
 283                 engine->graph.fifo_access       = nv50_graph_fifo_access;
 284                 engine->graph.channel           = nv50_graph_channel;
 285                 engine->graph.create_context    = nv50_graph_create_context;
 286                 engine->graph.destroy_context   = nv50_graph_destroy_context;
 287                 engine->graph.load_context      = nv50_graph_load_context;
 288                 engine->graph.unload_context    = nv50_graph_unload_context;
 289                 engine->fifo.channels           = 128;
 290                 engine->fifo.init               = nv50_fifo_init;
 291                 engine->fifo.takedown           = nv50_fifo_takedown;
 292                 engine->fifo.disable            = nv04_fifo_disable;
 293                 engine->fifo.enable             = nv04_fifo_enable;
 294                 engine->fifo.reassign           = nv04_fifo_reassign;
 295                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 296                 engine->fifo.create_context     = nv50_fifo_create_context;
 297                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 298                 engine->fifo.load_context       = nv50_fifo_load_context;
 299                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 300                 break;
 301         default:
 302                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 303                 return 1;
 304         }
 305
 306         return 0;
 307 }
 308
 309 static unsigned int
 310 nouveau_vga_set_decode(void *priv, bool state)
 311 {
 312         struct drm_device *dev = priv;
 313         struct drm_nouveau_private *dev_priv = dev->dev_private;
 314
 315         if (dev_priv->chipset >= 0x40)
 316                 nv_wr32(dev, 0x88054, state);
 317         else
 318                 nv_wr32(dev, 0x1854, state);
 319
 320         if (state)
 321                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 322                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 323         else
 324                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 325 }
 326
 327 static int
 328 nouveau_card_init_channel(struct drm_device *dev)
 329 {
 330         struct drm_nouveau_private *dev_priv = dev->dev_private;
 331         struct nouveau_gpuobj *gpuobj;
 332         int ret;
 333
 334         ret = nouveau_channel_alloc(dev, &dev_priv->channel,
 335                                     (struct drm_file *)-2,
 336                                     NvDmaFB, NvDmaTT);
 337         if (ret)
 338                 return ret;
 339
 340         gpuobj = NULL;
 341         ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
 342                                      0, dev_priv->vram_size,
 343                                      NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
 344                                      &gpuobj);
 345         if (ret)
 346                 goto out_err;
 347
 348         ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
 349                                      gpuobj, NULL);
 350         if (ret)
 351                 goto out_err;
 352
 353         gpuobj = NULL;
 354         ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
 355                                           dev_priv->gart_info.aper_size,
 356                                           NV_DMA_ACCESS_RW, &gpuobj, NULL);
 357         if (ret)
 358                 goto out_err;
 359
 360         ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
 361                                      gpuobj, NULL);
 362         if (ret)
 363                 goto out_err;
 364
 365         return 0;
 366 out_err:
 367         nouveau_gpuobj_del(dev, &gpuobj);
 368         nouveau_channel_free(dev_priv->channel);
 369         dev_priv->channel = NULL;
 370         return ret;
 371 }
 372
 373 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 374                                          enum vga_switcheroo_state state)
 375 {
 376         struct drm_device *dev = pci_get_drvdata(pdev);
 377         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 378         if (state == VGA_SWITCHEROO_ON) {
 379                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 380                 nouveau_pci_resume(pdev);
 381                 drm_kms_helper_poll_enable(dev);
 382         } else {
 383                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 384                 drm_kms_helper_poll_disable(dev);
 385                 nouveau_pci_suspend(pdev, pmm);
 386         }
 387 }
 388
 389 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 390 {
 391         struct drm_device *dev = pci_get_drvdata(pdev);
 392         bool can_switch;
 393
 394         spin_lock(&dev->count_lock);
 395         can_switch = (dev->open_count == 0);
 396         spin_unlock(&dev->count_lock);
 397         return can_switch;
 398 }
 399
 400 int
 401 nouveau_card_init(struct drm_device *dev)
 402 {
 403         struct drm_nouveau_private *dev_priv = dev->dev_private;
 404         struct nouveau_engine *engine;
 405         int ret;
 406
 407         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 408         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 409                                        nouveau_switcheroo_can_switch);
 410
 411         /* Initialise internal driver API hooks */
 412         ret = nouveau_init_engine_ptrs(dev);
 413         if (ret)
 414                 goto out;
 415         engine = &dev_priv->engine;
 416         spin_lock_init(&dev_priv->context_switch_lock);
 417
 418         /* Parse BIOS tables / Run init tables if card not POSTed */
 419         ret = nouveau_bios_init(dev);
 420         if (ret)
 421                 goto out;
 422
 423         ret = nouveau_mem_detect(dev);
 424         if (ret)
 425                 goto out_bios;
 426
 427         ret = nouveau_gpuobj_early_init(dev);
 428         if (ret)
 429                 goto out_bios;
 430
 431         /* Initialise instance memory, must happen before mem_init so we
 432          * know exactly how much VRAM we're able to use for "normal"
 433          * purposes.
 434          */
 435         ret = engine->instmem.init(dev);
 436         if (ret)
 437                 goto out_gpuobj_early;
 438
 439         /* Setup the memory manager */
 440         ret = nouveau_mem_init(dev);
 441         if (ret)
 442                 goto out_instmem;
 443
 444         ret = nouveau_gpuobj_init(dev);
 445         if (ret)
 446                 goto out_mem;
 447
 448         /* PMC */
 449         ret = engine->mc.init(dev);
 450         if (ret)
 451                 goto out_gpuobj;
 452
 453         /* PTIMER */
 454         ret = engine->timer.init(dev);
 455         if (ret)
 456                 goto out_mc;
 457
 458         /* PFB */
 459         ret = engine->fb.init(dev);
 460         if (ret)
 461                 goto out_timer;
 462
 463         if (nouveau_noaccel)
 464                 engine->graph.accel_blocked = true;
 465         else {
 466                 /* PGRAPH */
 467                 ret = engine->graph.init(dev);
 468                 if (ret)
 469                         goto out_fb;
 470
 471                 /* PFIFO */
 472                 ret = engine->fifo.init(dev);
 473                 if (ret)
 474                         goto out_graph;
 475         }
 476
 477         if (dev_priv->card_type >= NV_50)
 478                 ret = nv50_display_create(dev);
 479         else
 480                 ret = nv04_display_create(dev);
 481         if (ret)
 482                 goto out_fifo;
 483
 484         /* this call irq_preinstall, register irq handler and
 485          * call irq_postinstall
 486          */
 487         ret = drm_irq_install(dev);
 488         if (ret)
 489                 goto out_display;
 490
 491         ret = drm_vblank_init(dev, 0);
 492         if (ret)
 493                 goto out_irq;
 494
 495         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 496
 497         if (!engine->graph.accel_blocked) {
 498                 ret = nouveau_card_init_channel(dev);
 499                 if (ret)
 500                         goto out_irq;
 501         }
 502
 503         ret = nouveau_backlight_init(dev);
 504         if (ret)
 505                 NV_ERROR(dev, "Error %d registering backlight\n", ret);
 506
 507         nouveau_fbcon_init(dev);
 508         drm_kms_helper_poll_init(dev);
 509         return 0;
 510
 511 out_irq:
 512         drm_irq_uninstall(dev);
 513 out_display:
 514         if (dev_priv->card_type >= NV_50)
 515                 nv50_display_destroy(dev);
 516         else
 517                 nv04_display_destroy(dev);
 518 out_fifo:
 519         if (!nouveau_noaccel)
 520                 engine->fifo.takedown(dev);
 521 out_graph:
 522         if (!nouveau_noaccel)
 523                 engine->graph.takedown(dev);
 524 out_fb:
 525         engine->fb.takedown(dev);
 526 out_timer:
 527         engine->timer.takedown(dev);
 528 out_mc:
 529         engine->mc.takedown(dev);
 530 out_gpuobj:
 531         nouveau_gpuobj_takedown(dev);
 532 out_mem:
 533         nouveau_sgdma_takedown(dev);
 534         nouveau_mem_close(dev);
 535 out_instmem:
 536         engine->instmem.takedown(dev);
 537 out_gpuobj_early:
 538         nouveau_gpuobj_late_takedown(dev);
 539 out_bios:
 540         nouveau_bios_takedown(dev);
 541 out:
 542         vga_client_register(dev->pdev, NULL, NULL, NULL);
 543         return ret;
 544 }
 545
 546 static void nouveau_card_takedown(struct drm_device *dev)
 547 {
 548         struct drm_nouveau_private *dev_priv = dev->dev_private;
 549         struct nouveau_engine *engine = &dev_priv->engine;
 550
 551         nouveau_backlight_exit(dev);
 552
 553         if (dev_priv->channel) {
 554                 nouveau_channel_free(dev_priv->channel);
 555                 dev_priv->channel = NULL;
 556         }
 557
 558         if (!nouveau_noaccel) {
 559                 engine->fifo.takedown(dev);
 560                 engine->graph.takedown(dev);
 561         }
 562         engine->fb.takedown(dev);
 563         engine->timer.takedown(dev);
 564         engine->mc.takedown(dev);
 565
 566         mutex_lock(&dev->struct_mutex);
 567         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 568         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 569         mutex_unlock(&dev->struct_mutex);
 570         nouveau_sgdma_takedown(dev);
 571
 572         nouveau_gpuobj_takedown(dev);
 573         nouveau_mem_close(dev);
 574         engine->instmem.takedown(dev);
 575
 576         drm_irq_uninstall(dev);
 577
 578         nouveau_gpuobj_late_takedown(dev);
 579         nouveau_bios_takedown(dev);
 580
 581         vga_client_register(dev->pdev, NULL, NULL, NULL);
 582 }
 583
 584 /* here a client dies, release the stuff that was allocated for its
 585  * file_priv */
 586 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 587 {
 588         nouveau_channel_cleanup(dev, file_priv);
 589 }
 590
 591 /* first module load, setup the mmio/fb mapping */
 592 /* KMS: we need mmio at load time, not when the first drm client opens. */
 593 int nouveau_firstopen(struct drm_device *dev)
 594 {
 595         return 0;
 596 }
 597
 598 /* if we have an OF card, copy vbios to RAMIN */
 599 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 600 {
 601 #if defined(__powerpc__)
 602         int size, i;
 603         const uint32_t *bios;
 604         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 605         if (!dn) {
 606                 NV_INFO(dev, "Unable to get the OF node\n");
 607                 return;
 608         }
 609
 610         bios = of_get_property(dn, "NVDA,BMP", &size);
 611         if (bios) {
 612                 for (i = 0; i < size; i += 4)
 613                         nv_wi32(dev, i, bios[i/4]);
 614                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 615         } else {
 616                 NV_INFO(dev, "Unable to get the OF bios\n");
 617         }
 618 #endif
 619 }
 620
 621 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 622 {
 623         struct pci_dev *pdev = dev->pdev;
 624         struct apertures_struct *aper = alloc_apertures(3);
 625         if (!aper)
 626                 return NULL;
 627
 628         aper->ranges[0].base = pci_resource_start(pdev, 1);
 629         aper->ranges[0].size = pci_resource_len(pdev, 1);
 630         aper->count = 1;
 631
 632         if (pci_resource_len(pdev, 2)) {
 633                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 634                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 635                 aper->count++;
 636         }
 637
 638         if (pci_resource_len(pdev, 3)) {
 639                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 640                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 641                 aper->count++;
 642         }
 643
 644         return aper;
 645 }
 646
 647 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 648 {
 649         struct drm_nouveau_private *dev_priv = dev->dev_private;
 650         bool primary = false;
 651         dev_priv->apertures = nouveau_get_apertures(dev);
 652         if (!dev_priv->apertures)
 653                 return -ENOMEM;
 654
 655 #ifdef CONFIG_X86
 656         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 657 #endif
 658
 659         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 660         return 0;
 661 }
 662
 663 int nouveau_load(struct drm_device *dev, unsigned long flags)
 664 {
 665         struct drm_nouveau_private *dev_priv;
 666         uint32_t reg0;
 667         resource_size_t mmio_start_offs;
 668         int ret;
 669
 670         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 671         if (!dev_priv)
 672                 return -ENOMEM;
 673         dev->dev_private = dev_priv;
 674         dev_priv->dev = dev;
 675
 676         dev_priv->flags = flags & NOUVEAU_FLAGS;
 677
 678         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 679                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 680
 681         dev_priv->wq = create_workqueue("nouveau");
 682         if (!dev_priv->wq)
 683                 return -EINVAL;
 684
 685         /* resource 0 is mmio regs */
 686         /* resource 1 is linear FB */
 687         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 688         /* resource 6 is bios */
 689
 690         /* map the mmio regs */
 691         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 692         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 693         if (!dev_priv->mmio) {
 694                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 695                          "Please report your setup to " DRIVER_EMAIL "\n");
 696                 return -EINVAL;
 697         }
 698         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 699                                         (unsigned long long)mmio_start_offs);
 700
 701 #ifdef __BIG_ENDIAN
 702         /* Put the card in BE mode if it's not */
 703         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 704                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 705
 706         DRM_MEMORYBARRIER();
 707 #endif
 708
 709         /* Time to determine the card architecture */
 710         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 711
 712         /* We're dealing with >=NV10 */
 713         if ((reg0 & 0x0f000000) > 0) {
 714                 /* Bit 27-20 contain the architecture in hex */
 715                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 716         /* NV04 or NV05 */
 717         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 718                 if (reg0 & 0x00f00000)
 719                         dev_priv->chipset = 0x05;
 720                 else
 721                         dev_priv->chipset = 0x04;
 722         } else
 723                 dev_priv->chipset = 0xff;
 724
 725         switch (dev_priv->chipset & 0xf0) {
 726         case 0x00:
 727         case 0x10:
 728         case 0x20:
 729         case 0x30:
 730                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 731                 break;
 732         case 0x40:
 733         case 0x60:
 734                 dev_priv->card_type = NV_40;
 735                 break;
 736         case 0x50:
 737         case 0x80:
 738         case 0x90:
 739         case 0xa0:
 740                 dev_priv->card_type = NV_50;
 741                 break;
 742         default:
 743                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 744                 return -EINVAL;
 745         }
 746
 747         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
 748                 dev_priv->card_type, reg0);
 749
 750         ret = nouveau_remove_conflicting_drivers(dev);
 751         if (ret)
 752                 return ret;
 753
 754         /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
 755         if (dev_priv->card_type >= NV_40) {
 756                 int ramin_bar = 2;
 757                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
 758                         ramin_bar = 3;
 759
 760                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
 761                 dev_priv->ramin =
 762                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
 763                                 dev_priv->ramin_size);
 764                 if (!dev_priv->ramin) {
 765                         NV_ERROR(dev, "Failed to PRAMIN BAR");
 766                         return -ENOMEM;
 767                 }
 768         } else {
 769                 dev_priv->ramin_size = 1 * 1024 * 1024;
 770                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
 771                                           dev_priv->ramin_size);
 772                 if (!dev_priv->ramin) {
 773                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
 774                         return -ENOMEM;
 775                 }
 776         }
 777
 778         nouveau_OF_copy_vbios_to_ramin(dev);
 779
 780         /* Special flags */
 781         if (dev->pci_device == 0x01a0)
 782                 dev_priv->flags |= NV_NFORCE;
 783         else if (dev->pci_device == 0x01f0)
 784                 dev_priv->flags |= NV_NFORCE2;
 785
 786         /* For kernel modesetting, init card now and bring up fbcon */
 787         ret = nouveau_card_init(dev);
 788         if (ret)
 789                 return ret;
 790
 791         return 0;
 792 }
 793
 794 void nouveau_lastclose(struct drm_device *dev)
 795 {
 796 }
 797
 798 int nouveau_unload(struct drm_device *dev)
 799 {
 800         struct drm_nouveau_private *dev_priv = dev->dev_private;
 801
 802         drm_kms_helper_poll_fini(dev);
 803         nouveau_fbcon_fini(dev);
 804         if (dev_priv->card_type >= NV_50)
 805                 nv50_display_destroy(dev);
 806         else
 807                 nv04_display_destroy(dev);
 808         nouveau_card_takedown(dev);
 809
 810         iounmap(dev_priv->mmio);
 811         iounmap(dev_priv->ramin);
 812
 813         kfree(dev_priv);
 814         dev->dev_private = NULL;
 815         return 0;
 816 }
 817
 818 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
 819                                                 struct drm_file *file_priv)
 820 {
 821         struct drm_nouveau_private *dev_priv = dev->dev_private;
 822         struct drm_nouveau_getparam *getparam = data;
 823
 824         switch (getparam->param) {
 825         case NOUVEAU_GETPARAM_CHIPSET_ID:
 826                 getparam->value = dev_priv->chipset;
 827                 break;
 828         case NOUVEAU_GETPARAM_PCI_VENDOR:
 829                 getparam->value = dev->pci_vendor;
 830                 break;
 831         case NOUVEAU_GETPARAM_PCI_DEVICE:
 832                 getparam->value = dev->pci_device;
 833                 break;
 834         case NOUVEAU_GETPARAM_BUS_TYPE:
 835                 if (drm_device_is_agp(dev))
 836                         getparam->value = NV_AGP;
 837                 else if (drm_device_is_pcie(dev))
 838                         getparam->value = NV_PCIE;
 839                 else
 840                         getparam->value = NV_PCI;
 841                 break;
 842         case NOUVEAU_GETPARAM_FB_PHYSICAL:
 843                 getparam->value = dev_priv->fb_phys;
 844                 break;
 845         case NOUVEAU_GETPARAM_AGP_PHYSICAL:
 846                 getparam->value = dev_priv->gart_info.aper_base;
 847                 break;
 848         case NOUVEAU_GETPARAM_PCI_PHYSICAL:
 849                 if (dev->sg) {
 850                         getparam->value = (unsigned long)dev->sg->virtual;
 851                 } else {
 852                         NV_ERROR(dev, "Requested PCIGART address, "
 853                                         "while no PCIGART was created\n");
 854                         return -EINVAL;
 855                 }
 856                 break;
 857         case NOUVEAU_GETPARAM_FB_SIZE:
 858                 getparam->value = dev_priv->fb_available_size;
 859                 break;
 860         case NOUVEAU_GETPARAM_AGP_SIZE:
 861                 getparam->value = dev_priv->gart_info.aper_size;
 862                 break;
 863         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
 864                 getparam->value = dev_priv->vm_vram_base;
 865                 break;
 866         case NOUVEAU_GETPARAM_PTIMER_TIME:
 867                 getparam->value = dev_priv->engine.timer.read(dev);
 868                 break;
 869         case NOUVEAU_GETPARAM_GRAPH_UNITS:
 870                 /* NV40 and NV50 versions are quite different, but register
 871                  * address is the same. User is supposed to know the card
 872                  * family anyway... */
 873                 if (dev_priv->chipset >= 0x40) {
 874                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
 875                         break;
 876                 }
 877                 /* FALLTHRU */
 878         default:
 879                 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
 880                 return -EINVAL;
 881         }
 882
 883         return 0;
 884 }
 885
 886 int
 887 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
 888                        struct drm_file *file_priv)
 889 {
 890         struct drm_nouveau_setparam *setparam = data;
 891
 892         switch (setparam->param) {
 893         default:
 894                 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
 895                 return -EINVAL;
 896         }
 897
 898         return 0;
 899 }
 900
 901 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
 902 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
 903                         uint32_t reg, uint32_t mask, uint32_t val)
 904 {
 905         struct drm_nouveau_private *dev_priv = dev->dev_private;
 906         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 907         uint64_t start = ptimer->read(dev);
 908
 909         do {
 910                 if ((nv_rd32(dev, reg) & mask) == val)
 911                         return true;
 912         } while (ptimer->read(dev) - start < timeout);
 913
 914         return false;
 915 }
 916
 917 /* Waits for PGRAPH to go completely idle */
 918 bool nouveau_wait_for_idle(struct drm_device *dev)
 919 {
 920         if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
 921                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
 922                          nv_rd32(dev, NV04_PGRAPH_STATUS));
 923                 return false;
 924         }
 925
 926         return true;
 927 }
 928