2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 15
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
63 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
64 #define NV50_VM_BLOCK (512*1024*1024ULL)
65 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct ttm_buffer_object bo;
69 struct ttm_placement placement;
71 struct ttm_bo_kmap_obj kmap;
72 struct list_head head;
74 /* protected by ttm_bo_reserve() */
75 struct drm_file *reserved_by;
76 struct list_head entry;
79 struct nouveau_channel *channel;
87 struct drm_gem_object *gem;
88 struct drm_file *cpu_filp;
92 static inline struct nouveau_bo *
93 nouveau_bo(struct ttm_buffer_object *bo)
95 return container_of(bo, struct nouveau_bo, bo);
98 static inline struct nouveau_bo *
99 nouveau_gem_object(struct drm_gem_object *gem)
101 return gem ? gem->driver_private : NULL;
104 /* TODO: submit equivalent to TTM generic API upstream? */
105 static inline void __iomem *
106 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
109 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
110 &nvbo->kmap, &is_iomem);
111 WARN_ON_ONCE(ioptr && !is_iomem);
116 struct mem_block *next;
117 struct mem_block *prev;
120 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
124 NV_NFORCE = 0x10000000,
125 NV_NFORCE2 = 0x20000000
128 #define NVOBJ_ENGINE_SW 0
129 #define NVOBJ_ENGINE_GR 1
130 #define NVOBJ_ENGINE_DISPLAY 2
131 #define NVOBJ_ENGINE_INT 0xdeadbeef
133 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
134 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
135 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
136 #define NVOBJ_FLAG_FAKE (1 << 3)
137 struct nouveau_gpuobj {
138 struct list_head list;
140 struct nouveau_channel *im_channel;
141 struct mem_block *im_pramin;
142 struct nouveau_bo *im_backing;
143 uint32_t im_backing_start;
144 uint32_t *im_backing_suspend;
153 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
157 struct nouveau_gpuobj_ref {
158 struct list_head list;
160 struct nouveau_gpuobj *gpuobj;
163 struct nouveau_channel *channel;
167 struct nouveau_channel {
168 struct drm_device *dev;
171 /* owner of this fifo */
172 struct drm_file *file_priv;
173 /* mapping of the fifo itself */
174 struct drm_local_map *map;
176 /* mapping of the regs controling the fifo */
183 /* lock protects the pending list only */
185 struct list_head pending;
187 uint32_t sequence_ack;
188 uint32_t last_sequence_irq;
191 /* DMA push buffer */
192 struct nouveau_gpuobj_ref *pushbuf;
193 struct nouveau_bo *pushbuf_bo;
194 uint32_t pushbuf_base;
196 /* Notifier memory */
197 struct nouveau_bo *notifier_bo;
198 struct mem_block *notifier_heap;
201 struct nouveau_gpuobj_ref *ramfc;
202 struct nouveau_gpuobj_ref *cache;
205 /* XXX may be merge 2 pointers as private data ??? */
206 struct nouveau_gpuobj_ref *ramin_grctx;
210 struct nouveau_gpuobj *vm_pd;
211 struct nouveau_gpuobj_ref *vm_gart_pt;
212 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
215 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
216 struct mem_block *ramin_heap; /* Private PRAMIN heap */
217 struct nouveau_gpuobj_ref *ramht; /* Hash table */
218 struct list_head ramht_refs; /* Objects referenced by RAMHT */
220 /* GPU object info for stuff used in-kernel (mm_enabled) */
222 uint32_t vram_handle;
223 uint32_t gart_handle;
226 /* Push buffer state (only for drm's channel on !mm_enabled) */
232 /* access via pushbuf_bo */
235 uint32_t sw_subchannel[8];
238 struct nouveau_gpuobj *vblsem;
239 uint32_t vblsem_offset;
240 uint32_t vblsem_rval;
241 struct list_head vbl_wait;
247 struct drm_info_list info;
251 struct nouveau_instmem_engine {
254 int (*init)(struct drm_device *dev);
255 void (*takedown)(struct drm_device *dev);
256 int (*suspend)(struct drm_device *dev);
257 void (*resume)(struct drm_device *dev);
259 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
261 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
262 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
263 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
264 void (*prepare_access)(struct drm_device *, bool write);
265 void (*finish_access)(struct drm_device *);
268 struct nouveau_mc_engine {
269 int (*init)(struct drm_device *dev);
270 void (*takedown)(struct drm_device *dev);
273 struct nouveau_timer_engine {
274 int (*init)(struct drm_device *dev);
275 void (*takedown)(struct drm_device *dev);
276 uint64_t (*read)(struct drm_device *dev);
279 struct nouveau_fb_engine {
282 int (*init)(struct drm_device *dev);
283 void (*takedown)(struct drm_device *dev);
285 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
286 uint32_t size, uint32_t pitch);
289 struct nouveau_fifo_engine {
294 int (*init)(struct drm_device *);
295 void (*takedown)(struct drm_device *);
297 void (*disable)(struct drm_device *);
298 void (*enable)(struct drm_device *);
299 bool (*reassign)(struct drm_device *, bool enable);
300 bool (*cache_flush)(struct drm_device *dev);
301 bool (*cache_pull)(struct drm_device *dev, bool enable);
303 int (*channel_id)(struct drm_device *);
305 int (*create_context)(struct nouveau_channel *);
306 void (*destroy_context)(struct nouveau_channel *);
307 int (*load_context)(struct nouveau_channel *);
308 int (*unload_context)(struct drm_device *);
311 struct nouveau_pgraph_object_method {
313 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
317 struct nouveau_pgraph_object_class {
320 struct nouveau_pgraph_object_method *methods;
323 struct nouveau_pgraph_engine {
324 struct nouveau_pgraph_object_class *grclass;
330 int (*init)(struct drm_device *);
331 void (*takedown)(struct drm_device *);
333 void (*fifo_access)(struct drm_device *, bool);
335 struct nouveau_channel *(*channel)(struct drm_device *);
336 int (*create_context)(struct nouveau_channel *);
337 void (*destroy_context)(struct nouveau_channel *);
338 int (*load_context)(struct nouveau_channel *);
339 int (*unload_context)(struct drm_device *);
341 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
342 uint32_t size, uint32_t pitch);
345 struct nouveau_engine {
346 struct nouveau_instmem_engine instmem;
347 struct nouveau_mc_engine mc;
348 struct nouveau_timer_engine timer;
349 struct nouveau_fb_engine fb;
350 struct nouveau_pgraph_engine graph;
351 struct nouveau_fifo_engine fifo;
354 struct nouveau_pll_vals {
358 uint8_t N1, M1, N2, M2;
360 uint8_t M1, N1, M2, N2;
365 } __attribute__((packed));
372 enum nv04_fp_display_regs {
382 struct nv04_crtc_reg {
383 unsigned char MiscOutReg; /* */
386 uint8_t Sequencer[5];
388 uint8_t Attribute[21];
389 unsigned char DAC[768]; /* Internal Colorlookuptable */
399 uint32_t crtc_eng_ctrl;
402 uint32_t nv10_cursync;
403 struct nouveau_pll_vals pllvals;
404 uint32_t ramdac_gen_ctrl;
410 uint32_t tv_vsync_delay;
413 uint32_t tv_hsync_delay;
414 uint32_t tv_hsync_delay2;
415 uint32_t fp_horiz_regs[7];
416 uint32_t fp_vert_regs[7];
419 uint32_t dither_regs[6];
423 uint32_t fp_margin_color;
428 uint32_t ctv_regs[38];
431 struct nv04_output_reg {
436 struct nv04_mode_state {
464 uint32_t cursorConfig;
473 struct nv04_crtc_reg crtc_reg[2];
476 enum nouveau_card_type {
485 struct drm_nouveau_private {
486 struct drm_device *dev;
488 NOUVEAU_CARD_INIT_DOWN,
489 NOUVEAU_CARD_INIT_DONE,
490 NOUVEAU_CARD_INIT_FAILED
493 /* the card type, takes NV_* as values */
494 enum nouveau_card_type card_type;
495 /* exact chipset, derived from NV_PMC_BOOT_0 */
503 struct workqueue_struct *wq;
504 struct work_struct irq_work;
506 struct list_head vbl_waiting;
509 struct ttm_global_reference mem_global_ref;
510 struct ttm_bo_global_ref bo_global_ref;
511 struct ttm_bo_device bdev;
512 spinlock_t bo_list_lock;
513 struct list_head bo_list;
514 atomic_t validate_sequence;
517 struct fb_info *fbdev_info;
519 int fifo_alloc_count;
520 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
522 struct nouveau_engine engine;
523 struct nouveau_channel *channel;
525 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
526 struct nouveau_gpuobj *ramht;
527 uint32_t ramin_rsvd_vram;
528 uint32_t ramht_offset;
531 uint32_t ramfc_offset;
533 uint32_t ramro_offset;
536 /* base physical adresses */
538 uint64_t fb_available_size;
539 uint64_t fb_mappable_pages;
540 uint64_t fb_aper_free;
544 NOUVEAU_GART_NONE = 0,
552 struct nouveau_gpuobj *sg_ctxdma;
553 struct page *sg_dummy_page;
554 dma_addr_t sg_dummy_bus;
557 struct drm_ttm_backend *sg_be;
558 unsigned long sg_handle;
561 /* G8x/G9x virtual address space */
562 uint64_t vm_gart_base;
563 uint64_t vm_gart_size;
564 uint64_t vm_vram_base;
565 uint64_t vm_vram_size;
567 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
570 /* the mtrr covering the FB */
573 struct mem_block *ramin_heap;
575 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
576 uint32_t ctx_table_size;
577 struct nouveau_gpuobj_ref *ctx_table;
579 struct list_head gpuobj_list;
582 struct nouveau_bios_info *vbios;
584 struct nv04_mode_state mode_reg;
585 struct nv04_mode_state saved_reg;
586 uint32_t saved_vga_font[4][16384];
588 uint32_t dac_users[4];
590 struct nouveau_suspend_resume {
592 uint32_t graph_ctx_control;
593 uint32_t graph_state;
594 uint32_t *ramin_copy;
598 struct backlight_device *backlight;
601 struct nouveau_channel *evo;
604 struct dentry *channel_root;
608 static inline struct drm_nouveau_private *
609 nouveau_bdev(struct ttm_bo_device *bd)
611 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
615 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
617 struct nouveau_bo *prev;
623 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
625 struct ttm_buffer_object *bo = &prev->bo;
633 #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
634 struct drm_nouveau_private *nv = dev->dev_private; \
635 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
636 NV_ERROR(dev, "called without init\n"); \
641 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
642 struct drm_nouveau_private *nv = dev->dev_private; \
643 if (!nouveau_channel_owner(dev, (cl), (id))) { \
644 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
645 DRM_CURRENTPID, (id)); \
648 (ch) = nv->fifos[(id)]; \
652 extern int nouveau_noagp;
653 extern int nouveau_duallink;
654 extern int nouveau_uscript_lvds;
655 extern int nouveau_uscript_tmds;
656 extern int nouveau_vram_pushbuf;
657 extern int nouveau_vram_notify;
658 extern int nouveau_fbpercrtc;
659 extern char *nouveau_tv_norm;
660 extern int nouveau_reg_debug;
661 extern char *nouveau_vbios;
662 extern int nouveau_ctxfw;
664 /* nouveau_state.c */
665 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
666 extern int nouveau_load(struct drm_device *, unsigned long flags);
667 extern int nouveau_firstopen(struct drm_device *);
668 extern void nouveau_lastclose(struct drm_device *);
669 extern int nouveau_unload(struct drm_device *);
670 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
672 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
674 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
675 uint32_t reg, uint32_t mask, uint32_t val);
676 extern bool nouveau_wait_for_idle(struct drm_device *);
677 extern int nouveau_card_init(struct drm_device *);
678 extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
680 extern int nouveau_ioctl_suspend(struct drm_device *, void *data,
682 extern int nouveau_ioctl_resume(struct drm_device *, void *data,
686 extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
688 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
689 uint64_t size, int align2,
690 struct drm_file *, int tail);
691 extern void nouveau_mem_takedown(struct mem_block **heap);
692 extern void nouveau_mem_free_block(struct mem_block *);
693 extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
694 extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
695 extern int nouveau_mem_init(struct drm_device *);
696 extern int nouveau_mem_init_agp(struct drm_device *);
697 extern void nouveau_mem_close(struct drm_device *);
698 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
699 uint32_t size, uint32_t flags,
701 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
704 /* nouveau_notifier.c */
705 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
706 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
707 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
708 int cout, uint32_t *offset);
709 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
710 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
712 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
715 /* nouveau_channel.c */
716 extern struct drm_ioctl_desc nouveau_ioctls[];
717 extern int nouveau_max_ioctl;
718 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
719 extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
721 extern int nouveau_channel_alloc(struct drm_device *dev,
722 struct nouveau_channel **chan,
723 struct drm_file *file_priv,
724 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
725 extern void nouveau_channel_free(struct nouveau_channel *);
726 extern int nouveau_channel_idle(struct nouveau_channel *chan);
728 /* nouveau_object.c */
729 extern int nouveau_gpuobj_early_init(struct drm_device *);
730 extern int nouveau_gpuobj_init(struct drm_device *);
731 extern void nouveau_gpuobj_takedown(struct drm_device *);
732 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
733 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
734 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
735 extern void nouveau_gpuobj_resume(struct drm_device *dev);
736 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
737 uint32_t vram_h, uint32_t tt_h);
738 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
739 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
740 uint32_t size, int align, uint32_t flags,
741 struct nouveau_gpuobj **);
742 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
743 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
744 uint32_t handle, struct nouveau_gpuobj *,
745 struct nouveau_gpuobj_ref **);
746 extern int nouveau_gpuobj_ref_del(struct drm_device *,
747 struct nouveau_gpuobj_ref **);
748 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
749 struct nouveau_gpuobj_ref **ref_ret);
750 extern int nouveau_gpuobj_new_ref(struct drm_device *,
751 struct nouveau_channel *alloc_chan,
752 struct nouveau_channel *ref_chan,
753 uint32_t handle, uint32_t size, int align,
754 uint32_t flags, struct nouveau_gpuobj_ref **);
755 extern int nouveau_gpuobj_new_fake(struct drm_device *,
756 uint32_t p_offset, uint32_t b_offset,
757 uint32_t size, uint32_t flags,
758 struct nouveau_gpuobj **,
759 struct nouveau_gpuobj_ref**);
760 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
761 uint64_t offset, uint64_t size, int access,
762 int target, struct nouveau_gpuobj **);
763 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
764 uint64_t offset, uint64_t size,
765 int access, struct nouveau_gpuobj **,
767 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
768 struct nouveau_gpuobj **);
769 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
771 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
775 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
776 extern void nouveau_irq_preinstall(struct drm_device *);
777 extern int nouveau_irq_postinstall(struct drm_device *);
778 extern void nouveau_irq_uninstall(struct drm_device *);
780 /* nouveau_sgdma.c */
781 extern int nouveau_sgdma_init(struct drm_device *);
782 extern void nouveau_sgdma_takedown(struct drm_device *);
783 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
785 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
787 /* nouveau_debugfs.c */
788 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
789 extern int nouveau_debugfs_init(struct drm_minor *);
790 extern void nouveau_debugfs_takedown(struct drm_minor *);
791 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
792 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
795 nouveau_debugfs_init(struct drm_minor *minor)
800 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
805 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
811 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
817 extern int nouveau_dma_init(struct nouveau_channel *);
818 extern int nouveau_dma_wait(struct nouveau_channel *, int size);
822 extern int nouveau_hybrid_setup(struct drm_device *dev);
823 extern bool nouveau_dsm_probe(struct drm_device *dev);
825 static inline int nouveau_hybrid_setup(struct drm_device *dev)
829 static inline bool nouveau_dsm_probe(struct drm_device *dev)
835 /* nouveau_backlight.c */
836 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
837 extern int nouveau_backlight_init(struct drm_device *);
838 extern void nouveau_backlight_exit(struct drm_device *);
840 static inline int nouveau_backlight_init(struct drm_device *dev)
845 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
849 extern int nouveau_bios_init(struct drm_device *);
850 extern void nouveau_bios_takedown(struct drm_device *dev);
851 extern int nouveau_run_vbios_init(struct drm_device *);
852 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
854 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
856 extern struct dcb_connector_table_entry *
857 nouveau_bios_connector_entry(struct drm_device *, int index);
858 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
860 extern int nouveau_bios_run_display_table(struct drm_device *,
862 uint32_t script, int pxclk);
863 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
865 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
866 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
867 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
868 bool *dl, bool *if_is_24bit);
869 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
870 int head, int pxclk);
871 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
872 enum LVDS_script, int pxclk);
875 int nouveau_ttm_global_init(struct drm_nouveau_private *);
876 void nouveau_ttm_global_release(struct drm_nouveau_private *);
877 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
880 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
881 uint8_t *data, int data_nr);
882 bool nouveau_dp_detect(struct drm_encoder *);
883 bool nouveau_dp_link_train(struct drm_encoder *);
886 extern int nv04_fb_init(struct drm_device *);
887 extern void nv04_fb_takedown(struct drm_device *);
890 extern int nv10_fb_init(struct drm_device *);
891 extern void nv10_fb_takedown(struct drm_device *);
892 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
896 extern int nv40_fb_init(struct drm_device *);
897 extern void nv40_fb_takedown(struct drm_device *);
898 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
902 extern int nv04_fifo_init(struct drm_device *);
903 extern void nv04_fifo_disable(struct drm_device *);
904 extern void nv04_fifo_enable(struct drm_device *);
905 extern bool nv04_fifo_reassign(struct drm_device *, bool);
906 extern bool nv04_fifo_cache_flush(struct drm_device *);
907 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
908 extern int nv04_fifo_channel_id(struct drm_device *);
909 extern int nv04_fifo_create_context(struct nouveau_channel *);
910 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
911 extern int nv04_fifo_load_context(struct nouveau_channel *);
912 extern int nv04_fifo_unload_context(struct drm_device *);
915 extern int nv10_fifo_init(struct drm_device *);
916 extern int nv10_fifo_channel_id(struct drm_device *);
917 extern int nv10_fifo_create_context(struct nouveau_channel *);
918 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
919 extern int nv10_fifo_load_context(struct nouveau_channel *);
920 extern int nv10_fifo_unload_context(struct drm_device *);
923 extern int nv40_fifo_init(struct drm_device *);
924 extern int nv40_fifo_create_context(struct nouveau_channel *);
925 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
926 extern int nv40_fifo_load_context(struct nouveau_channel *);
927 extern int nv40_fifo_unload_context(struct drm_device *);
930 extern int nv50_fifo_init(struct drm_device *);
931 extern void nv50_fifo_takedown(struct drm_device *);
932 extern int nv50_fifo_channel_id(struct drm_device *);
933 extern int nv50_fifo_create_context(struct nouveau_channel *);
934 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
935 extern int nv50_fifo_load_context(struct nouveau_channel *);
936 extern int nv50_fifo_unload_context(struct drm_device *);
939 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
940 extern int nv04_graph_init(struct drm_device *);
941 extern void nv04_graph_takedown(struct drm_device *);
942 extern void nv04_graph_fifo_access(struct drm_device *, bool);
943 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
944 extern int nv04_graph_create_context(struct nouveau_channel *);
945 extern void nv04_graph_destroy_context(struct nouveau_channel *);
946 extern int nv04_graph_load_context(struct nouveau_channel *);
947 extern int nv04_graph_unload_context(struct drm_device *);
948 extern void nv04_graph_context_switch(struct drm_device *);
951 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
952 extern int nv10_graph_init(struct drm_device *);
953 extern void nv10_graph_takedown(struct drm_device *);
954 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
955 extern int nv10_graph_create_context(struct nouveau_channel *);
956 extern void nv10_graph_destroy_context(struct nouveau_channel *);
957 extern int nv10_graph_load_context(struct nouveau_channel *);
958 extern int nv10_graph_unload_context(struct drm_device *);
959 extern void nv10_graph_context_switch(struct drm_device *);
960 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
964 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
965 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
966 extern int nv20_graph_create_context(struct nouveau_channel *);
967 extern void nv20_graph_destroy_context(struct nouveau_channel *);
968 extern int nv20_graph_load_context(struct nouveau_channel *);
969 extern int nv20_graph_unload_context(struct drm_device *);
970 extern int nv20_graph_init(struct drm_device *);
971 extern void nv20_graph_takedown(struct drm_device *);
972 extern int nv30_graph_init(struct drm_device *);
973 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
977 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
978 extern int nv40_graph_init(struct drm_device *);
979 extern void nv40_graph_takedown(struct drm_device *);
980 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
981 extern int nv40_graph_create_context(struct nouveau_channel *);
982 extern void nv40_graph_destroy_context(struct nouveau_channel *);
983 extern int nv40_graph_load_context(struct nouveau_channel *);
984 extern int nv40_graph_unload_context(struct drm_device *);
985 extern void nv40_grctx_init(struct nouveau_grctx *);
986 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
990 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
991 extern int nv50_graph_init(struct drm_device *);
992 extern void nv50_graph_takedown(struct drm_device *);
993 extern void nv50_graph_fifo_access(struct drm_device *, bool);
994 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
995 extern int nv50_graph_create_context(struct nouveau_channel *);
996 extern void nv50_graph_destroy_context(struct nouveau_channel *);
997 extern int nv50_graph_load_context(struct nouveau_channel *);
998 extern int nv50_graph_unload_context(struct drm_device *);
999 extern void nv50_graph_context_switch(struct drm_device *);
1001 /* nouveau_grctx.c */
1002 extern int nouveau_grctx_prog_load(struct drm_device *);
1003 extern void nouveau_grctx_vals_load(struct drm_device *,
1004 struct nouveau_gpuobj *);
1005 extern void nouveau_grctx_fini(struct drm_device *);
1007 /* nv04_instmem.c */
1008 extern int nv04_instmem_init(struct drm_device *);
1009 extern void nv04_instmem_takedown(struct drm_device *);
1010 extern int nv04_instmem_suspend(struct drm_device *);
1011 extern void nv04_instmem_resume(struct drm_device *);
1012 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1014 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1015 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1016 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1017 extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1018 extern void nv04_instmem_finish_access(struct drm_device *);
1020 /* nv50_instmem.c */
1021 extern int nv50_instmem_init(struct drm_device *);
1022 extern void nv50_instmem_takedown(struct drm_device *);
1023 extern int nv50_instmem_suspend(struct drm_device *);
1024 extern void nv50_instmem_resume(struct drm_device *);
1025 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1027 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1028 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1029 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1030 extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1031 extern void nv50_instmem_finish_access(struct drm_device *);
1034 extern int nv04_mc_init(struct drm_device *);
1035 extern void nv04_mc_takedown(struct drm_device *);
1038 extern int nv40_mc_init(struct drm_device *);
1039 extern void nv40_mc_takedown(struct drm_device *);
1042 extern int nv50_mc_init(struct drm_device *);
1043 extern void nv50_mc_takedown(struct drm_device *);
1046 extern int nv04_timer_init(struct drm_device *);
1047 extern uint64_t nv04_timer_read(struct drm_device *);
1048 extern void nv04_timer_takedown(struct drm_device *);
1050 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1054 extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
1055 extern enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
1056 struct drm_connector *connector);
1057 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1058 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1061 extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry);
1062 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1063 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1065 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1066 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1069 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1070 extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1073 extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1074 extern enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
1075 struct drm_connector *connector,
1078 /* nv04_display.c */
1079 extern int nv04_display_create(struct drm_device *);
1080 extern void nv04_display_destroy(struct drm_device *);
1081 extern void nv04_display_restore(struct drm_device *);
1084 extern int nv04_crtc_create(struct drm_device *, int index);
1087 extern struct ttm_bo_driver nouveau_bo_driver;
1088 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1089 int size, int align, uint32_t flags,
1090 uint32_t tile_mode, uint32_t tile_flags,
1091 bool no_vm, bool mappable, struct nouveau_bo **);
1092 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1093 extern int nouveau_bo_unpin(struct nouveau_bo *);
1094 extern int nouveau_bo_map(struct nouveau_bo *);
1095 extern void nouveau_bo_unmap(struct nouveau_bo *);
1096 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype);
1097 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1098 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1099 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1100 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1102 /* nouveau_fence.c */
1103 struct nouveau_fence;
1104 extern int nouveau_fence_init(struct nouveau_channel *);
1105 extern void nouveau_fence_fini(struct nouveau_channel *);
1106 extern void nouveau_fence_update(struct nouveau_channel *);
1107 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1109 extern int nouveau_fence_emit(struct nouveau_fence *);
1110 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1111 extern bool nouveau_fence_signalled(void *obj, void *arg);
1112 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1113 extern int nouveau_fence_flush(void *obj, void *arg);
1114 extern void nouveau_fence_unref(void **obj);
1115 extern void *nouveau_fence_ref(void *obj);
1116 extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1119 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1120 int size, int align, uint32_t flags,
1121 uint32_t tile_mode, uint32_t tile_flags,
1122 bool no_vm, bool mappable, struct nouveau_bo **);
1123 extern int nouveau_gem_object_new(struct drm_gem_object *);
1124 extern void nouveau_gem_object_del(struct drm_gem_object *);
1125 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1127 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1129 extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *,
1131 extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *,
1133 extern int nouveau_gem_ioctl_pin(struct drm_device *, void *,
1135 extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *,
1137 extern int nouveau_gem_ioctl_tile(struct drm_device *, void *,
1139 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1141 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1143 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1147 int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1148 int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1150 #ifndef ioread32_native
1152 #define ioread16_native ioread16be
1153 #define iowrite16_native iowrite16be
1154 #define ioread32_native ioread32be
1155 #define iowrite32_native iowrite32be
1156 #else /* def __BIG_ENDIAN */
1157 #define ioread16_native ioread16
1158 #define iowrite16_native iowrite16
1159 #define ioread32_native ioread32
1160 #define iowrite32_native iowrite32
1161 #endif /* def __BIG_ENDIAN else */
1162 #endif /* !ioread32_native */
1164 /* channel control reg access */
1165 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1167 return ioread32_native(chan->user + reg);
1170 static inline void nvchan_wr32(struct nouveau_channel *chan,
1171 unsigned reg, u32 val)
1173 iowrite32_native(val, chan->user + reg);
1176 /* register access */
1177 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1179 struct drm_nouveau_private *dev_priv = dev->dev_private;
1180 return ioread32_native(dev_priv->mmio + reg);
1183 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1185 struct drm_nouveau_private *dev_priv = dev->dev_private;
1186 iowrite32_native(val, dev_priv->mmio + reg);
1189 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1191 struct drm_nouveau_private *dev_priv = dev->dev_private;
1192 return ioread8(dev_priv->mmio + reg);
1195 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1197 struct drm_nouveau_private *dev_priv = dev->dev_private;
1198 iowrite8(val, dev_priv->mmio + reg);
1201 #define nv_wait(reg, mask, val) \
1202 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1205 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1207 struct drm_nouveau_private *dev_priv = dev->dev_private;
1208 return ioread32_native(dev_priv->ramin + offset);
1211 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1213 struct drm_nouveau_private *dev_priv = dev->dev_private;
1214 iowrite32_native(val, dev_priv->ramin + offset);
1218 static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1221 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1224 static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1225 unsigned index, u32 val)
1227 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1232 * Argument d is (struct drm_device *).
1234 #define NV_PRINTK(level, d, fmt, arg...) \
1235 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1236 pci_name(d->pdev), ##arg)
1237 #ifndef NV_DEBUG_NOTRACE
1238 #define NV_DEBUG(d, fmt, arg...) do { \
1239 if (drm_debug & DRM_UT_DRIVER) { \
1240 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1244 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1245 if (drm_debug & DRM_UT_KMS) { \
1246 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1251 #define NV_DEBUG(d, fmt, arg...) do { \
1252 if (drm_debug & DRM_UT_DRIVER) \
1253 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1255 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1256 if (drm_debug & DRM_UT_KMS) \
1257 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1260 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1261 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1262 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1263 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1264 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1266 /* nouveau_reg_debug bitmask */
1268 NOUVEAU_REG_DEBUG_MC = 0x1,
1269 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1270 NOUVEAU_REG_DEBUG_FB = 0x4,
1271 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1272 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1273 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1274 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1275 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1276 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1277 NOUVEAU_REG_DEBUG_EVO = 0x200,
1280 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1281 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1282 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1286 nv_two_heads(struct drm_device *dev)
1288 struct drm_nouveau_private *dev_priv = dev->dev_private;
1289 const int impl = dev->pci_device & 0x0ff0;
1291 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1292 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1299 nv_gf4_disp_arch(struct drm_device *dev)
1301 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1305 nv_two_reg_pll(struct drm_device *dev)
1307 struct drm_nouveau_private *dev_priv = dev->dev_private;
1308 const int impl = dev->pci_device & 0x0ff0;
1310 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1315 #define NV50_NVSW 0x0000506e
1316 #define NV50_NVSW_DMA_SEMAPHORE 0x00000060
1317 #define NV50_NVSW_SEMAPHORE_OFFSET 0x00000064
1318 #define NV50_NVSW_SEMAPHORE_ACQUIRE 0x00000068
1319 #define NV50_NVSW_SEMAPHORE_RELEASE 0x0000006c
1320 #define NV50_NVSW_DMA_VBLSEM 0x0000018c
1321 #define NV50_NVSW_VBLSEM_OFFSET 0x00000400
1322 #define NV50_NVSW_VBLSEM_RELEASE_VALUE 0x00000404
1323 #define NV50_NVSW_VBLSEM_RELEASE 0x00000408
1325 #endif /* __NOUVEAU_DRV_H__ */