2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "nouveau@lists.freedesktop.org"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20120316"
35 #define DRIVER_MAJOR 1
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 0
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
50 struct list_head channels;
51 struct nouveau_vm *vm;
54 static inline struct nouveau_fpriv *
55 nouveau_fpriv(struct drm_file *file_priv)
57 return file_priv ? file_priv->driver_priv : NULL;
60 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
62 #include "nouveau_drm.h"
63 #include "nouveau_reg.h"
64 #include "nouveau_bios.h"
65 #include "nouveau_util.h"
69 #include "nouveau_vm.h"
71 #define MAX_NUM_DCB_ENTRIES 16
73 #define NOUVEAU_MAX_CHANNEL_NR 4096
74 #define NOUVEAU_MAX_TILE_NR 15
77 struct drm_device *dev;
79 struct nouveau_vma bar_vma;
80 struct nouveau_vma vma[2];
83 struct drm_mm_node *tag;
84 struct list_head regions;
92 struct nouveau_tile_reg {
98 struct drm_mm_node *tag_mem;
99 struct nouveau_fence *fence;
103 struct ttm_buffer_object bo;
104 struct ttm_placement placement;
107 u32 busy_placements[3];
108 struct ttm_bo_kmap_obj kmap;
109 struct list_head head;
111 /* protected by ttm_bo_reserve() */
112 struct drm_file *reserved_by;
113 struct list_head entry;
115 bool validate_mapped;
117 struct list_head vma_list;
122 struct nouveau_tile_reg *tile;
124 struct drm_gem_object *gem;
128 #define nouveau_bo_tile_layout(nvbo) \
129 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
131 static inline struct nouveau_bo *
132 nouveau_bo(struct ttm_buffer_object *bo)
134 return container_of(bo, struct nouveau_bo, bo);
137 static inline struct nouveau_bo *
138 nouveau_gem_object(struct drm_gem_object *gem)
140 return gem ? gem->driver_private : NULL;
143 /* TODO: submit equivalent to TTM generic API upstream? */
144 static inline void __iomem *
145 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
148 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
149 &nvbo->kmap, &is_iomem);
150 WARN_ON_ONCE(ioptr && !is_iomem);
155 NV_NFORCE = 0x10000000,
156 NV_NFORCE2 = 0x20000000
159 #define NVOBJ_ENGINE_SW 0
160 #define NVOBJ_ENGINE_GR 1
161 #define NVOBJ_ENGINE_CRYPT 2
162 #define NVOBJ_ENGINE_COPY0 3
163 #define NVOBJ_ENGINE_COPY1 4
164 #define NVOBJ_ENGINE_MPEG 5
165 #define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG
166 #define NVOBJ_ENGINE_BSP 6
167 #define NVOBJ_ENGINE_VP 7
168 #define NVOBJ_ENGINE_FENCE 14
169 #define NVOBJ_ENGINE_DISPLAY 15
170 #define NVOBJ_ENGINE_NR 16
172 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
173 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
174 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
175 #define NVOBJ_FLAG_VM (1 << 3)
176 #define NVOBJ_FLAG_VM_USER (1 << 4)
178 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
180 struct nouveau_gpuobj {
181 struct drm_device *dev;
182 struct kref refcount;
183 struct list_head list;
191 u32 pinst; /* PRAMIN BAR offset */
192 u32 cinst; /* Channel offset */
193 u64 vinst; /* VRAM address */
194 u64 linst; /* VM address */
199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
203 struct nouveau_page_flip_state {
204 struct list_head head;
205 struct drm_pending_vblank_event *event;
206 int crtc, bpp, pitch, x, y;
210 enum nouveau_channel_mutex_class {
211 NOUVEAU_UCHANNEL_MUTEX,
212 NOUVEAU_KCHANNEL_MUTEX
215 struct nouveau_channel {
216 struct drm_device *dev;
217 struct list_head list;
220 /* references to the channel data structure */
222 /* users of the hardware channel resources, the hardware
223 * context will be kicked off when it reaches zero. */
227 /* owner of this fifo */
228 struct drm_file *file_priv;
229 /* mapping of the fifo itself */
230 struct drm_local_map *map;
232 /* mapping of the regs controlling the fifo */
235 uint32_t user_get_hi;
238 /* DMA push buffer */
239 struct nouveau_gpuobj *pushbuf;
240 struct nouveau_bo *pushbuf_bo;
241 struct nouveau_vma pushbuf_vma;
242 uint64_t pushbuf_base;
244 /* Notifier memory */
245 struct nouveau_bo *notifier_bo;
246 struct nouveau_vma notifier_vma;
247 struct drm_mm notifier_heap;
250 struct nouveau_gpuobj *ramfc;
251 struct nouveau_gpuobj *cache;
254 /* Execution engine contexts */
255 void *engctx[NVOBJ_ENGINE_NR];
258 struct nouveau_vm *vm;
259 struct nouveau_gpuobj *vm_pd;
262 struct nouveau_gpuobj *ramin; /* Private instmem */
263 struct drm_mm ramin_heap; /* Private PRAMIN heap */
264 struct nouveau_ramht *ramht; /* Hash table */
266 /* GPU object info for stuff used in-kernel (mm_enabled) */
268 uint32_t vram_handle;
269 uint32_t gart_handle;
272 /* Push buffer state (only for drm's channel on !mm_enabled) */
278 /* access via pushbuf_bo */
286 uint32_t sw_subchannel[8];
291 struct drm_info_list info;
295 struct nouveau_exec_engine {
296 void (*destroy)(struct drm_device *, int engine);
297 int (*init)(struct drm_device *, int engine);
298 int (*fini)(struct drm_device *, int engine, bool suspend);
299 int (*context_new)(struct nouveau_channel *, int engine);
300 void (*context_del)(struct nouveau_channel *, int engine);
301 int (*object_new)(struct nouveau_channel *, int engine,
302 u32 handle, u16 class);
303 void (*set_tile_region)(struct drm_device *dev, int i);
304 void (*tlb_flush)(struct drm_device *, int engine);
307 struct nouveau_instmem_engine {
310 int (*init)(struct drm_device *dev);
311 void (*takedown)(struct drm_device *dev);
312 int (*suspend)(struct drm_device *dev);
313 void (*resume)(struct drm_device *dev);
315 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *,
316 u32 size, u32 align);
317 void (*put)(struct nouveau_gpuobj *);
318 int (*map)(struct nouveau_gpuobj *);
319 void (*unmap)(struct nouveau_gpuobj *);
321 void (*flush)(struct drm_device *);
324 struct nouveau_mc_engine {
325 int (*init)(struct drm_device *dev);
326 void (*takedown)(struct drm_device *dev);
329 struct nouveau_timer_engine {
330 int (*init)(struct drm_device *dev);
331 void (*takedown)(struct drm_device *dev);
332 uint64_t (*read)(struct drm_device *dev);
335 struct nouveau_fb_engine {
337 struct drm_mm tag_heap;
340 int (*init)(struct drm_device *dev);
341 void (*takedown)(struct drm_device *dev);
343 void (*init_tile_region)(struct drm_device *dev, int i,
344 uint32_t addr, uint32_t size,
345 uint32_t pitch, uint32_t flags);
346 void (*set_tile_region)(struct drm_device *dev, int i);
347 void (*free_tile_region)(struct drm_device *dev, int i);
350 struct nouveau_fifo_engine {
354 struct nouveau_gpuobj *playlist[2];
357 int (*init)(struct drm_device *);
358 void (*takedown)(struct drm_device *);
360 int (*create_context)(struct nouveau_channel *);
361 void (*destroy_context)(struct nouveau_channel *);
362 int (*load_context)(struct nouveau_channel *);
363 int (*unload_context)(struct drm_device *);
364 void (*tlb_flush)(struct drm_device *dev);
367 struct nouveau_display_engine {
369 int (*early_init)(struct drm_device *);
370 void (*late_takedown)(struct drm_device *);
371 int (*create)(struct drm_device *);
372 void (*destroy)(struct drm_device *);
373 int (*init)(struct drm_device *);
374 void (*fini)(struct drm_device *);
376 struct drm_property *dithering_mode;
377 struct drm_property *dithering_depth;
378 struct drm_property *underscan_property;
379 struct drm_property *underscan_hborder_property;
380 struct drm_property *underscan_vborder_property;
381 /* not really hue and saturation: */
382 struct drm_property *vibrant_hue_property;
383 struct drm_property *color_vibrance_property;
386 struct nouveau_gpio_engine {
388 struct list_head isr;
389 int (*init)(struct drm_device *);
390 void (*fini)(struct drm_device *);
391 int (*drive)(struct drm_device *, int line, int dir, int out);
392 int (*sense)(struct drm_device *, int line);
393 void (*irq_enable)(struct drm_device *, int line, bool);
396 struct nouveau_pm_voltage_level {
397 u32 voltage; /* microvolts */
401 struct nouveau_pm_voltage {
406 struct nouveau_pm_voltage_level *level;
410 /* Exclusive upper limits */
411 #define NV_MEM_CL_DDR2_MAX 8
412 #define NV_MEM_WR_DDR2_MAX 9
413 #define NV_MEM_CL_DDR3_MAX 17
414 #define NV_MEM_WR_DDR3_MAX 17
415 #define NV_MEM_CL_GDDR3_MAX 16
416 #define NV_MEM_WR_GDDR3_MAX 18
417 #define NV_MEM_CL_GDDR5_MAX 21
418 #define NV_MEM_WR_GDDR5_MAX 20
420 struct nouveau_pm_memtiming {
432 struct nouveau_pm_tbl_header {
439 struct nouveau_pm_tbl_entry {
445 u8 tRFC; /* Byte 5 */
447 u8 tRAS; /* Byte 7 */
454 u8 RAM_FT1; /* 14, a bitmask of random RAM features */
463 struct nouveau_pm_profile;
464 struct nouveau_pm_profile_func {
465 void (*destroy)(struct nouveau_pm_profile *);
466 void (*init)(struct nouveau_pm_profile *);
467 void (*fini)(struct nouveau_pm_profile *);
468 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
471 struct nouveau_pm_profile {
472 const struct nouveau_pm_profile_func *func;
473 struct list_head head;
477 #define NOUVEAU_PM_MAX_LEVEL 8
478 struct nouveau_pm_level {
479 struct nouveau_pm_profile profile;
480 struct device_attribute dev_attr;
484 struct nouveau_pm_memtiming timing;
495 u32 unka0; /* nva3:nvc0 */
496 u32 hub01; /* nvc0- */
497 u32 hub06; /* nvc0- */
498 u32 hub07; /* nvc0- */
500 u32 volt_min; /* microvolts */
505 struct nouveau_pm_temp_sensor_constants {
513 struct nouveau_pm_threshold_temp {
519 struct nouveau_pm_fan {
527 struct nouveau_pm_engine {
528 struct nouveau_pm_voltage voltage;
529 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
531 struct nouveau_pm_temp_sensor_constants sensor_constants;
532 struct nouveau_pm_threshold_temp threshold_temp;
533 struct nouveau_pm_fan fan;
535 struct nouveau_pm_profile *profile_ac;
536 struct nouveau_pm_profile *profile_dc;
537 struct nouveau_pm_profile *profile;
538 struct list_head profiles;
540 struct nouveau_pm_level boot;
541 struct nouveau_pm_level *cur;
543 struct device *hwmon;
544 struct notifier_block acpi_nb;
546 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
547 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
548 int (*clocks_set)(struct drm_device *, void *);
550 int (*voltage_get)(struct drm_device *);
551 int (*voltage_set)(struct drm_device *, int voltage);
552 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
553 int (*pwm_set)(struct drm_device *, int line, u32, u32);
554 int (*temp_get)(struct drm_device *);
557 struct nouveau_vram_engine {
558 struct nouveau_mm mm;
560 int (*init)(struct drm_device *);
561 void (*takedown)(struct drm_device *dev);
562 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
563 u32 type, struct nouveau_mem **);
564 void (*put)(struct drm_device *, struct nouveau_mem **);
566 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
569 struct nouveau_engine {
570 struct nouveau_instmem_engine instmem;
571 struct nouveau_mc_engine mc;
572 struct nouveau_timer_engine timer;
573 struct nouveau_fb_engine fb;
574 struct nouveau_fifo_engine fifo;
575 struct nouveau_display_engine display;
576 struct nouveau_gpio_engine gpio;
577 struct nouveau_pm_engine pm;
578 struct nouveau_vram_engine vram;
581 struct nouveau_pll_vals {
585 uint8_t N1, M1, N2, M2;
587 uint8_t M1, N1, M2, N2;
592 } __attribute__((packed));
599 enum nv04_fp_display_regs {
609 struct nv04_crtc_reg {
610 unsigned char MiscOutReg;
613 uint8_t Sequencer[5];
615 uint8_t Attribute[21];
616 unsigned char DAC[768];
626 uint32_t crtc_eng_ctrl;
629 uint32_t nv10_cursync;
630 struct nouveau_pll_vals pllvals;
631 uint32_t ramdac_gen_ctrl;
637 uint32_t tv_vsync_delay;
640 uint32_t tv_hsync_delay;
641 uint32_t tv_hsync_delay2;
642 uint32_t fp_horiz_regs[7];
643 uint32_t fp_vert_regs[7];
646 uint32_t dither_regs[6];
650 uint32_t fp_margin_color;
655 uint32_t ctv_regs[38];
658 struct nv04_output_reg {
663 struct nv04_mode_state {
664 struct nv04_crtc_reg crtc_reg[2];
669 enum nouveau_card_type {
681 struct drm_nouveau_private {
682 struct drm_device *dev;
685 /* the card type, takes NV_* as values */
686 enum nouveau_card_type card_type;
687 /* exact chipset, derived from NV_PMC_BOOT_0 */
694 spinlock_t ramin_lock;
698 bool ramin_available;
699 struct drm_mm ramin_heap;
700 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
701 struct list_head gpuobj_list;
702 struct list_head classes;
704 struct nouveau_bo *vga_ram;
706 /* interrupt handling */
707 void (*irq_handler[32])(struct drm_device *);
710 struct list_head vbl_waiting;
713 struct drm_global_reference mem_global_ref;
714 struct ttm_bo_global_ref bo_global_ref;
715 struct ttm_bo_device bdev;
716 atomic_t validate_sequence;
722 struct nouveau_bo *bo;
727 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
730 struct nouveau_engine engine;
731 struct nouveau_channel *channel;
733 /* For PFIFO and PGRAPH. */
734 spinlock_t context_switch_lock;
736 /* VM/PRAMIN flush, legacy PRAMIN aperture */
739 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
740 struct nouveau_ramht *ramht;
741 struct nouveau_gpuobj *ramfc;
742 struct nouveau_gpuobj *ramro;
744 uint32_t ramin_rsvd_vram;
748 NOUVEAU_GART_NONE = 0,
749 NOUVEAU_GART_AGP, /* AGP */
750 NOUVEAU_GART_PDMA, /* paged dma object */
751 NOUVEAU_GART_HW /* on-chip gart/vm */
757 struct ttm_backend_func *func;
764 struct nouveau_gpuobj *sg_ctxdma;
767 /* nv10-nv40 tiling regions */
769 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
773 /* VRAM/fb configuration */
775 NV_MEM_TYPE_UNKNOWN = 0,
788 uint64_t vram_sys_base;
791 uint64_t fb_available_size;
792 uint64_t fb_mappable_pages;
793 uint64_t fb_aper_free;
796 /* BAR control (NV50-) */
797 struct nouveau_vm *bar1_vm;
798 struct nouveau_vm *bar3_vm;
800 /* G8x/G9x virtual address space */
801 struct nouveau_vm *chan_vm;
805 struct list_head i2c_ports;
807 struct nv04_mode_state mode_reg;
808 struct nv04_mode_state saved_reg;
809 uint32_t saved_vga_font[4][16384];
811 uint32_t dac_users[4];
813 struct backlight_device *backlight;
816 struct dentry *channel_root;
819 struct nouveau_fbdev *nfbdev;
820 struct apertures_struct *apertures;
823 static inline struct drm_nouveau_private *
824 nouveau_private(struct drm_device *dev)
826 return dev->dev_private;
829 static inline struct drm_nouveau_private *
830 nouveau_bdev(struct ttm_bo_device *bd)
832 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
836 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
838 struct nouveau_bo *prev;
844 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
846 struct ttm_buffer_object *bo = &prev->bo;
855 extern int nouveau_modeset;
856 extern int nouveau_agpmode;
857 extern int nouveau_duallink;
858 extern int nouveau_uscript_lvds;
859 extern int nouveau_uscript_tmds;
860 extern int nouveau_vram_pushbuf;
861 extern int nouveau_vram_notify;
862 extern char *nouveau_vram_type;
863 extern int nouveau_fbpercrtc;
864 extern int nouveau_tv_disable;
865 extern char *nouveau_tv_norm;
866 extern int nouveau_reg_debug;
867 extern char *nouveau_vbios;
868 extern int nouveau_ignorelid;
869 extern int nouveau_nofbaccel;
870 extern int nouveau_noaccel;
871 extern int nouveau_force_post;
872 extern int nouveau_override_conntype;
873 extern char *nouveau_perflvl;
874 extern int nouveau_perflvl_wr;
875 extern int nouveau_msi;
876 extern int nouveau_ctxfw;
877 extern int nouveau_mxmdcb;
879 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
880 extern int nouveau_pci_resume(struct pci_dev *pdev);
882 /* nouveau_state.c */
883 extern int nouveau_open(struct drm_device *, struct drm_file *);
884 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
885 extern void nouveau_postclose(struct drm_device *, struct drm_file *);
886 extern int nouveau_load(struct drm_device *, unsigned long flags);
887 extern int nouveau_firstopen(struct drm_device *);
888 extern void nouveau_lastclose(struct drm_device *);
889 extern int nouveau_unload(struct drm_device *);
890 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
892 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
894 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
895 uint32_t reg, uint32_t mask, uint32_t val);
896 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
897 uint32_t reg, uint32_t mask, uint32_t val);
898 extern bool nouveau_wait_cb(struct drm_device *, u64 timeout,
899 bool (*cond)(void *), void *);
900 extern bool nouveau_wait_for_idle(struct drm_device *);
901 extern int nouveau_card_init(struct drm_device *);
904 extern int nouveau_mem_vram_init(struct drm_device *);
905 extern void nouveau_mem_vram_fini(struct drm_device *);
906 extern int nouveau_mem_gart_init(struct drm_device *);
907 extern void nouveau_mem_gart_fini(struct drm_device *);
908 extern int nouveau_mem_init_agp(struct drm_device *);
909 extern int nouveau_mem_reset_agp(struct drm_device *);
910 extern void nouveau_mem_close(struct drm_device *);
911 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
912 extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
913 struct nouveau_pm_memtiming *);
914 extern void nouveau_mem_timing_read(struct drm_device *,
915 struct nouveau_pm_memtiming *);
916 extern int nouveau_mem_vbios_type(struct drm_device *);
917 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
918 struct drm_device *dev, uint32_t addr, uint32_t size,
919 uint32_t pitch, uint32_t flags);
920 extern void nv10_mem_put_tile_region(struct drm_device *dev,
921 struct nouveau_tile_reg *tile,
922 struct nouveau_fence *fence);
923 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
924 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
926 /* nouveau_notifier.c */
927 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
928 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
929 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
930 int cout, uint32_t start, uint32_t end,
932 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
933 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
935 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
938 /* nouveau_channel.c */
939 extern struct drm_ioctl_desc nouveau_ioctls[];
940 extern int nouveau_max_ioctl;
941 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
942 extern int nouveau_channel_alloc(struct drm_device *dev,
943 struct nouveau_channel **chan,
944 struct drm_file *file_priv,
945 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
946 extern struct nouveau_channel *
947 nouveau_channel_get_unlocked(struct nouveau_channel *);
948 extern struct nouveau_channel *
949 nouveau_channel_get(struct drm_file *, int id);
950 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
951 extern void nouveau_channel_put(struct nouveau_channel **);
952 extern void nouveau_channel_ref(struct nouveau_channel *chan,
953 struct nouveau_channel **pchan);
954 extern void nouveau_channel_idle(struct nouveau_channel *chan);
956 /* nouveau_object.c */
957 #define NVOBJ_ENGINE_ADD(d, e, p) do { \
958 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
959 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
962 #define NVOBJ_ENGINE_DEL(d, e) do { \
963 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
964 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
967 #define NVOBJ_CLASS(d, c, e) do { \
968 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
973 #define NVOBJ_MTHD(d, c, m, e) do { \
974 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
979 extern int nouveau_gpuobj_early_init(struct drm_device *);
980 extern int nouveau_gpuobj_init(struct drm_device *);
981 extern void nouveau_gpuobj_takedown(struct drm_device *);
982 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
983 extern void nouveau_gpuobj_resume(struct drm_device *dev);
984 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
985 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
986 int (*exec)(struct nouveau_channel *,
987 u32 class, u32 mthd, u32 data));
988 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
989 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
990 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
991 uint32_t vram_h, uint32_t tt_h);
992 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
993 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
994 uint32_t size, int align, uint32_t flags,
995 struct nouveau_gpuobj **);
996 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
997 struct nouveau_gpuobj **);
998 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
1000 struct nouveau_gpuobj **);
1001 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
1002 uint64_t offset, uint64_t size, int access,
1003 int target, struct nouveau_gpuobj **);
1004 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
1005 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
1006 u64 size, int target, int access, u32 type,
1007 u32 comp, struct nouveau_gpuobj **pobj);
1008 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
1009 int class, u64 base, u64 size, int target,
1010 int access, u32 type, u32 comp);
1011 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
1013 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
1017 extern int nouveau_irq_init(struct drm_device *);
1018 extern void nouveau_irq_fini(struct drm_device *);
1019 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
1020 extern void nouveau_irq_register(struct drm_device *, int status_bit,
1021 void (*)(struct drm_device *));
1022 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
1023 extern void nouveau_irq_preinstall(struct drm_device *);
1024 extern int nouveau_irq_postinstall(struct drm_device *);
1025 extern void nouveau_irq_uninstall(struct drm_device *);
1027 /* nouveau_sgdma.c */
1028 extern int nouveau_sgdma_init(struct drm_device *);
1029 extern void nouveau_sgdma_takedown(struct drm_device *);
1030 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
1032 extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
1034 uint32_t page_flags,
1035 struct page *dummy_read_page);
1037 /* nouveau_debugfs.c */
1038 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
1039 extern int nouveau_debugfs_init(struct drm_minor *);
1040 extern void nouveau_debugfs_takedown(struct drm_minor *);
1041 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
1042 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
1045 nouveau_debugfs_init(struct drm_minor *minor)
1050 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
1055 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
1061 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
1067 extern void nouveau_dma_init(struct nouveau_channel *);
1068 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
1070 /* nouveau_acpi.c */
1071 #define ROM_BIOS_PAGE 4096
1072 #if defined(CONFIG_ACPI)
1073 void nouveau_register_dsm_handler(void);
1074 void nouveau_unregister_dsm_handler(void);
1075 void nouveau_switcheroo_optimus_dsm(void);
1076 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
1077 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
1078 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
1080 static inline void nouveau_register_dsm_handler(void) {}
1081 static inline void nouveau_unregister_dsm_handler(void) {}
1082 static inline void nouveau_switcheroo_optimus_dsm(void) {}
1083 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
1084 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
1085 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
1088 /* nouveau_backlight.c */
1089 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1090 extern int nouveau_backlight_init(struct drm_device *);
1091 extern void nouveau_backlight_exit(struct drm_device *);
1093 static inline int nouveau_backlight_init(struct drm_device *dev)
1098 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1101 /* nouveau_bios.c */
1102 extern int nouveau_bios_init(struct drm_device *);
1103 extern void nouveau_bios_takedown(struct drm_device *dev);
1104 extern int nouveau_run_vbios_init(struct drm_device *);
1105 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1106 struct dcb_entry *, int crtc);
1107 extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table);
1108 extern struct dcb_connector_table_entry *
1109 nouveau_bios_connector_entry(struct drm_device *, int index);
1110 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1111 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1113 extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1114 struct dcb_entry *, int crtc);
1115 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1116 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1117 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1118 bool *dl, bool *if_is_24bit);
1119 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1120 int head, int pxclk);
1121 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1122 enum LVDS_script, int pxclk);
1123 bool bios_encoder_match(struct dcb_entry *, u32 hash);
1126 int nouveau_mxm_init(struct drm_device *dev);
1127 void nouveau_mxm_fini(struct drm_device *dev);
1130 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1131 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1132 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1134 /* nouveau_hdmi.c */
1135 void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
1138 extern int nv04_fb_vram_init(struct drm_device *);
1139 extern int nv04_fb_init(struct drm_device *);
1140 extern void nv04_fb_takedown(struct drm_device *);
1143 extern int nv10_fb_vram_init(struct drm_device *dev);
1144 extern int nv1a_fb_vram_init(struct drm_device *dev);
1145 extern int nv10_fb_init(struct drm_device *);
1146 extern void nv10_fb_takedown(struct drm_device *);
1147 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1148 uint32_t addr, uint32_t size,
1149 uint32_t pitch, uint32_t flags);
1150 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1151 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1154 extern int nv20_fb_vram_init(struct drm_device *dev);
1155 extern int nv20_fb_init(struct drm_device *);
1156 extern void nv20_fb_takedown(struct drm_device *);
1157 extern void nv20_fb_init_tile_region(struct drm_device *dev, int i,
1158 uint32_t addr, uint32_t size,
1159 uint32_t pitch, uint32_t flags);
1160 extern void nv20_fb_set_tile_region(struct drm_device *dev, int i);
1161 extern void nv20_fb_free_tile_region(struct drm_device *dev, int i);
1164 extern int nv30_fb_init(struct drm_device *);
1165 extern void nv30_fb_takedown(struct drm_device *);
1166 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1167 uint32_t addr, uint32_t size,
1168 uint32_t pitch, uint32_t flags);
1169 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1172 extern int nv40_fb_vram_init(struct drm_device *dev);
1173 extern int nv40_fb_init(struct drm_device *);
1174 extern void nv40_fb_takedown(struct drm_device *);
1175 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1178 extern int nv50_fb_init(struct drm_device *);
1179 extern void nv50_fb_takedown(struct drm_device *);
1180 extern void nv50_fb_vm_trap(struct drm_device *, int display);
1183 extern int nvc0_fb_init(struct drm_device *);
1184 extern void nvc0_fb_takedown(struct drm_device *);
1187 extern int nv04_fifo_init(struct drm_device *);
1188 extern void nv04_fifo_fini(struct drm_device *);
1189 extern int nv04_fifo_create_context(struct nouveau_channel *);
1190 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1191 extern int nv04_fifo_load_context(struct nouveau_channel *);
1192 extern int nv04_fifo_unload_context(struct drm_device *);
1193 extern void nv04_fifo_isr(struct drm_device *);
1194 bool nv04_fifo_cache_pull(struct drm_device *, bool enable);
1197 extern int nv10_fifo_init(struct drm_device *);
1198 extern int nv10_fifo_create_context(struct nouveau_channel *);
1199 extern int nv10_fifo_load_context(struct nouveau_channel *);
1200 extern int nv10_fifo_unload_context(struct drm_device *);
1203 extern int nv40_fifo_init(struct drm_device *);
1204 extern int nv40_fifo_create_context(struct nouveau_channel *);
1205 extern int nv40_fifo_load_context(struct nouveau_channel *);
1206 extern int nv40_fifo_unload_context(struct drm_device *);
1209 extern int nv50_fifo_init(struct drm_device *);
1210 extern void nv50_fifo_takedown(struct drm_device *);
1211 extern int nv50_fifo_create_context(struct nouveau_channel *);
1212 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1213 extern int nv50_fifo_load_context(struct nouveau_channel *);
1214 extern int nv50_fifo_unload_context(struct drm_device *);
1215 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1218 extern int nvc0_fifo_init(struct drm_device *);
1219 extern void nvc0_fifo_takedown(struct drm_device *);
1220 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1221 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1222 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1223 extern int nvc0_fifo_unload_context(struct drm_device *);
1226 extern int nve0_fifo_init(struct drm_device *);
1227 extern void nve0_fifo_takedown(struct drm_device *);
1228 extern int nve0_fifo_create_context(struct nouveau_channel *);
1229 extern void nve0_fifo_destroy_context(struct nouveau_channel *);
1230 extern int nve0_fifo_unload_context(struct drm_device *);
1233 extern int nv04_graph_create(struct drm_device *);
1234 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
1235 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1236 u32 class, u32 mthd, u32 data);
1237 extern struct nouveau_bitfield nv04_graph_nsource[];
1240 extern int nv10_graph_create(struct drm_device *);
1241 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1242 extern struct nouveau_bitfield nv10_graph_intr[];
1243 extern struct nouveau_bitfield nv10_graph_nstatus[];
1246 extern int nv20_graph_create(struct drm_device *);
1249 extern int nv40_graph_create(struct drm_device *);
1250 extern void nv40_grctx_init(struct drm_device *, u32 *size);
1251 extern void nv40_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
1254 extern int nv50_graph_create(struct drm_device *);
1255 extern struct nouveau_enum nv50_data_error_names[];
1256 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
1257 extern int nv50_grctx_init(struct drm_device *, u32 *, u32, u32 *, u32 *);
1258 extern void nv50_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
1261 extern int nvc0_graph_create(struct drm_device *);
1262 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
1265 extern int nve0_graph_create(struct drm_device *);
1268 extern int nv84_crypt_create(struct drm_device *);
1271 extern int nv98_crypt_create(struct drm_device *dev);
1274 extern int nva3_copy_create(struct drm_device *dev);
1277 extern int nvc0_copy_create(struct drm_device *dev, int engine);
1280 extern int nv31_mpeg_create(struct drm_device *dev);
1283 extern int nv50_mpeg_create(struct drm_device *dev);
1287 extern int nv84_bsp_create(struct drm_device *dev);
1291 extern int nv84_vp_create(struct drm_device *dev);
1294 extern int nv98_ppp_create(struct drm_device *dev);
1296 /* nv04_instmem.c */
1297 extern int nv04_instmem_init(struct drm_device *);
1298 extern void nv04_instmem_takedown(struct drm_device *);
1299 extern int nv04_instmem_suspend(struct drm_device *);
1300 extern void nv04_instmem_resume(struct drm_device *);
1301 extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1302 u32 size, u32 align);
1303 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1304 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1305 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1306 extern void nv04_instmem_flush(struct drm_device *);
1308 /* nv50_instmem.c */
1309 extern int nv50_instmem_init(struct drm_device *);
1310 extern void nv50_instmem_takedown(struct drm_device *);
1311 extern int nv50_instmem_suspend(struct drm_device *);
1312 extern void nv50_instmem_resume(struct drm_device *);
1313 extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1314 u32 size, u32 align);
1315 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1316 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1317 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1318 extern void nv50_instmem_flush(struct drm_device *);
1319 extern void nv84_instmem_flush(struct drm_device *);
1321 /* nvc0_instmem.c */
1322 extern int nvc0_instmem_init(struct drm_device *);
1323 extern void nvc0_instmem_takedown(struct drm_device *);
1324 extern int nvc0_instmem_suspend(struct drm_device *);
1325 extern void nvc0_instmem_resume(struct drm_device *);
1328 extern int nv04_mc_init(struct drm_device *);
1329 extern void nv04_mc_takedown(struct drm_device *);
1332 extern int nv40_mc_init(struct drm_device *);
1333 extern void nv40_mc_takedown(struct drm_device *);
1336 extern int nv50_mc_init(struct drm_device *);
1337 extern void nv50_mc_takedown(struct drm_device *);
1340 extern int nv04_timer_init(struct drm_device *);
1341 extern uint64_t nv04_timer_read(struct drm_device *);
1342 extern void nv04_timer_takedown(struct drm_device *);
1344 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1348 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1349 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1350 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1351 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1352 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1355 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1356 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1357 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1359 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1360 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1363 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1364 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1367 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1369 /* nv04_display.c */
1370 extern int nv04_display_early_init(struct drm_device *);
1371 extern void nv04_display_late_takedown(struct drm_device *);
1372 extern int nv04_display_create(struct drm_device *);
1373 extern void nv04_display_destroy(struct drm_device *);
1374 extern int nv04_display_init(struct drm_device *);
1375 extern void nv04_display_fini(struct drm_device *);
1377 /* nvd0_display.c */
1378 extern int nvd0_display_create(struct drm_device *);
1379 extern void nvd0_display_destroy(struct drm_device *);
1380 extern int nvd0_display_init(struct drm_device *);
1381 extern void nvd0_display_fini(struct drm_device *);
1382 struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
1383 void nvd0_display_flip_stop(struct drm_crtc *);
1384 int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
1385 struct nouveau_channel *, u32 swap_interval);
1388 extern int nv04_crtc_create(struct drm_device *, int index);
1391 extern struct ttm_bo_driver nouveau_bo_driver;
1392 extern int nouveau_bo_new(struct drm_device *, int size, int align,
1393 uint32_t flags, uint32_t tile_mode,
1394 uint32_t tile_flags,
1395 struct sg_table *sg,
1396 struct nouveau_bo **);
1397 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1398 extern int nouveau_bo_unpin(struct nouveau_bo *);
1399 extern int nouveau_bo_map(struct nouveau_bo *);
1400 extern void nouveau_bo_unmap(struct nouveau_bo *);
1401 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1403 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1404 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1405 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1406 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1407 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1408 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1409 bool no_wait_reserve, bool no_wait_gpu);
1411 extern struct nouveau_vma *
1412 nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
1413 extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
1414 struct nouveau_vma *);
1415 extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
1418 extern int nouveau_gem_new(struct drm_device *, int size, int align,
1419 uint32_t domain, uint32_t tile_mode,
1420 uint32_t tile_flags, struct nouveau_bo **);
1421 extern int nouveau_gem_object_new(struct drm_gem_object *);
1422 extern void nouveau_gem_object_del(struct drm_gem_object *);
1423 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
1424 extern void nouveau_gem_object_close(struct drm_gem_object *,
1426 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1428 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1430 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1432 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1434 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1437 extern struct dma_buf *nouveau_gem_prime_export(struct drm_device *dev,
1438 struct drm_gem_object *obj, int flags);
1439 extern struct drm_gem_object *nouveau_gem_prime_import(struct drm_device *dev,
1440 struct dma_buf *dma_buf);
1442 /* nouveau_display.c */
1443 int nouveau_display_create(struct drm_device *dev);
1444 void nouveau_display_destroy(struct drm_device *dev);
1445 int nouveau_display_init(struct drm_device *dev);
1446 void nouveau_display_fini(struct drm_device *dev);
1447 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1448 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1449 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1450 struct drm_pending_vblank_event *event);
1451 int nouveau_finish_page_flip(struct nouveau_channel *,
1452 struct nouveau_page_flip_state *);
1453 int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
1454 struct drm_mode_create_dumb *args);
1455 int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
1456 uint32_t handle, uint64_t *offset);
1457 int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
1461 int nv10_gpio_init(struct drm_device *dev);
1462 void nv10_gpio_fini(struct drm_device *dev);
1463 int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1464 int nv10_gpio_sense(struct drm_device *dev, int line);
1465 void nv10_gpio_irq_enable(struct drm_device *, int line, bool on);
1468 int nv50_gpio_init(struct drm_device *dev);
1469 void nv50_gpio_fini(struct drm_device *dev);
1470 int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1471 int nv50_gpio_sense(struct drm_device *dev, int line);
1472 void nv50_gpio_irq_enable(struct drm_device *, int line, bool on);
1473 int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1474 int nvd0_gpio_sense(struct drm_device *dev, int line);
1477 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1478 int *N1, int *M1, int *N2, int *M2, int *P);
1479 int nva3_calc_pll(struct drm_device *, struct pll_lims *,
1480 int clk, int *N, int *fN, int *M, int *P);
1482 #ifndef ioread32_native
1484 #define ioread16_native ioread16be
1485 #define iowrite16_native iowrite16be
1486 #define ioread32_native ioread32be
1487 #define iowrite32_native iowrite32be
1488 #else /* def __BIG_ENDIAN */
1489 #define ioread16_native ioread16
1490 #define iowrite16_native iowrite16
1491 #define ioread32_native ioread32
1492 #define iowrite32_native iowrite32
1493 #endif /* def __BIG_ENDIAN else */
1494 #endif /* !ioread32_native */
1496 /* channel control reg access */
1497 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1499 return ioread32_native(chan->user + reg);
1502 static inline void nvchan_wr32(struct nouveau_channel *chan,
1503 unsigned reg, u32 val)
1505 iowrite32_native(val, chan->user + reg);
1508 /* register access */
1509 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1511 struct drm_nouveau_private *dev_priv = dev->dev_private;
1512 return ioread32_native(dev_priv->mmio + reg);
1515 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1517 struct drm_nouveau_private *dev_priv = dev->dev_private;
1518 iowrite32_native(val, dev_priv->mmio + reg);
1521 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1523 u32 tmp = nv_rd32(dev, reg);
1524 nv_wr32(dev, reg, (tmp & ~mask) | val);
1528 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1530 struct drm_nouveau_private *dev_priv = dev->dev_private;
1531 return ioread8(dev_priv->mmio + reg);
1534 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1536 struct drm_nouveau_private *dev_priv = dev->dev_private;
1537 iowrite8(val, dev_priv->mmio + reg);
1540 #define nv_wait(dev, reg, mask, val) \
1541 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1542 #define nv_wait_ne(dev, reg, mask, val) \
1543 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1544 #define nv_wait_cb(dev, func, data) \
1545 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
1548 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1550 struct drm_nouveau_private *dev_priv = dev->dev_private;
1551 return ioread32_native(dev_priv->ramin + offset);
1554 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1556 struct drm_nouveau_private *dev_priv = dev->dev_private;
1557 iowrite32_native(val, dev_priv->ramin + offset);
1561 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1562 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1566 * Argument d is (struct drm_device *).
1568 #define NV_PRINTK(level, d, fmt, arg...) \
1569 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1570 pci_name(d->pdev), ##arg)
1571 #ifndef NV_DEBUG_NOTRACE
1572 #define NV_DEBUG(d, fmt, arg...) do { \
1573 if (drm_debug & DRM_UT_DRIVER) { \
1574 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1578 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1579 if (drm_debug & DRM_UT_KMS) { \
1580 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1585 #define NV_DEBUG(d, fmt, arg...) do { \
1586 if (drm_debug & DRM_UT_DRIVER) \
1587 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1589 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1590 if (drm_debug & DRM_UT_KMS) \
1591 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1594 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1595 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1596 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1597 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1598 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1599 #define NV_WARNONCE(d, fmt, arg...) do { \
1600 static int _warned = 0; \
1602 NV_WARN(d, fmt, ##arg); \
1607 /* nouveau_reg_debug bitmask */
1609 NOUVEAU_REG_DEBUG_MC = 0x1,
1610 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1611 NOUVEAU_REG_DEBUG_FB = 0x4,
1612 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1613 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1614 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1615 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1616 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1617 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1618 NOUVEAU_REG_DEBUG_EVO = 0x200,
1619 NOUVEAU_REG_DEBUG_AUXCH = 0x400
1622 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1623 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1624 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1628 nv_two_heads(struct drm_device *dev)
1630 struct drm_nouveau_private *dev_priv = dev->dev_private;
1631 const int impl = dev->pci_device & 0x0ff0;
1633 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1634 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1641 nv_gf4_disp_arch(struct drm_device *dev)
1643 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1647 nv_two_reg_pll(struct drm_device *dev)
1649 struct drm_nouveau_private *dev_priv = dev->dev_private;
1650 const int impl = dev->pci_device & 0x0ff0;
1652 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1658 nv_match_device(struct drm_device *dev, unsigned device,
1659 unsigned sub_vendor, unsigned sub_device)
1661 return dev->pdev->device == device &&
1662 dev->pdev->subsystem_vendor == sub_vendor &&
1663 dev->pdev->subsystem_device == sub_device;
1666 static inline void *
1667 nv_engine(struct drm_device *dev, int engine)
1669 struct drm_nouveau_private *dev_priv = dev->dev_private;
1670 return (void *)dev_priv->eng[engine];
1673 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1674 * helpful to determine a number of other hardware features
1677 nv44_graph_class(struct drm_device *dev)
1679 struct drm_nouveau_private *dev_priv = dev->dev_private;
1681 if ((dev_priv->chipset & 0xf0) == 0x60)
1684 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1687 /* memory type/access flags, do not match hardware values */
1688 #define NV_MEM_ACCESS_RO 1
1689 #define NV_MEM_ACCESS_WO 2
1690 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1691 #define NV_MEM_ACCESS_SYS 4
1692 #define NV_MEM_ACCESS_VM 8
1693 #define NV_MEM_ACCESS_NOSNOOP 16
1695 #define NV_MEM_TARGET_VRAM 0
1696 #define NV_MEM_TARGET_PCI 1
1697 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1698 #define NV_MEM_TARGET_VM 3
1699 #define NV_MEM_TARGET_GART 4
1701 #define NV_MEM_TYPE_VM 0x7f
1702 #define NV_MEM_COMP_VM 0x03
1705 #define NV01_SUBCHAN_OBJECT 0x00000000
1706 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
1707 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
1708 #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
1709 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
1710 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
1711 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
1712 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
1713 #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
1714 #define NV84_SUBCHAN_NOTIFY_INTR 0x00000020
1715 #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
1716 #define NV10_SUBCHAN_REF_CNT 0x00000050
1717 #define NVSW_SUBCHAN_PAGE_FLIP 0x00000054
1718 #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
1719 #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
1720 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
1721 #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
1722 #define NV40_SUBCHAN_YIELD 0x00000080
1724 /* NV_SW object class */
1725 #define NV_SW 0x0000506e
1726 #define NV_SW_DMA_VBLSEM 0x0000018c
1727 #define NV_SW_VBLSEM_OFFSET 0x00000400
1728 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1729 #define NV_SW_VBLSEM_RELEASE 0x00000408
1730 #define NV_SW_PAGE_FLIP 0x00000500
1732 #endif /* __NOUVEAU_DRV_H__ */