2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
79 struct ttm_bo_kmap_obj kmap;
80 struct list_head head;
82 /* protected by ttm_bo_reserve() */
83 struct drm_file *reserved_by;
84 struct list_head entry;
88 struct nouveau_channel *channel;
95 struct nouveau_tile_reg *tile;
97 struct drm_gem_object *gem;
98 struct drm_file *cpu_filp;
102 static inline struct nouveau_bo *
103 nouveau_bo(struct ttm_buffer_object *bo)
105 return container_of(bo, struct nouveau_bo, bo);
108 static inline struct nouveau_bo *
109 nouveau_gem_object(struct drm_gem_object *gem)
111 return gem ? gem->driver_private : NULL;
114 /* TODO: submit equivalent to TTM generic API upstream? */
115 static inline void __iomem *
116 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
119 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
120 &nvbo->kmap, &is_iomem);
121 WARN_ON_ONCE(ioptr && !is_iomem);
126 struct mem_block *next;
127 struct mem_block *prev;
130 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
134 NV_NFORCE = 0x10000000,
135 NV_NFORCE2 = 0x20000000
138 #define NVOBJ_ENGINE_SW 0
139 #define NVOBJ_ENGINE_GR 1
140 #define NVOBJ_ENGINE_DISPLAY 2
141 #define NVOBJ_ENGINE_INT 0xdeadbeef
143 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
144 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
145 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
146 #define NVOBJ_FLAG_FAKE (1 << 3)
147 struct nouveau_gpuobj {
148 struct list_head list;
150 struct nouveau_channel *im_channel;
151 struct mem_block *im_pramin;
152 struct nouveau_bo *im_backing;
153 uint32_t im_backing_start;
154 uint32_t *im_backing_suspend;
163 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
167 struct nouveau_gpuobj_ref {
168 struct list_head list;
170 struct nouveau_gpuobj *gpuobj;
173 struct nouveau_channel *channel;
177 struct nouveau_channel {
178 struct drm_device *dev;
181 /* owner of this fifo */
182 struct drm_file *file_priv;
183 /* mapping of the fifo itself */
184 struct drm_local_map *map;
186 /* mapping of the regs controling the fifo */
193 /* lock protects the pending list only */
195 struct list_head pending;
197 uint32_t sequence_ack;
198 uint32_t last_sequence_irq;
201 /* DMA push buffer */
202 struct nouveau_gpuobj_ref *pushbuf;
203 struct nouveau_bo *pushbuf_bo;
204 uint32_t pushbuf_base;
206 /* Notifier memory */
207 struct nouveau_bo *notifier_bo;
208 struct mem_block *notifier_heap;
211 struct nouveau_gpuobj_ref *ramfc;
212 struct nouveau_gpuobj_ref *cache;
215 /* XXX may be merge 2 pointers as private data ??? */
216 struct nouveau_gpuobj_ref *ramin_grctx;
220 struct nouveau_gpuobj *vm_pd;
221 struct nouveau_gpuobj_ref *vm_gart_pt;
222 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
225 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
226 struct mem_block *ramin_heap; /* Private PRAMIN heap */
227 struct nouveau_gpuobj_ref *ramht; /* Hash table */
228 struct list_head ramht_refs; /* Objects referenced by RAMHT */
230 /* GPU object info for stuff used in-kernel (mm_enabled) */
232 uint32_t vram_handle;
233 uint32_t gart_handle;
236 /* Push buffer state (only for drm's channel on !mm_enabled) */
242 /* access via pushbuf_bo */
250 uint32_t sw_subchannel[8];
253 struct nouveau_gpuobj *vblsem;
254 uint32_t vblsem_offset;
255 uint32_t vblsem_rval;
256 struct list_head vbl_wait;
262 struct drm_info_list info;
266 struct nouveau_instmem_engine {
269 int (*init)(struct drm_device *dev);
270 void (*takedown)(struct drm_device *dev);
271 int (*suspend)(struct drm_device *dev);
272 void (*resume)(struct drm_device *dev);
274 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
276 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
277 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
278 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
279 void (*prepare_access)(struct drm_device *, bool write);
280 void (*finish_access)(struct drm_device *);
283 struct nouveau_mc_engine {
284 int (*init)(struct drm_device *dev);
285 void (*takedown)(struct drm_device *dev);
288 struct nouveau_timer_engine {
289 int (*init)(struct drm_device *dev);
290 void (*takedown)(struct drm_device *dev);
291 uint64_t (*read)(struct drm_device *dev);
294 struct nouveau_fb_engine {
297 int (*init)(struct drm_device *dev);
298 void (*takedown)(struct drm_device *dev);
300 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
301 uint32_t size, uint32_t pitch);
304 struct nouveau_fifo_engine {
309 int (*init)(struct drm_device *);
310 void (*takedown)(struct drm_device *);
312 void (*disable)(struct drm_device *);
313 void (*enable)(struct drm_device *);
314 bool (*reassign)(struct drm_device *, bool enable);
315 bool (*cache_flush)(struct drm_device *dev);
316 bool (*cache_pull)(struct drm_device *dev, bool enable);
318 int (*channel_id)(struct drm_device *);
320 int (*create_context)(struct nouveau_channel *);
321 void (*destroy_context)(struct nouveau_channel *);
322 int (*load_context)(struct nouveau_channel *);
323 int (*unload_context)(struct drm_device *);
326 struct nouveau_pgraph_object_method {
328 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
332 struct nouveau_pgraph_object_class {
335 struct nouveau_pgraph_object_method *methods;
338 struct nouveau_pgraph_engine {
339 struct nouveau_pgraph_object_class *grclass;
345 int (*init)(struct drm_device *);
346 void (*takedown)(struct drm_device *);
348 void (*fifo_access)(struct drm_device *, bool);
350 struct nouveau_channel *(*channel)(struct drm_device *);
351 int (*create_context)(struct nouveau_channel *);
352 void (*destroy_context)(struct nouveau_channel *);
353 int (*load_context)(struct nouveau_channel *);
354 int (*unload_context)(struct drm_device *);
356 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
357 uint32_t size, uint32_t pitch);
360 struct nouveau_engine {
361 struct nouveau_instmem_engine instmem;
362 struct nouveau_mc_engine mc;
363 struct nouveau_timer_engine timer;
364 struct nouveau_fb_engine fb;
365 struct nouveau_pgraph_engine graph;
366 struct nouveau_fifo_engine fifo;
369 struct nouveau_pll_vals {
373 uint8_t N1, M1, N2, M2;
375 uint8_t M1, N1, M2, N2;
380 } __attribute__((packed));
387 enum nv04_fp_display_regs {
397 struct nv04_crtc_reg {
398 unsigned char MiscOutReg; /* */
401 uint8_t Sequencer[5];
403 uint8_t Attribute[21];
404 unsigned char DAC[768]; /* Internal Colorlookuptable */
414 uint32_t crtc_eng_ctrl;
417 uint32_t nv10_cursync;
418 struct nouveau_pll_vals pllvals;
419 uint32_t ramdac_gen_ctrl;
425 uint32_t tv_vsync_delay;
428 uint32_t tv_hsync_delay;
429 uint32_t tv_hsync_delay2;
430 uint32_t fp_horiz_regs[7];
431 uint32_t fp_vert_regs[7];
434 uint32_t dither_regs[6];
438 uint32_t fp_margin_color;
443 uint32_t ctv_regs[38];
446 struct nv04_output_reg {
451 struct nv04_mode_state {
479 uint32_t cursorConfig;
488 struct nv04_crtc_reg crtc_reg[2];
491 enum nouveau_card_type {
500 struct drm_nouveau_private {
501 struct drm_device *dev;
503 NOUVEAU_CARD_INIT_DOWN,
504 NOUVEAU_CARD_INIT_DONE,
505 NOUVEAU_CARD_INIT_FAILED
508 /* the card type, takes NV_* as values */
509 enum nouveau_card_type card_type;
510 /* exact chipset, derived from NV_PMC_BOOT_0 */
518 struct nouveau_bo *vga_ram;
520 struct workqueue_struct *wq;
521 struct work_struct irq_work;
523 struct list_head vbl_waiting;
526 struct ttm_global_reference mem_global_ref;
527 struct ttm_bo_global_ref bo_global_ref;
528 struct ttm_bo_device bdev;
529 spinlock_t bo_list_lock;
530 struct list_head bo_list;
531 atomic_t validate_sequence;
534 struct fb_info *fbdev_info;
536 int fifo_alloc_count;
537 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
539 struct nouveau_engine engine;
540 struct nouveau_channel *channel;
542 /* For PFIFO and PGRAPH. */
543 spinlock_t context_switch_lock;
545 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
546 struct nouveau_gpuobj *ramht;
547 uint32_t ramin_rsvd_vram;
548 uint32_t ramht_offset;
551 uint32_t ramfc_offset;
553 uint32_t ramro_offset;
556 /* base physical adresses */
558 uint64_t fb_available_size;
559 uint64_t fb_mappable_pages;
560 uint64_t fb_aper_free;
564 NOUVEAU_GART_NONE = 0,
572 struct nouveau_gpuobj *sg_ctxdma;
573 struct page *sg_dummy_page;
574 dma_addr_t sg_dummy_bus;
577 struct drm_ttm_backend *sg_be;
578 unsigned long sg_handle;
581 /* nv10-nv40 tiling regions */
583 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
587 /* G8x/G9x virtual address space */
588 uint64_t vm_gart_base;
589 uint64_t vm_gart_size;
590 uint64_t vm_vram_base;
591 uint64_t vm_vram_size;
593 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
595 uint64_t vram_sys_base;
597 /* the mtrr covering the FB */
600 struct mem_block *ramin_heap;
602 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
603 uint32_t ctx_table_size;
604 struct nouveau_gpuobj_ref *ctx_table;
606 struct list_head gpuobj_list;
610 struct nv04_mode_state mode_reg;
611 struct nv04_mode_state saved_reg;
612 uint32_t saved_vga_font[4][16384];
614 uint32_t dac_users[4];
616 struct nouveau_suspend_resume {
618 uint32_t graph_ctx_control;
619 uint32_t graph_state;
620 uint32_t *ramin_copy;
624 struct backlight_device *backlight;
626 struct nouveau_channel *evo;
629 struct dentry *channel_root;
633 static inline struct drm_nouveau_private *
634 nouveau_bdev(struct ttm_bo_device *bd)
636 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
640 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
642 struct nouveau_bo *prev;
648 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
650 struct ttm_buffer_object *bo = &prev->bo;
658 #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
659 struct drm_nouveau_private *nv = dev->dev_private; \
660 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
661 NV_ERROR(dev, "called without init\n"); \
666 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
667 struct drm_nouveau_private *nv = dev->dev_private; \
668 if (!nouveau_channel_owner(dev, (cl), (id))) { \
669 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
670 DRM_CURRENTPID, (id)); \
673 (ch) = nv->fifos[(id)]; \
677 extern int nouveau_noagp;
678 extern int nouveau_duallink;
679 extern int nouveau_uscript_lvds;
680 extern int nouveau_uscript_tmds;
681 extern int nouveau_vram_pushbuf;
682 extern int nouveau_vram_notify;
683 extern int nouveau_fbpercrtc;
684 extern int nouveau_tv_disable;
685 extern char *nouveau_tv_norm;
686 extern int nouveau_reg_debug;
687 extern char *nouveau_vbios;
688 extern int nouveau_ctxfw;
689 extern int nouveau_ignorelid;
690 extern int nouveau_nofbaccel;
691 extern int nouveau_noaccel;
692 extern int nouveau_override_conntype;
694 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
695 extern int nouveau_pci_resume(struct pci_dev *pdev);
697 /* nouveau_state.c */
698 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
699 extern int nouveau_load(struct drm_device *, unsigned long flags);
700 extern int nouveau_firstopen(struct drm_device *);
701 extern void nouveau_lastclose(struct drm_device *);
702 extern int nouveau_unload(struct drm_device *);
703 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
705 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
707 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
708 uint32_t reg, uint32_t mask, uint32_t val);
709 extern bool nouveau_wait_for_idle(struct drm_device *);
710 extern int nouveau_card_init(struct drm_device *);
713 extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
715 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
716 uint64_t size, int align2,
717 struct drm_file *, int tail);
718 extern void nouveau_mem_takedown(struct mem_block **heap);
719 extern void nouveau_mem_free_block(struct mem_block *);
720 extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
721 extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
722 extern int nouveau_mem_init(struct drm_device *);
723 extern int nouveau_mem_init_agp(struct drm_device *);
724 extern void nouveau_mem_close(struct drm_device *);
725 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
729 extern void nv10_mem_expire_tiling(struct drm_device *dev,
730 struct nouveau_tile_reg *tile,
731 struct nouveau_fence *fence);
732 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
733 uint32_t size, uint32_t flags,
735 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
738 /* nouveau_notifier.c */
739 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
740 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
741 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
742 int cout, uint32_t *offset);
743 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
744 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
746 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
749 /* nouveau_channel.c */
750 extern struct drm_ioctl_desc nouveau_ioctls[];
751 extern int nouveau_max_ioctl;
752 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
753 extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
755 extern int nouveau_channel_alloc(struct drm_device *dev,
756 struct nouveau_channel **chan,
757 struct drm_file *file_priv,
758 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
759 extern void nouveau_channel_free(struct nouveau_channel *);
761 /* nouveau_object.c */
762 extern int nouveau_gpuobj_early_init(struct drm_device *);
763 extern int nouveau_gpuobj_init(struct drm_device *);
764 extern void nouveau_gpuobj_takedown(struct drm_device *);
765 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
766 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
767 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
768 extern void nouveau_gpuobj_resume(struct drm_device *dev);
769 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
770 uint32_t vram_h, uint32_t tt_h);
771 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
772 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
773 uint32_t size, int align, uint32_t flags,
774 struct nouveau_gpuobj **);
775 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
776 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
777 uint32_t handle, struct nouveau_gpuobj *,
778 struct nouveau_gpuobj_ref **);
779 extern int nouveau_gpuobj_ref_del(struct drm_device *,
780 struct nouveau_gpuobj_ref **);
781 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
782 struct nouveau_gpuobj_ref **ref_ret);
783 extern int nouveau_gpuobj_new_ref(struct drm_device *,
784 struct nouveau_channel *alloc_chan,
785 struct nouveau_channel *ref_chan,
786 uint32_t handle, uint32_t size, int align,
787 uint32_t flags, struct nouveau_gpuobj_ref **);
788 extern int nouveau_gpuobj_new_fake(struct drm_device *,
789 uint32_t p_offset, uint32_t b_offset,
790 uint32_t size, uint32_t flags,
791 struct nouveau_gpuobj **,
792 struct nouveau_gpuobj_ref**);
793 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
794 uint64_t offset, uint64_t size, int access,
795 int target, struct nouveau_gpuobj **);
796 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
797 uint64_t offset, uint64_t size,
798 int access, struct nouveau_gpuobj **,
800 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
801 struct nouveau_gpuobj **);
802 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
803 struct nouveau_gpuobj **);
804 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
806 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
810 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
811 extern void nouveau_irq_preinstall(struct drm_device *);
812 extern int nouveau_irq_postinstall(struct drm_device *);
813 extern void nouveau_irq_uninstall(struct drm_device *);
815 /* nouveau_sgdma.c */
816 extern int nouveau_sgdma_init(struct drm_device *);
817 extern void nouveau_sgdma_takedown(struct drm_device *);
818 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
820 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
822 /* nouveau_debugfs.c */
823 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
824 extern int nouveau_debugfs_init(struct drm_minor *);
825 extern void nouveau_debugfs_takedown(struct drm_minor *);
826 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
827 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
830 nouveau_debugfs_init(struct drm_minor *minor)
835 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
840 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
846 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
852 extern void nouveau_dma_pre_init(struct nouveau_channel *);
853 extern int nouveau_dma_init(struct nouveau_channel *);
854 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
857 #if defined(CONFIG_ACPI)
858 void nouveau_register_dsm_handler(void);
859 void nouveau_unregister_dsm_handler(void);
861 static inline void nouveau_register_dsm_handler(void) {}
862 static inline void nouveau_unregister_dsm_handler(void) {}
865 /* nouveau_backlight.c */
866 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
867 extern int nouveau_backlight_init(struct drm_device *);
868 extern void nouveau_backlight_exit(struct drm_device *);
870 static inline int nouveau_backlight_init(struct drm_device *dev)
875 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
879 extern int nouveau_bios_init(struct drm_device *);
880 extern void nouveau_bios_takedown(struct drm_device *dev);
881 extern int nouveau_run_vbios_init(struct drm_device *);
882 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
884 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
886 extern struct dcb_connector_table_entry *
887 nouveau_bios_connector_entry(struct drm_device *, int index);
888 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
890 extern int nouveau_bios_run_display_table(struct drm_device *,
892 uint32_t script, int pxclk);
893 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
895 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
896 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
897 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
898 bool *dl, bool *if_is_24bit);
899 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
900 int head, int pxclk);
901 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
902 enum LVDS_script, int pxclk);
905 int nouveau_ttm_global_init(struct drm_nouveau_private *);
906 void nouveau_ttm_global_release(struct drm_nouveau_private *);
907 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
910 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
911 uint8_t *data, int data_nr);
912 bool nouveau_dp_detect(struct drm_encoder *);
913 bool nouveau_dp_link_train(struct drm_encoder *);
916 extern int nv04_fb_init(struct drm_device *);
917 extern void nv04_fb_takedown(struct drm_device *);
920 extern int nv10_fb_init(struct drm_device *);
921 extern void nv10_fb_takedown(struct drm_device *);
922 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
926 extern int nv40_fb_init(struct drm_device *);
927 extern void nv40_fb_takedown(struct drm_device *);
928 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
932 extern int nv50_fb_init(struct drm_device *);
933 extern void nv50_fb_takedown(struct drm_device *);
936 extern int nv04_fifo_init(struct drm_device *);
937 extern void nv04_fifo_disable(struct drm_device *);
938 extern void nv04_fifo_enable(struct drm_device *);
939 extern bool nv04_fifo_reassign(struct drm_device *, bool);
940 extern bool nv04_fifo_cache_flush(struct drm_device *);
941 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
942 extern int nv04_fifo_channel_id(struct drm_device *);
943 extern int nv04_fifo_create_context(struct nouveau_channel *);
944 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
945 extern int nv04_fifo_load_context(struct nouveau_channel *);
946 extern int nv04_fifo_unload_context(struct drm_device *);
949 extern int nv10_fifo_init(struct drm_device *);
950 extern int nv10_fifo_channel_id(struct drm_device *);
951 extern int nv10_fifo_create_context(struct nouveau_channel *);
952 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
953 extern int nv10_fifo_load_context(struct nouveau_channel *);
954 extern int nv10_fifo_unload_context(struct drm_device *);
957 extern int nv40_fifo_init(struct drm_device *);
958 extern int nv40_fifo_create_context(struct nouveau_channel *);
959 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
960 extern int nv40_fifo_load_context(struct nouveau_channel *);
961 extern int nv40_fifo_unload_context(struct drm_device *);
964 extern int nv50_fifo_init(struct drm_device *);
965 extern void nv50_fifo_takedown(struct drm_device *);
966 extern int nv50_fifo_channel_id(struct drm_device *);
967 extern int nv50_fifo_create_context(struct nouveau_channel *);
968 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
969 extern int nv50_fifo_load_context(struct nouveau_channel *);
970 extern int nv50_fifo_unload_context(struct drm_device *);
973 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
974 extern int nv04_graph_init(struct drm_device *);
975 extern void nv04_graph_takedown(struct drm_device *);
976 extern void nv04_graph_fifo_access(struct drm_device *, bool);
977 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
978 extern int nv04_graph_create_context(struct nouveau_channel *);
979 extern void nv04_graph_destroy_context(struct nouveau_channel *);
980 extern int nv04_graph_load_context(struct nouveau_channel *);
981 extern int nv04_graph_unload_context(struct drm_device *);
982 extern void nv04_graph_context_switch(struct drm_device *);
985 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
986 extern int nv10_graph_init(struct drm_device *);
987 extern void nv10_graph_takedown(struct drm_device *);
988 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
989 extern int nv10_graph_create_context(struct nouveau_channel *);
990 extern void nv10_graph_destroy_context(struct nouveau_channel *);
991 extern int nv10_graph_load_context(struct nouveau_channel *);
992 extern int nv10_graph_unload_context(struct drm_device *);
993 extern void nv10_graph_context_switch(struct drm_device *);
994 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
998 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
999 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1000 extern int nv20_graph_create_context(struct nouveau_channel *);
1001 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1002 extern int nv20_graph_load_context(struct nouveau_channel *);
1003 extern int nv20_graph_unload_context(struct drm_device *);
1004 extern int nv20_graph_init(struct drm_device *);
1005 extern void nv20_graph_takedown(struct drm_device *);
1006 extern int nv30_graph_init(struct drm_device *);
1007 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1008 uint32_t, uint32_t);
1011 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1012 extern int nv40_graph_init(struct drm_device *);
1013 extern void nv40_graph_takedown(struct drm_device *);
1014 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1015 extern int nv40_graph_create_context(struct nouveau_channel *);
1016 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1017 extern int nv40_graph_load_context(struct nouveau_channel *);
1018 extern int nv40_graph_unload_context(struct drm_device *);
1019 extern void nv40_grctx_init(struct nouveau_grctx *);
1020 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1021 uint32_t, uint32_t);
1024 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1025 extern int nv50_graph_init(struct drm_device *);
1026 extern void nv50_graph_takedown(struct drm_device *);
1027 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1028 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1029 extern int nv50_graph_create_context(struct nouveau_channel *);
1030 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1031 extern int nv50_graph_load_context(struct nouveau_channel *);
1032 extern int nv50_graph_unload_context(struct drm_device *);
1033 extern void nv50_graph_context_switch(struct drm_device *);
1034 extern int nv50_grctx_init(struct nouveau_grctx *);
1036 /* nouveau_grctx.c */
1037 extern int nouveau_grctx_prog_load(struct drm_device *);
1038 extern void nouveau_grctx_vals_load(struct drm_device *,
1039 struct nouveau_gpuobj *);
1040 extern void nouveau_grctx_fini(struct drm_device *);
1042 /* nv04_instmem.c */
1043 extern int nv04_instmem_init(struct drm_device *);
1044 extern void nv04_instmem_takedown(struct drm_device *);
1045 extern int nv04_instmem_suspend(struct drm_device *);
1046 extern void nv04_instmem_resume(struct drm_device *);
1047 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1049 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1050 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1051 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1052 extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1053 extern void nv04_instmem_finish_access(struct drm_device *);
1055 /* nv50_instmem.c */
1056 extern int nv50_instmem_init(struct drm_device *);
1057 extern void nv50_instmem_takedown(struct drm_device *);
1058 extern int nv50_instmem_suspend(struct drm_device *);
1059 extern void nv50_instmem_resume(struct drm_device *);
1060 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1062 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1063 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1064 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1065 extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1066 extern void nv50_instmem_finish_access(struct drm_device *);
1069 extern int nv04_mc_init(struct drm_device *);
1070 extern void nv04_mc_takedown(struct drm_device *);
1073 extern int nv40_mc_init(struct drm_device *);
1074 extern void nv40_mc_takedown(struct drm_device *);
1077 extern int nv50_mc_init(struct drm_device *);
1078 extern void nv50_mc_takedown(struct drm_device *);
1081 extern int nv04_timer_init(struct drm_device *);
1082 extern uint64_t nv04_timer_read(struct drm_device *);
1083 extern void nv04_timer_takedown(struct drm_device *);
1085 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1089 extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
1090 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1091 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1092 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1095 extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry);
1096 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1097 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1099 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1100 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1103 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1104 extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1107 extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1109 /* nv04_display.c */
1110 extern int nv04_display_create(struct drm_device *);
1111 extern void nv04_display_destroy(struct drm_device *);
1112 extern void nv04_display_restore(struct drm_device *);
1115 extern int nv04_crtc_create(struct drm_device *, int index);
1118 extern struct ttm_bo_driver nouveau_bo_driver;
1119 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1120 int size, int align, uint32_t flags,
1121 uint32_t tile_mode, uint32_t tile_flags,
1122 bool no_vm, bool mappable, struct nouveau_bo **);
1123 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1124 extern int nouveau_bo_unpin(struct nouveau_bo *);
1125 extern int nouveau_bo_map(struct nouveau_bo *);
1126 extern void nouveau_bo_unmap(struct nouveau_bo *);
1127 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype);
1128 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1129 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1130 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1131 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1133 /* nouveau_fence.c */
1134 struct nouveau_fence;
1135 extern int nouveau_fence_init(struct nouveau_channel *);
1136 extern void nouveau_fence_fini(struct nouveau_channel *);
1137 extern void nouveau_fence_update(struct nouveau_channel *);
1138 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1140 extern int nouveau_fence_emit(struct nouveau_fence *);
1141 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1142 extern bool nouveau_fence_signalled(void *obj, void *arg);
1143 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1144 extern int nouveau_fence_flush(void *obj, void *arg);
1145 extern void nouveau_fence_unref(void **obj);
1146 extern void *nouveau_fence_ref(void *obj);
1147 extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1150 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1151 int size, int align, uint32_t flags,
1152 uint32_t tile_mode, uint32_t tile_flags,
1153 bool no_vm, bool mappable, struct nouveau_bo **);
1154 extern int nouveau_gem_object_new(struct drm_gem_object *);
1155 extern void nouveau_gem_object_del(struct drm_gem_object *);
1156 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1158 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1160 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1162 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1164 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1168 int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1169 int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1171 #ifndef ioread32_native
1173 #define ioread16_native ioread16be
1174 #define iowrite16_native iowrite16be
1175 #define ioread32_native ioread32be
1176 #define iowrite32_native iowrite32be
1177 #else /* def __BIG_ENDIAN */
1178 #define ioread16_native ioread16
1179 #define iowrite16_native iowrite16
1180 #define ioread32_native ioread32
1181 #define iowrite32_native iowrite32
1182 #endif /* def __BIG_ENDIAN else */
1183 #endif /* !ioread32_native */
1185 /* channel control reg access */
1186 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1188 return ioread32_native(chan->user + reg);
1191 static inline void nvchan_wr32(struct nouveau_channel *chan,
1192 unsigned reg, u32 val)
1194 iowrite32_native(val, chan->user + reg);
1197 /* register access */
1198 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1200 struct drm_nouveau_private *dev_priv = dev->dev_private;
1201 return ioread32_native(dev_priv->mmio + reg);
1204 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1206 struct drm_nouveau_private *dev_priv = dev->dev_private;
1207 iowrite32_native(val, dev_priv->mmio + reg);
1210 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1212 struct drm_nouveau_private *dev_priv = dev->dev_private;
1213 return ioread8(dev_priv->mmio + reg);
1216 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1218 struct drm_nouveau_private *dev_priv = dev->dev_private;
1219 iowrite8(val, dev_priv->mmio + reg);
1222 #define nv_wait(reg, mask, val) \
1223 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1226 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1228 struct drm_nouveau_private *dev_priv = dev->dev_private;
1229 return ioread32_native(dev_priv->ramin + offset);
1232 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1234 struct drm_nouveau_private *dev_priv = dev->dev_private;
1235 iowrite32_native(val, dev_priv->ramin + offset);
1239 static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1242 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1245 static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1246 unsigned index, u32 val)
1248 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1253 * Argument d is (struct drm_device *).
1255 #define NV_PRINTK(level, d, fmt, arg...) \
1256 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1257 pci_name(d->pdev), ##arg)
1258 #ifndef NV_DEBUG_NOTRACE
1259 #define NV_DEBUG(d, fmt, arg...) do { \
1260 if (drm_debug & DRM_UT_DRIVER) { \
1261 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1265 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1266 if (drm_debug & DRM_UT_KMS) { \
1267 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1272 #define NV_DEBUG(d, fmt, arg...) do { \
1273 if (drm_debug & DRM_UT_DRIVER) \
1274 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1276 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1277 if (drm_debug & DRM_UT_KMS) \
1278 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1281 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1282 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1283 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1284 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1285 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1287 /* nouveau_reg_debug bitmask */
1289 NOUVEAU_REG_DEBUG_MC = 0x1,
1290 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1291 NOUVEAU_REG_DEBUG_FB = 0x4,
1292 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1293 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1294 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1295 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1296 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1297 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1298 NOUVEAU_REG_DEBUG_EVO = 0x200,
1301 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1302 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1303 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1307 nv_two_heads(struct drm_device *dev)
1309 struct drm_nouveau_private *dev_priv = dev->dev_private;
1310 const int impl = dev->pci_device & 0x0ff0;
1312 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1313 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1320 nv_gf4_disp_arch(struct drm_device *dev)
1322 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1326 nv_two_reg_pll(struct drm_device *dev)
1328 struct drm_nouveau_private *dev_priv = dev->dev_private;
1329 const int impl = dev->pci_device & 0x0ff0;
1331 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1336 #define NV_SW 0x0000506e
1337 #define NV_SW_DMA_SEMAPHORE 0x00000060
1338 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1339 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1340 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1341 #define NV_SW_DMA_VBLSEM 0x0000018c
1342 #define NV_SW_VBLSEM_OFFSET 0x00000400
1343 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1344 #define NV_SW_VBLSEM_RELEASE 0x00000408
1346 #endif /* __NOUVEAU_DRV_H__ */