2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/console.h>
26 #include <linux/delay.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/vga_switcheroo.h>
31 #include <linux/mmu_notifier.h>
33 #include <drm/drm_aperture.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_gem_ttm_helper.h>
36 #include <drm/drm_ioctl.h>
37 #include <drm/drm_vblank.h>
39 #include <core/gpuobj.h>
40 #include <core/option.h>
42 #include <core/tegra.h>
44 #include <nvif/driver.h>
45 #include <nvif/fifo.h>
46 #include <nvif/push006c.h>
47 #include <nvif/user.h>
49 #include <nvif/class.h>
50 #include <nvif/cl0002.h>
51 #include <nvif/cla06f.h>
53 #include "nouveau_drv.h"
54 #include "nouveau_dma.h"
55 #include "nouveau_ttm.h"
56 #include "nouveau_gem.h"
57 #include "nouveau_vga.h"
58 #include "nouveau_led.h"
59 #include "nouveau_hwmon.h"
60 #include "nouveau_acpi.h"
61 #include "nouveau_bios.h"
62 #include "nouveau_ioctl.h"
63 #include "nouveau_abi16.h"
64 #include "nouveau_fbcon.h"
65 #include "nouveau_fence.h"
66 #include "nouveau_debugfs.h"
67 #include "nouveau_usif.h"
68 #include "nouveau_connector.h"
69 #include "nouveau_platform.h"
70 #include "nouveau_svm.h"
71 #include "nouveau_dmem.h"
73 MODULE_PARM_DESC(config, "option string to pass to driver core");
74 static char *nouveau_config;
75 module_param_named(config, nouveau_config, charp, 0400);
77 MODULE_PARM_DESC(debug, "debug string to pass to driver core");
78 static char *nouveau_debug;
79 module_param_named(debug, nouveau_debug, charp, 0400);
81 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
82 static int nouveau_noaccel = 0;
83 module_param_named(noaccel, nouveau_noaccel, int, 0400);
85 MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
86 "0 = disabled, 1 = enabled, 2 = headless)");
87 int nouveau_modeset = -1;
88 module_param_named(modeset, nouveau_modeset, int, 0400);
90 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
91 static int nouveau_atomic = 0;
92 module_param_named(atomic, nouveau_atomic, int, 0400);
94 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
95 static int nouveau_runtime_pm = -1;
96 module_param_named(runpm, nouveau_runtime_pm, int, 0400);
98 static struct drm_driver driver_stub;
99 static struct drm_driver driver_pci;
100 static struct drm_driver driver_platform;
103 nouveau_pci_name(struct pci_dev *pdev)
105 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
106 name |= pdev->bus->number << 16;
107 name |= PCI_SLOT(pdev->devfn) << 8;
108 return name | PCI_FUNC(pdev->devfn);
112 nouveau_platform_name(struct platform_device *platformdev)
114 return platformdev->id;
118 nouveau_name(struct drm_device *dev)
120 if (dev_is_pci(dev->dev))
121 return nouveau_pci_name(to_pci_dev(dev->dev));
123 return nouveau_platform_name(to_platform_device(dev->dev));
127 nouveau_cli_work_ready(struct dma_fence *fence)
129 if (!dma_fence_is_signaled(fence))
131 dma_fence_put(fence);
136 nouveau_cli_work(struct work_struct *w)
138 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
139 struct nouveau_cli_work *work, *wtmp;
140 mutex_lock(&cli->lock);
141 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
142 if (!work->fence || nouveau_cli_work_ready(work->fence)) {
143 list_del(&work->head);
147 mutex_unlock(&cli->lock);
151 nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
153 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
154 schedule_work(&work->cli->work);
158 nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
159 struct nouveau_cli_work *work)
161 work->fence = dma_fence_get(fence);
163 mutex_lock(&cli->lock);
164 list_add_tail(&work->head, &cli->worker);
165 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
166 nouveau_cli_work_fence(fence, &work->cb);
167 mutex_unlock(&cli->lock);
171 nouveau_cli_fini(struct nouveau_cli *cli)
173 /* All our channels are dead now, which means all the fences they
174 * own are signalled, and all callback functions have been called.
176 * So, after flushing the workqueue, there should be nothing left.
178 flush_work(&cli->work);
179 WARN_ON(!list_empty(&cli->worker));
181 usif_client_fini(cli);
182 nouveau_vmm_fini(&cli->svm);
183 nouveau_vmm_fini(&cli->vmm);
184 nvif_mmu_dtor(&cli->mmu);
185 nvif_device_dtor(&cli->device);
186 mutex_lock(&cli->drm->master.lock);
187 nvif_client_dtor(&cli->base);
188 mutex_unlock(&cli->drm->master.lock);
192 nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
193 struct nouveau_cli *cli)
195 static const struct nvif_mclass
197 { NVIF_CLASS_MEM_GF100, -1 },
198 { NVIF_CLASS_MEM_NV50 , -1 },
199 { NVIF_CLASS_MEM_NV04 , -1 },
202 static const struct nvif_mclass
204 { NVIF_CLASS_MMU_GF100, -1 },
205 { NVIF_CLASS_MMU_NV50 , -1 },
206 { NVIF_CLASS_MMU_NV04 , -1 },
209 static const struct nvif_mclass
211 { NVIF_CLASS_VMM_GP100, -1 },
212 { NVIF_CLASS_VMM_GM200, -1 },
213 { NVIF_CLASS_VMM_GF100, -1 },
214 { NVIF_CLASS_VMM_NV50 , -1 },
215 { NVIF_CLASS_VMM_NV04 , -1 },
218 u64 device = nouveau_name(drm->dev);
221 snprintf(cli->name, sizeof(cli->name), "%s", sname);
223 mutex_init(&cli->mutex);
224 usif_client_init(cli);
226 INIT_WORK(&cli->work, nouveau_cli_work);
227 INIT_LIST_HEAD(&cli->worker);
228 mutex_init(&cli->lock);
230 if (cli == &drm->master) {
231 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
232 cli->name, device, &cli->base);
234 mutex_lock(&drm->master.lock);
235 ret = nvif_client_ctor(&drm->master.base, cli->name, device,
237 mutex_unlock(&drm->master.lock);
240 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
244 ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE,
245 &(struct nv_device_v0) {
248 }, sizeof(struct nv_device_v0),
251 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
255 ret = nvif_mclass(&cli->device.object, mmus);
257 NV_PRINTK(err, cli, "No supported MMU class\n");
261 ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", mmus[ret].oclass,
264 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
268 ret = nvif_mclass(&cli->mmu.object, vmms);
270 NV_PRINTK(err, cli, "No supported VMM class\n");
274 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
276 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
280 ret = nvif_mclass(&cli->mmu.object, mems);
282 NV_PRINTK(err, cli, "No supported MEM class\n");
286 cli->mem = &mems[ret];
290 nouveau_cli_fini(cli);
295 nouveau_accel_ce_fini(struct nouveau_drm *drm)
297 nouveau_channel_idle(drm->cechan);
298 nvif_object_dtor(&drm->ttm.copy);
299 nouveau_channel_del(&drm->cechan);
303 nouveau_accel_ce_init(struct nouveau_drm *drm)
305 struct nvif_device *device = &drm->client.device;
308 /* Allocate channel that has access to a (preferably async) copy
309 * engine, to use for TTM buffer moves.
311 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
312 ret = nouveau_channel_new(drm, device,
313 nvif_fifo_runlist_ce(device), 0,
316 if (device->info.chipset >= 0xa3 &&
317 device->info.chipset != 0xaa &&
318 device->info.chipset != 0xac) {
319 /* Prior to Kepler, there's only a single runlist, so all
320 * engines can be accessed from any channel.
322 * We still want to use a separate channel though.
324 ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false,
329 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
333 nouveau_accel_gr_fini(struct nouveau_drm *drm)
335 nouveau_channel_idle(drm->channel);
336 nvif_object_dtor(&drm->ntfy);
337 nvkm_gpuobj_del(&drm->notify);
338 nouveau_channel_del(&drm->channel);
342 nouveau_accel_gr_init(struct nouveau_drm *drm)
344 struct nvif_device *device = &drm->client.device;
348 if (device->info.family >= NV_DEVICE_INFO_V0_AMPERE)
351 /* Allocate channel that has access to the graphics engine. */
352 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
353 arg0 = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR);
360 ret = nouveau_channel_new(drm, device, arg0, arg1, false,
363 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
364 nouveau_accel_gr_fini(drm);
368 /* A SW class is used on pre-NV50 HW to assist with handling the
369 * synchronisation of page flips, as well as to implement fences
370 * on TNT/TNT2 HW that lacks any kind of support in host.
372 if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) {
373 ret = nvif_object_ctor(&drm->channel->user, "drmNvsw",
374 NVDRM_NVSW, nouveau_abi16_swclass(drm),
375 NULL, 0, &drm->channel->nvsw);
377 struct nvif_push *push = drm->channel->chan.push;
378 ret = PUSH_WAIT(push, 2);
380 PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
384 NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
385 nouveau_accel_gr_fini(drm);
390 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
391 * even if notification is never requested, so, allocate a ctxdma on
392 * any GPU where it's possible we'll end up using M2MF for BO moves.
394 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
395 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,
398 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
399 nouveau_accel_gr_fini(drm);
403 ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy",
404 NvNotify0, NV_DMA_IN_MEMORY,
405 &(struct nv_dma_v0) {
406 .target = NV_DMA_V0_TARGET_VRAM,
407 .access = NV_DMA_V0_ACCESS_RDWR,
408 .start = drm->notify->addr,
409 .limit = drm->notify->addr + 31
410 }, sizeof(struct nv_dma_v0),
413 nouveau_accel_gr_fini(drm);
420 nouveau_accel_fini(struct nouveau_drm *drm)
422 nouveau_accel_ce_fini(drm);
423 nouveau_accel_gr_fini(drm);
425 nouveau_fence(drm)->dtor(drm);
429 nouveau_accel_init(struct nouveau_drm *drm)
431 struct nvif_device *device = &drm->client.device;
432 struct nvif_sclass *sclass;
438 /* Initialise global support for channels, and synchronisation. */
439 ret = nouveau_channels_init(drm);
443 /*XXX: this is crap, but the fence/channel stuff is a little
444 * backwards in some places. this will be fixed.
446 ret = n = nvif_object_sclass_get(&device->object, &sclass);
450 for (ret = -ENOSYS, i = 0; i < n; i++) {
451 switch (sclass[i].oclass) {
452 case NV03_CHANNEL_DMA:
453 ret = nv04_fence_create(drm);
455 case NV10_CHANNEL_DMA:
456 ret = nv10_fence_create(drm);
458 case NV17_CHANNEL_DMA:
459 case NV40_CHANNEL_DMA:
460 ret = nv17_fence_create(drm);
462 case NV50_CHANNEL_GPFIFO:
463 ret = nv50_fence_create(drm);
465 case G82_CHANNEL_GPFIFO:
466 ret = nv84_fence_create(drm);
468 case FERMI_CHANNEL_GPFIFO:
469 case KEPLER_CHANNEL_GPFIFO_A:
470 case KEPLER_CHANNEL_GPFIFO_B:
471 case MAXWELL_CHANNEL_GPFIFO_A:
472 case PASCAL_CHANNEL_GPFIFO_A:
473 case VOLTA_CHANNEL_GPFIFO_A:
474 case TURING_CHANNEL_GPFIFO_A:
475 case AMPERE_CHANNEL_GPFIFO_B:
476 ret = nvc0_fence_create(drm);
483 nvif_object_sclass_put(&sclass);
485 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
486 nouveau_accel_fini(drm);
490 /* Volta requires access to a doorbell register for kickoff. */
491 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
492 ret = nvif_user_ctor(device, "drmUsermode");
497 /* Allocate channels we need to support various functions. */
498 nouveau_accel_gr_init(drm);
499 nouveau_accel_ce_init(drm);
501 /* Initialise accelerated TTM buffer moves. */
502 nouveau_bo_move_init(drm);
505 static void __printf(2, 3)
506 nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...)
508 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
509 struct va_format vaf;
515 NV_ERROR(drm, "%pV", &vaf);
519 static void __printf(2, 3)
520 nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...)
522 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
523 struct va_format vaf;
529 NV_DEBUG(drm, "%pV", &vaf);
533 static const struct nvif_parent_func
535 .debugf = nouveau_drm_debugf,
536 .errorf = nouveau_drm_errorf,
540 nouveau_drm_device_init(struct drm_device *dev)
542 struct nouveau_drm *drm;
545 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
547 dev->dev_private = drm;
550 nvif_parent_ctor(&nouveau_parent, &drm->parent);
551 drm->master.base.object.parent = &drm->parent;
553 ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
557 ret = nouveau_cli_init(drm, "DRM", &drm->client);
561 nvxx_client(&drm->client.base)->debug =
562 nvkm_dbgopt(nouveau_debug, "DRM");
564 INIT_LIST_HEAD(&drm->clients);
565 spin_lock_init(&drm->tile.lock);
567 /* workaround an odd issue on nvc1 by disabling the device's
568 * nosnoop capability. hopefully won't cause issues until a
569 * better fix is found - assuming there is one...
571 if (drm->client.device.info.chipset == 0xc1)
572 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
574 nouveau_vga_init(drm);
576 ret = nouveau_ttm_init(drm);
580 ret = nouveau_bios_init(dev);
584 nouveau_accel_init(drm);
586 ret = nouveau_display_create(dev);
590 if (dev->mode_config.num_crtc) {
591 ret = nouveau_display_init(dev, false, false);
596 nouveau_debugfs_init(drm);
597 nouveau_hwmon_init(dev);
598 nouveau_svm_init(drm);
599 nouveau_dmem_init(drm);
600 nouveau_fbcon_init(dev);
601 nouveau_led_init(dev);
603 if (nouveau_pmops_runtime()) {
604 pm_runtime_use_autosuspend(dev->dev);
605 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
606 pm_runtime_set_active(dev->dev);
607 pm_runtime_allow(dev->dev);
608 pm_runtime_mark_last_busy(dev->dev);
609 pm_runtime_put(dev->dev);
615 nouveau_display_destroy(dev);
617 nouveau_accel_fini(drm);
618 nouveau_bios_takedown(dev);
620 nouveau_ttm_fini(drm);
622 nouveau_vga_fini(drm);
623 nouveau_cli_fini(&drm->client);
625 nouveau_cli_fini(&drm->master);
627 nvif_parent_dtor(&drm->parent);
633 nouveau_drm_device_fini(struct drm_device *dev)
635 struct nouveau_drm *drm = nouveau_drm(dev);
637 if (nouveau_pmops_runtime()) {
638 pm_runtime_get_sync(dev->dev);
639 pm_runtime_forbid(dev->dev);
642 nouveau_led_fini(dev);
643 nouveau_fbcon_fini(dev);
644 nouveau_dmem_fini(drm);
645 nouveau_svm_fini(drm);
646 nouveau_hwmon_fini(dev);
647 nouveau_debugfs_fini(drm);
649 if (dev->mode_config.num_crtc)
650 nouveau_display_fini(dev, false, false);
651 nouveau_display_destroy(dev);
653 nouveau_accel_fini(drm);
654 nouveau_bios_takedown(dev);
656 nouveau_ttm_fini(drm);
657 nouveau_vga_fini(drm);
659 nouveau_cli_fini(&drm->client);
660 nouveau_cli_fini(&drm->master);
661 nvif_parent_dtor(&drm->parent);
666 * On some Intel PCIe bridge controllers doing a
667 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear.
668 * Skipping the intermediate D3hot step seems to make it work again. This is
669 * probably caused by not meeting the expectation the involved AML code has
670 * when the GPU is put into D3hot state before invoking it.
672 * This leads to various manifestations of this issue:
673 * - AML code execution to power on the GPU hits an infinite loop (as the
674 * code waits on device memory to change).
675 * - kernel crashes, as all PCI reads return -1, which most code isn't able
676 * to handle well enough.
678 * In all cases dmesg will contain at least one line like this:
679 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3'
680 * followed by a lot of nouveau timeouts.
682 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
683 * documented PCI config space register 0x248 of the Intel PCIe bridge
684 * controller (0x1901) in order to change the state of the PCIe link between
685 * the PCIe port and the GPU. There are alternative code paths using other
686 * registers, which seem to work fine (executed pre Windows 8):
687 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
688 * - 0xb0 bit 0x10 (link disable)
689 * Changing the conditions inside the firmware by poking into the relevant
690 * addresses does resolve the issue, but it seemed to be ACPI private memory
691 * and not any device accessible memory at all, so there is no portable way of
692 * changing the conditions.
693 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
695 * The only systems where this behavior can be seen are hybrid graphics laptops
696 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether
697 * this issue only occurs in combination with listed Intel PCIe bridge
698 * controllers and the mentioned GPUs or other devices as well.
700 * documentation on the PCIe bridge controller can be found in the
701 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2"
702 * Section "12 PCI Express* Controller (x16) Registers"
705 static void quirk_broken_nv_runpm(struct pci_dev *pdev)
707 struct drm_device *dev = pci_get_drvdata(pdev);
708 struct nouveau_drm *drm = nouveau_drm(dev);
709 struct pci_dev *bridge = pci_upstream_bridge(pdev);
711 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL)
714 switch (bridge->device) {
716 drm->old_pm_cap = pdev->pm_cap;
718 NV_INFO(drm, "Disabling PCI power management to avoid bug\n");
723 static int nouveau_drm_probe(struct pci_dev *pdev,
724 const struct pci_device_id *pent)
726 struct nvkm_device *device;
727 struct drm_device *drm_dev;
730 if (vga_switcheroo_client_probe_defer(pdev))
731 return -EPROBE_DEFER;
733 /* We need to check that the chipset is supported before booting
734 * fbdev off the hardware, as there's no way to put it back.
736 ret = nvkm_device_pci_new(pdev, nouveau_config, "error",
737 true, false, 0, &device);
741 nvkm_device_del(&device);
743 /* Remove conflicting drivers (vesafb, efifb etc). */
744 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver_pci);
748 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
749 true, true, ~0ULL, &device);
753 pci_set_master(pdev);
756 driver_pci.driver_features |= DRIVER_ATOMIC;
758 drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev);
759 if (IS_ERR(drm_dev)) {
760 ret = PTR_ERR(drm_dev);
764 ret = pci_enable_device(pdev);
768 pci_set_drvdata(pdev, drm_dev);
770 ret = nouveau_drm_device_init(drm_dev);
774 ret = drm_dev_register(drm_dev, pent->driver_data);
776 goto fail_drm_dev_init;
778 quirk_broken_nv_runpm(pdev);
782 nouveau_drm_device_fini(drm_dev);
784 pci_disable_device(pdev);
786 drm_dev_put(drm_dev);
788 nvkm_device_del(&device);
793 nouveau_drm_device_remove(struct drm_device *dev)
795 struct nouveau_drm *drm = nouveau_drm(dev);
796 struct nvkm_client *client;
797 struct nvkm_device *device;
799 drm_dev_unregister(dev);
801 client = nvxx_client(&drm->client.base);
802 device = nvkm_device_find(client->device);
804 nouveau_drm_device_fini(dev);
806 nvkm_device_del(&device);
810 nouveau_drm_remove(struct pci_dev *pdev)
812 struct drm_device *dev = pci_get_drvdata(pdev);
813 struct nouveau_drm *drm = nouveau_drm(dev);
815 /* revert our workaround */
817 pdev->pm_cap = drm->old_pm_cap;
818 nouveau_drm_device_remove(dev);
819 pci_disable_device(pdev);
823 nouveau_do_suspend(struct drm_device *dev, bool runtime)
825 struct nouveau_drm *drm = nouveau_drm(dev);
826 struct ttm_resource_manager *man;
829 nouveau_svm_suspend(drm);
830 nouveau_dmem_suspend(drm);
831 nouveau_led_suspend(dev);
833 if (dev->mode_config.num_crtc) {
834 NV_DEBUG(drm, "suspending console...\n");
835 nouveau_fbcon_set_suspend(dev, 1);
836 NV_DEBUG(drm, "suspending display...\n");
837 ret = nouveau_display_suspend(dev, runtime);
842 NV_DEBUG(drm, "evicting buffers...\n");
844 man = ttm_manager_type(&drm->ttm.bdev, TTM_PL_VRAM);
845 ttm_resource_manager_evict_all(&drm->ttm.bdev, man);
847 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
849 ret = nouveau_channel_idle(drm->cechan);
855 ret = nouveau_channel_idle(drm->channel);
860 NV_DEBUG(drm, "suspending fence...\n");
861 if (drm->fence && nouveau_fence(drm)->suspend) {
862 if (!nouveau_fence(drm)->suspend(drm)) {
868 NV_DEBUG(drm, "suspending object tree...\n");
869 ret = nvif_client_suspend(&drm->master.base);
876 if (drm->fence && nouveau_fence(drm)->resume)
877 nouveau_fence(drm)->resume(drm);
880 if (dev->mode_config.num_crtc) {
881 NV_DEBUG(drm, "resuming display...\n");
882 nouveau_display_resume(dev, runtime);
888 nouveau_do_resume(struct drm_device *dev, bool runtime)
891 struct nouveau_drm *drm = nouveau_drm(dev);
893 NV_DEBUG(drm, "resuming object tree...\n");
894 ret = nvif_client_resume(&drm->master.base);
896 NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
900 NV_DEBUG(drm, "resuming fence...\n");
901 if (drm->fence && nouveau_fence(drm)->resume)
902 nouveau_fence(drm)->resume(drm);
904 nouveau_run_vbios_init(dev);
906 if (dev->mode_config.num_crtc) {
907 NV_DEBUG(drm, "resuming display...\n");
908 nouveau_display_resume(dev, runtime);
909 NV_DEBUG(drm, "resuming console...\n");
910 nouveau_fbcon_set_suspend(dev, 0);
913 nouveau_led_resume(dev);
914 nouveau_dmem_resume(drm);
915 nouveau_svm_resume(drm);
920 nouveau_pmops_suspend(struct device *dev)
922 struct pci_dev *pdev = to_pci_dev(dev);
923 struct drm_device *drm_dev = pci_get_drvdata(pdev);
926 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
927 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
930 ret = nouveau_do_suspend(drm_dev, false);
934 pci_save_state(pdev);
935 pci_disable_device(pdev);
936 pci_set_power_state(pdev, PCI_D3hot);
942 nouveau_pmops_resume(struct device *dev)
944 struct pci_dev *pdev = to_pci_dev(dev);
945 struct drm_device *drm_dev = pci_get_drvdata(pdev);
948 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
949 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
952 pci_set_power_state(pdev, PCI_D0);
953 pci_restore_state(pdev);
954 ret = pci_enable_device(pdev);
957 pci_set_master(pdev);
959 ret = nouveau_do_resume(drm_dev, false);
961 /* Monitors may have been connected / disconnected during suspend */
962 nouveau_display_hpd_resume(drm_dev);
968 nouveau_pmops_freeze(struct device *dev)
970 struct pci_dev *pdev = to_pci_dev(dev);
971 struct drm_device *drm_dev = pci_get_drvdata(pdev);
972 return nouveau_do_suspend(drm_dev, false);
976 nouveau_pmops_thaw(struct device *dev)
978 struct pci_dev *pdev = to_pci_dev(dev);
979 struct drm_device *drm_dev = pci_get_drvdata(pdev);
980 return nouveau_do_resume(drm_dev, false);
984 nouveau_pmops_runtime(void)
986 if (nouveau_runtime_pm == -1)
987 return nouveau_is_optimus() || nouveau_is_v1_dsm();
988 return nouveau_runtime_pm == 1;
992 nouveau_pmops_runtime_suspend(struct device *dev)
994 struct pci_dev *pdev = to_pci_dev(dev);
995 struct drm_device *drm_dev = pci_get_drvdata(pdev);
998 if (!nouveau_pmops_runtime()) {
999 pm_runtime_forbid(dev);
1003 nouveau_switcheroo_optimus_dsm();
1004 ret = nouveau_do_suspend(drm_dev, true);
1005 pci_save_state(pdev);
1006 pci_disable_device(pdev);
1007 pci_ignore_hotplug(pdev);
1008 pci_set_power_state(pdev, PCI_D3cold);
1009 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1014 nouveau_pmops_runtime_resume(struct device *dev)
1016 struct pci_dev *pdev = to_pci_dev(dev);
1017 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1018 struct nouveau_drm *drm = nouveau_drm(drm_dev);
1019 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
1022 if (!nouveau_pmops_runtime()) {
1023 pm_runtime_forbid(dev);
1027 pci_set_power_state(pdev, PCI_D0);
1028 pci_restore_state(pdev);
1029 ret = pci_enable_device(pdev);
1032 pci_set_master(pdev);
1034 ret = nouveau_do_resume(drm_dev, true);
1036 NV_ERROR(drm, "resume failed with: %d\n", ret);
1041 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
1042 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1044 /* Monitors may have been connected / disconnected during suspend */
1045 nouveau_display_hpd_resume(drm_dev);
1051 nouveau_pmops_runtime_idle(struct device *dev)
1053 if (!nouveau_pmops_runtime()) {
1054 pm_runtime_forbid(dev);
1058 pm_runtime_mark_last_busy(dev);
1059 pm_runtime_autosuspend(dev);
1060 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1065 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
1067 struct nouveau_drm *drm = nouveau_drm(dev);
1068 struct nouveau_cli *cli;
1069 char name[32], tmpname[TASK_COMM_LEN];
1072 /* need to bring up power immediately if opening device */
1073 ret = pm_runtime_get_sync(dev->dev);
1074 if (ret < 0 && ret != -EACCES) {
1075 pm_runtime_put_autosuspend(dev->dev);
1079 get_task_comm(tmpname, current);
1080 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
1082 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
1087 ret = nouveau_cli_init(drm, name, cli);
1091 fpriv->driver_priv = cli;
1093 mutex_lock(&drm->client.mutex);
1094 list_add(&cli->head, &drm->clients);
1095 mutex_unlock(&drm->client.mutex);
1099 nouveau_cli_fini(cli);
1103 pm_runtime_mark_last_busy(dev->dev);
1104 pm_runtime_put_autosuspend(dev->dev);
1109 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
1111 struct nouveau_cli *cli = nouveau_cli(fpriv);
1112 struct nouveau_drm *drm = nouveau_drm(dev);
1114 pm_runtime_get_sync(dev->dev);
1116 mutex_lock(&cli->mutex);
1118 nouveau_abi16_fini(cli->abi16);
1119 mutex_unlock(&cli->mutex);
1121 mutex_lock(&drm->client.mutex);
1122 list_del(&cli->head);
1123 mutex_unlock(&drm->client.mutex);
1125 nouveau_cli_fini(cli);
1127 pm_runtime_mark_last_busy(dev->dev);
1128 pm_runtime_put_autosuspend(dev->dev);
1131 static const struct drm_ioctl_desc
1132 nouveau_ioctls[] = {
1133 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
1134 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1135 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
1136 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
1137 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
1138 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
1139 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
1140 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
1141 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
1142 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
1143 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
1144 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
1145 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
1146 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
1150 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1152 struct drm_file *filp = file->private_data;
1153 struct drm_device *dev = filp->minor->dev;
1156 ret = pm_runtime_get_sync(dev->dev);
1157 if (ret < 0 && ret != -EACCES) {
1158 pm_runtime_put_autosuspend(dev->dev);
1162 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1163 case DRM_NOUVEAU_NVIF:
1164 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1167 ret = drm_ioctl(file, cmd, arg);
1171 pm_runtime_mark_last_busy(dev->dev);
1172 pm_runtime_put_autosuspend(dev->dev);
1176 static const struct file_operations
1177 nouveau_driver_fops = {
1178 .owner = THIS_MODULE,
1180 .release = drm_release,
1181 .unlocked_ioctl = nouveau_drm_ioctl,
1182 .mmap = drm_gem_mmap,
1185 #if defined(CONFIG_COMPAT)
1186 .compat_ioctl = nouveau_compat_ioctl,
1188 .llseek = noop_llseek,
1191 static struct drm_driver
1194 DRIVER_GEM | DRIVER_MODESET | DRIVER_RENDER
1195 #if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT)
1196 | DRIVER_KMS_LEGACY_CONTEXT
1200 .open = nouveau_drm_open,
1201 .postclose = nouveau_drm_postclose,
1202 .lastclose = nouveau_vga_lastclose,
1204 #if defined(CONFIG_DEBUG_FS)
1205 .debugfs_init = nouveau_drm_debugfs_init,
1208 .ioctls = nouveau_ioctls,
1209 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
1210 .fops = &nouveau_driver_fops,
1212 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1213 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1214 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1215 .gem_prime_mmap = drm_gem_prime_mmap,
1217 .dumb_create = nouveau_display_dumb_create,
1218 .dumb_map_offset = drm_gem_ttm_dumb_map_offset,
1220 .name = DRIVER_NAME,
1221 .desc = DRIVER_DESC,
1223 .date = GIT_REVISION,
1225 .date = DRIVER_DATE,
1227 .major = DRIVER_MAJOR,
1228 .minor = DRIVER_MINOR,
1229 .patchlevel = DRIVER_PATCHLEVEL,
1232 static struct pci_device_id
1233 nouveau_drm_pci_table[] = {
1235 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1236 .class = PCI_BASE_CLASS_DISPLAY << 16,
1237 .class_mask = 0xff << 16,
1240 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1241 .class = PCI_BASE_CLASS_DISPLAY << 16,
1242 .class_mask = 0xff << 16,
1247 static void nouveau_display_options(void)
1249 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1251 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1252 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1253 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1254 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
1255 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1256 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1257 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1258 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1259 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1260 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
1261 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
1264 static const struct dev_pm_ops nouveau_pm_ops = {
1265 .suspend = nouveau_pmops_suspend,
1266 .resume = nouveau_pmops_resume,
1267 .freeze = nouveau_pmops_freeze,
1268 .thaw = nouveau_pmops_thaw,
1269 .poweroff = nouveau_pmops_freeze,
1270 .restore = nouveau_pmops_resume,
1271 .runtime_suspend = nouveau_pmops_runtime_suspend,
1272 .runtime_resume = nouveau_pmops_runtime_resume,
1273 .runtime_idle = nouveau_pmops_runtime_idle,
1276 static struct pci_driver
1277 nouveau_drm_pci_driver = {
1279 .id_table = nouveau_drm_pci_table,
1280 .probe = nouveau_drm_probe,
1281 .remove = nouveau_drm_remove,
1282 .driver.pm = &nouveau_pm_ops,
1286 nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1287 struct platform_device *pdev,
1288 struct nvkm_device **pdevice)
1290 struct drm_device *drm;
1293 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
1294 true, true, ~0ULL, pdevice);
1298 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
1304 err = nouveau_drm_device_init(drm);
1308 platform_set_drvdata(pdev, drm);
1315 nvkm_device_del(pdevice);
1317 return ERR_PTR(err);
1321 nouveau_drm_init(void)
1323 driver_pci = driver_stub;
1324 driver_platform = driver_stub;
1326 nouveau_display_options();
1328 if (nouveau_modeset == -1) {
1329 if (vgacon_text_force())
1330 nouveau_modeset = 0;
1333 if (!nouveau_modeset)
1336 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1337 platform_driver_register(&nouveau_platform_driver);
1340 nouveau_register_dsm_handler();
1341 nouveau_backlight_ctor();
1344 return pci_register_driver(&nouveau_drm_pci_driver);
1351 nouveau_drm_exit(void)
1353 if (!nouveau_modeset)
1357 pci_unregister_driver(&nouveau_drm_pci_driver);
1359 nouveau_backlight_dtor();
1360 nouveau_unregister_dsm_handler();
1362 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1363 platform_driver_unregister(&nouveau_platform_driver);
1365 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM))
1366 mmu_notifier_synchronize();
1369 module_init(nouveau_drm_init);
1370 module_exit(nouveau_drm_exit);
1372 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
1373 MODULE_AUTHOR(DRIVER_AUTHOR);
1374 MODULE_DESCRIPTION(DRIVER_DESC);
1375 MODULE_LICENSE("GPL and additional rights");