2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
30 #include <linux/dma-mapping.h>
31 #include <linux/swiotlb.h>
33 #include "nouveau_drv.h"
34 #include "nouveau_chan.h"
35 #include "nouveau_fence.h"
37 #include "nouveau_bo.h"
38 #include "nouveau_ttm.h"
39 #include "nouveau_gem.h"
40 #include "nouveau_mem.h"
41 #include "nouveau_vmm.h"
43 #include <nvif/class.h>
44 #include <nvif/if500b.h>
45 #include <nvif/if900b.h>
47 static int nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm,
48 struct ttm_resource *reg);
51 * NV10-NV40 tiling helpers
55 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
56 u32 addr, u32 size, u32 pitch, u32 flags)
58 struct nouveau_drm *drm = nouveau_drm(dev);
59 int i = reg - drm->tile.reg;
60 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
61 struct nvkm_fb_tile *tile = &fb->tile.region[i];
63 nouveau_fence_unref(®->fence);
66 nvkm_fb_tile_fini(fb, i, tile);
69 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
71 nvkm_fb_tile_prog(fb, i, tile);
74 static struct nouveau_drm_tile *
75 nv10_bo_get_tile_region(struct drm_device *dev, int i)
77 struct nouveau_drm *drm = nouveau_drm(dev);
78 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80 spin_lock(&drm->tile.lock);
83 (!tile->fence || nouveau_fence_done(tile->fence)))
88 spin_unlock(&drm->tile.lock);
93 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
94 struct dma_fence *fence)
96 struct nouveau_drm *drm = nouveau_drm(dev);
99 spin_lock(&drm->tile.lock);
100 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
102 spin_unlock(&drm->tile.lock);
106 static struct nouveau_drm_tile *
107 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
108 u32 size, u32 pitch, u32 zeta)
110 struct nouveau_drm *drm = nouveau_drm(dev);
111 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
112 struct nouveau_drm_tile *tile, *found = NULL;
115 for (i = 0; i < fb->tile.regions; i++) {
116 tile = nv10_bo_get_tile_region(dev, i);
118 if (pitch && !found) {
122 } else if (tile && fb->tile.region[i].pitch) {
123 /* Kill an unused tile region. */
124 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
127 nv10_bo_put_tile_region(dev, tile, NULL);
131 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
136 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
138 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
139 struct drm_device *dev = drm->dev;
140 struct nouveau_bo *nvbo = nouveau_bo(bo);
142 WARN_ON(nvbo->bo.pin_count > 0);
143 nouveau_bo_del_io_reserve_lru(bo);
144 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
147 * If nouveau_bo_new() allocated this buffer, the GEM object was never
148 * initialized, so don't attempt to release it.
151 drm_gem_object_release(&bo->base);
157 roundup_64(u64 x, u32 y)
165 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
167 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
168 struct nvif_device *device = &drm->client.device;
170 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
172 if (device->info.chipset >= 0x40) {
174 *size = roundup_64(*size, 64 * nvbo->mode);
176 } else if (device->info.chipset >= 0x30) {
178 *size = roundup_64(*size, 64 * nvbo->mode);
180 } else if (device->info.chipset >= 0x20) {
182 *size = roundup_64(*size, 64 * nvbo->mode);
184 } else if (device->info.chipset >= 0x10) {
186 *size = roundup_64(*size, 32 * nvbo->mode);
190 *size = roundup_64(*size, (1 << nvbo->page));
191 *align = max((1 << nvbo->page), *align);
194 *size = roundup_64(*size, PAGE_SIZE);
198 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
199 u32 tile_mode, u32 tile_flags)
201 struct nouveau_drm *drm = cli->drm;
202 struct nouveau_bo *nvbo;
203 struct nvif_mmu *mmu = &cli->mmu;
204 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
208 NV_WARN(drm, "skipped size %016llx\n", *size);
209 return ERR_PTR(-EINVAL);
212 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
214 return ERR_PTR(-ENOMEM);
215 INIT_LIST_HEAD(&nvbo->head);
216 INIT_LIST_HEAD(&nvbo->entry);
217 INIT_LIST_HEAD(&nvbo->vma_list);
218 nvbo->bo.bdev = &drm->ttm.bdev;
220 /* This is confusing, and doesn't actually mean we want an uncached
221 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
222 * into in nouveau_gem_new().
224 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
225 /* Determine if we can get a cache-coherent map, forcing
226 * uncached mapping if we can't.
228 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
229 nvbo->force_coherent = true;
232 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
233 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
234 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
236 return ERR_PTR(-EINVAL);
239 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
241 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
242 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
243 nvbo->comp = (tile_flags & 0x00030000) >> 16;
244 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
246 return ERR_PTR(-EINVAL);
249 nvbo->zeta = (tile_flags & 0x00000007);
251 nvbo->mode = tile_mode;
252 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
254 /* Determine the desirable target GPU page size for the buffer. */
255 for (i = 0; i < vmm->page_nr; i++) {
256 /* Because we cannot currently allow VMM maps to fail
257 * during buffer migration, we need to determine page
258 * size for the buffer up-front, and pre-allocate its
261 * Skip page sizes that can't support needed domains.
263 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
264 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
266 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
267 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
270 /* Select this page size if it's the first that supports
271 * the potential memory domains, or when it's compatible
272 * with the requested compression settings.
274 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
277 /* Stop once the buffer is larger than the current page size. */
278 if (*size >= 1ULL << vmm->page[i].shift)
283 return ERR_PTR(-EINVAL);
285 /* Disable compression if suitable settings couldn't be found. */
286 if (nvbo->comp && !vmm->page[pi].comp) {
287 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
288 nvbo->kind = mmu->kind[nvbo->kind];
291 nvbo->page = vmm->page[pi].shift;
293 nouveau_bo_fixup_align(nvbo, align, size);
299 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
300 struct sg_table *sg, struct dma_resv *robj)
302 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
306 acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo));
308 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
309 nouveau_bo_placement_set(nvbo, domain, 0);
310 INIT_LIST_HEAD(&nvbo->io_reserve_lru);
312 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type,
313 &nvbo->placement, align >> PAGE_SHIFT, false,
314 acc_size, sg, robj, nouveau_bo_del_ttm);
316 /* ttm will call nouveau_bo_del_ttm if it fails.. */
324 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
325 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
326 struct sg_table *sg, struct dma_resv *robj,
327 struct nouveau_bo **pnvbo)
329 struct nouveau_bo *nvbo;
332 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
335 return PTR_ERR(nvbo);
337 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
346 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain)
350 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
351 pl[*n].mem_type = TTM_PL_VRAM;
355 if (domain & NOUVEAU_GEM_DOMAIN_GART) {
356 pl[*n].mem_type = TTM_PL_TT;
360 if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
361 pl[*n].mem_type = TTM_PL_SYSTEM;
362 pl[(*n)++].flags = 0;
367 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
369 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
370 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
371 unsigned i, fpfn, lpfn;
373 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
374 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
375 nvbo->bo.mem.num_pages < vram_pages / 4) {
377 * Make sure that the color and depth buffers are handled
378 * by independent memory controller units. Up to a 9x
379 * speed up when alpha-blending and depth-test are enabled
383 fpfn = vram_pages / 2;
387 lpfn = vram_pages / 2;
389 for (i = 0; i < nvbo->placement.num_placement; ++i) {
390 nvbo->placements[i].fpfn = fpfn;
391 nvbo->placements[i].lpfn = lpfn;
393 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
394 nvbo->busy_placements[i].fpfn = fpfn;
395 nvbo->busy_placements[i].lpfn = lpfn;
401 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
404 struct ttm_placement *pl = &nvbo->placement;
406 pl->placement = nvbo->placements;
407 set_placement_list(nvbo->placements, &pl->num_placement, domain);
409 pl->busy_placement = nvbo->busy_placements;
410 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
413 set_placement_range(nvbo, domain);
417 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
419 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
420 struct ttm_buffer_object *bo = &nvbo->bo;
421 bool force = false, evict = false;
424 ret = ttm_bo_reserve(bo, false, false, NULL);
428 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
429 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
437 if (nvbo->bo.pin_count) {
440 switch (bo->mem.mem_type) {
442 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
445 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
451 NV_ERROR(drm, "bo %p pinned elsewhere: "
452 "0x%08x vs 0x%08x\n", bo,
453 bo->mem.mem_type, domain);
456 ttm_bo_pin(&nvbo->bo);
461 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
462 ret = nouveau_bo_validate(nvbo, false, false);
467 nouveau_bo_placement_set(nvbo, domain, 0);
468 ret = nouveau_bo_validate(nvbo, false, false);
472 ttm_bo_pin(&nvbo->bo);
474 switch (bo->mem.mem_type) {
476 drm->gem.vram_available -= bo->mem.size;
479 drm->gem.gart_available -= bo->mem.size;
487 nvbo->contig = false;
488 ttm_bo_unreserve(bo);
493 nouveau_bo_unpin(struct nouveau_bo *nvbo)
495 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
496 struct ttm_buffer_object *bo = &nvbo->bo;
499 ret = ttm_bo_reserve(bo, false, false, NULL);
503 ttm_bo_unpin(&nvbo->bo);
504 if (!nvbo->bo.pin_count) {
505 switch (bo->mem.mem_type) {
507 drm->gem.vram_available += bo->mem.size;
510 drm->gem.gart_available += bo->mem.size;
517 ttm_bo_unreserve(bo);
522 nouveau_bo_map(struct nouveau_bo *nvbo)
526 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
530 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
532 ttm_bo_unreserve(&nvbo->bo);
537 nouveau_bo_unmap(struct nouveau_bo *nvbo)
542 ttm_bo_kunmap(&nvbo->kmap);
546 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
548 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
549 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
555 /* Don't waste time looping if the object is coherent */
556 if (nvbo->force_coherent)
559 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
560 dma_sync_single_for_device(drm->dev->dev,
561 ttm_dma->dma_address[i],
562 PAGE_SIZE, DMA_TO_DEVICE);
566 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
568 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
569 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
575 /* Don't waste time looping if the object is coherent */
576 if (nvbo->force_coherent)
579 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
580 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
581 PAGE_SIZE, DMA_FROM_DEVICE);
584 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
586 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
587 struct nouveau_bo *nvbo = nouveau_bo(bo);
589 mutex_lock(&drm->ttm.io_reserve_mutex);
590 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
591 mutex_unlock(&drm->ttm.io_reserve_mutex);
594 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
596 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
597 struct nouveau_bo *nvbo = nouveau_bo(bo);
599 mutex_lock(&drm->ttm.io_reserve_mutex);
600 list_del_init(&nvbo->io_reserve_lru);
601 mutex_unlock(&drm->ttm.io_reserve_mutex);
605 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
608 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
611 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
615 nouveau_bo_sync_for_device(nvbo);
621 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
624 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
629 iowrite16_native(val, (void __force __iomem *)mem);
635 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
638 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
643 return ioread32_native((void __force __iomem *)mem);
649 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
652 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
657 iowrite32_native(val, (void __force __iomem *)mem);
662 static struct ttm_tt *
663 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
665 #if IS_ENABLED(CONFIG_AGP)
666 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
668 if (drm->agp.bridge) {
669 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
673 return nouveau_sgdma_create_ttm(bo, page_flags);
677 nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm,
678 struct ttm_resource *reg)
680 #if IS_ENABLED(CONFIG_AGP)
681 struct nouveau_drm *drm = nouveau_bdev(bdev);
685 #if IS_ENABLED(CONFIG_AGP)
687 return ttm_agp_bind(ttm, reg);
689 return nouveau_sgdma_bind(bdev, ttm, reg);
693 nouveau_ttm_tt_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
695 #if IS_ENABLED(CONFIG_AGP)
696 struct nouveau_drm *drm = nouveau_bdev(bdev);
698 if (drm->agp.bridge) {
703 nouveau_sgdma_unbind(bdev, ttm);
707 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
709 struct nouveau_bo *nvbo = nouveau_bo(bo);
711 switch (bo->mem.mem_type) {
713 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
714 NOUVEAU_GEM_DOMAIN_CPU);
717 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
721 *pl = nvbo->placement;
725 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
726 struct ttm_resource *reg)
728 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
729 struct nouveau_mem *new_mem = nouveau_mem(reg);
730 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
733 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
734 old_mem->mem.size, &old_mem->vma[0]);
738 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
739 new_mem->mem.size, &old_mem->vma[1]);
743 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
747 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
750 nvif_vmm_put(vmm, &old_mem->vma[1]);
751 nvif_vmm_put(vmm, &old_mem->vma[0]);
757 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
758 struct ttm_operation_ctx *ctx,
759 struct ttm_resource *new_reg)
761 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
762 struct nouveau_channel *chan = drm->ttm.chan;
763 struct nouveau_cli *cli = (void *)chan->user.client;
764 struct nouveau_fence *fence;
767 /* create temporary vmas for the transfer and attach them to the
768 * old nvkm_mem node, these will get cleaned up after ttm has
769 * destroyed the ttm_resource
771 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
772 ret = nouveau_bo_move_prep(drm, bo, new_reg);
777 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
778 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
780 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
782 ret = nouveau_fence_new(chan, false, &fence);
784 ret = ttm_bo_move_accel_cleanup(bo,
788 nouveau_fence_unref(&fence);
792 mutex_unlock(&cli->mutex);
797 nouveau_bo_move_init(struct nouveau_drm *drm)
799 static const struct _method_table {
803 int (*exec)(struct nouveau_channel *,
804 struct ttm_buffer_object *,
805 struct ttm_resource *, struct ttm_resource *);
806 int (*init)(struct nouveau_channel *, u32 handle);
808 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
809 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
810 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
811 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
812 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
813 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
814 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
815 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
816 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
817 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
818 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
819 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
820 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
821 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
822 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
823 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
824 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
825 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
826 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
829 const struct _method_table *mthd = _methods;
830 const char *name = "CPU";
834 struct nouveau_channel *chan;
843 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
844 mthd->oclass | (mthd->engine << 16),
845 mthd->oclass, NULL, 0,
848 ret = mthd->init(chan, drm->ttm.copy.handle);
850 nvif_object_dtor(&drm->ttm.copy);
854 drm->ttm.move = mthd->exec;
855 drm->ttm.chan = chan;
859 } while ((++mthd)->exec);
861 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
865 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict,
866 struct ttm_operation_ctx *ctx,
867 struct ttm_resource *new_reg)
869 struct ttm_place placement_memtype = {
872 .mem_type = TTM_PL_TT,
875 struct ttm_placement placement;
876 struct ttm_resource tmp_reg;
879 placement.num_placement = placement.num_busy_placement = 1;
880 placement.placement = placement.busy_placement = &placement_memtype;
883 tmp_reg.mm_node = NULL;
884 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, ctx);
888 ret = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
892 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, &tmp_reg);
896 ret = nouveau_bo_move_m2mf(bo, true, ctx, &tmp_reg);
900 ret = ttm_bo_move_ttm(bo, ctx, new_reg);
902 ttm_resource_free(bo, &tmp_reg);
907 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict,
908 struct ttm_operation_ctx *ctx,
909 struct ttm_resource *new_reg)
911 struct ttm_place placement_memtype = {
914 .mem_type = TTM_PL_TT,
917 struct ttm_placement placement;
918 struct ttm_resource tmp_reg;
921 placement.num_placement = placement.num_busy_placement = 1;
922 placement.placement = placement.busy_placement = &placement_memtype;
925 tmp_reg.mm_node = NULL;
926 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, ctx);
930 ret = ttm_bo_move_to_new_tt_mem(bo, ctx, &tmp_reg);
934 ttm_bo_assign_mem(bo, &tmp_reg);
935 ret = nouveau_bo_move_m2mf(bo, true, ctx, new_reg);
940 ttm_resource_free(bo, &tmp_reg);
945 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict,
946 struct ttm_resource *new_reg)
948 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
949 struct nouveau_bo *nvbo = nouveau_bo(bo);
950 struct nouveau_vma *vma;
952 /* ttm can now (stupidly) pass the driver bos it didn't create... */
953 if (bo->destroy != nouveau_bo_del_ttm)
956 nouveau_bo_del_io_reserve_lru(bo);
958 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
959 mem->mem.page == nvbo->page) {
960 list_for_each_entry(vma, &nvbo->vma_list, head) {
961 nouveau_vma_map(vma, mem);
964 list_for_each_entry(vma, &nvbo->vma_list, head) {
965 WARN_ON(ttm_bo_wait(bo, false, false));
966 nouveau_vma_unmap(vma);
971 if (new_reg->mm_node)
972 nvbo->offset = (new_reg->start << PAGE_SHIFT);
980 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
981 struct nouveau_drm_tile **new_tile)
983 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
984 struct drm_device *dev = drm->dev;
985 struct nouveau_bo *nvbo = nouveau_bo(bo);
986 u64 offset = new_reg->start << PAGE_SHIFT;
989 if (new_reg->mem_type != TTM_PL_VRAM)
992 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
993 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size,
994 nvbo->mode, nvbo->zeta);
1001 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1002 struct nouveau_drm_tile *new_tile,
1003 struct nouveau_drm_tile **old_tile)
1005 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1006 struct drm_device *dev = drm->dev;
1007 struct dma_fence *fence = dma_resv_get_excl(bo->base.resv);
1009 nv10_bo_put_tile_region(dev, *old_tile, fence);
1010 *old_tile = new_tile;
1014 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1015 struct ttm_operation_ctx *ctx,
1016 struct ttm_resource *new_reg)
1018 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1019 struct nouveau_bo *nvbo = nouveau_bo(bo);
1020 struct ttm_resource *old_reg = &bo->mem;
1021 struct nouveau_drm_tile *new_tile = NULL;
1024 ret = ttm_bo_wait_ctx(bo, ctx);
1028 if (nvbo->bo.pin_count)
1029 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1031 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1032 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1038 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1039 ttm_bo_move_null(bo, new_reg);
1043 if (old_reg->mem_type == TTM_PL_SYSTEM &&
1044 new_reg->mem_type == TTM_PL_TT) {
1045 ttm_bo_move_null(bo, new_reg);
1049 if (old_reg->mem_type == TTM_PL_TT &&
1050 new_reg->mem_type == TTM_PL_SYSTEM) {
1051 ret = ttm_bo_move_ttm(bo, ctx, new_reg);
1055 /* Hardware assisted copy. */
1056 if (drm->ttm.move) {
1057 if (new_reg->mem_type == TTM_PL_SYSTEM)
1058 ret = nouveau_bo_move_flipd(bo, evict, ctx,
1060 else if (old_reg->mem_type == TTM_PL_SYSTEM)
1061 ret = nouveau_bo_move_flips(bo, evict, ctx,
1064 ret = nouveau_bo_move_m2mf(bo, evict, ctx,
1070 /* Fallback to software copy. */
1071 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1074 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1076 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1078 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1085 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1087 struct nouveau_bo *nvbo = nouveau_bo(bo);
1089 return drm_vma_node_verify_access(&nvbo->bo.base.vma_node,
1090 filp->private_data);
1094 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1095 struct ttm_resource *reg)
1097 struct nouveau_mem *mem = nouveau_mem(reg);
1099 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1100 switch (reg->mem_type) {
1103 nvif_object_unmap_handle(&mem->mem.object);
1106 nvif_object_unmap_handle(&mem->mem.object);
1115 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg)
1117 struct nouveau_drm *drm = nouveau_bdev(bdev);
1118 struct nvkm_device *device = nvxx_device(&drm->client.device);
1119 struct nouveau_mem *mem = nouveau_mem(reg);
1120 struct nvif_mmu *mmu = &drm->client.mmu;
1121 const u8 type = mmu->type[drm->ttm.type_vram].type;
1124 mutex_lock(&drm->ttm.io_reserve_mutex);
1126 switch (reg->mem_type) {
1132 #if IS_ENABLED(CONFIG_AGP)
1133 if (drm->agp.bridge) {
1134 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1136 reg->bus.is_iomem = !drm->agp.cma;
1137 reg->bus.caching = ttm_write_combined;
1140 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1146 fallthrough; /* tiled memory */
1148 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1149 device->func->resource_addr(device, 1);
1150 reg->bus.is_iomem = true;
1152 /* Some BARs do not support being ioremapped WC */
1153 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
1154 type & NVIF_MEM_UNCACHED)
1155 reg->bus.caching = ttm_uncached;
1157 reg->bus.caching = ttm_write_combined;
1159 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1161 struct nv50_mem_map_v0 nv50;
1162 struct gf100_mem_map_v0 gf100;
1167 switch (mem->mem.object.oclass) {
1168 case NVIF_CLASS_MEM_NV50:
1169 args.nv50.version = 0;
1171 args.nv50.kind = mem->kind;
1172 args.nv50.comp = mem->comp;
1173 argc = sizeof(args.nv50);
1175 case NVIF_CLASS_MEM_GF100:
1176 args.gf100.version = 0;
1178 args.gf100.kind = mem->kind;
1179 argc = sizeof(args.gf100);
1186 ret = nvif_object_map_handle(&mem->mem.object,
1190 if (WARN_ON(ret == 0))
1195 reg->bus.offset = handle;
1204 if (ret == -ENOSPC) {
1205 struct nouveau_bo *nvbo;
1207 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1211 list_del_init(&nvbo->io_reserve_lru);
1212 drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1214 nouveau_ttm_io_mem_free_locked(drm, &nvbo->bo.mem);
1219 mutex_unlock(&drm->ttm.io_reserve_mutex);
1224 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_resource *reg)
1226 struct nouveau_drm *drm = nouveau_bdev(bdev);
1228 mutex_lock(&drm->ttm.io_reserve_mutex);
1229 nouveau_ttm_io_mem_free_locked(drm, reg);
1230 mutex_unlock(&drm->ttm.io_reserve_mutex);
1233 vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1235 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1236 struct nouveau_bo *nvbo = nouveau_bo(bo);
1237 struct nvkm_device *device = nvxx_device(&drm->client.device);
1238 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1241 /* as long as the bo isn't in vram, and isn't tiled, we've got
1242 * nothing to do here.
1244 if (bo->mem.mem_type != TTM_PL_VRAM) {
1245 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1249 if (bo->mem.mem_type != TTM_PL_SYSTEM)
1252 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
1255 /* make sure bo is in mappable vram */
1256 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1257 bo->mem.start + bo->mem.num_pages < mappable)
1260 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1261 nvbo->placements[i].fpfn = 0;
1262 nvbo->placements[i].lpfn = mappable;
1265 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1266 nvbo->busy_placements[i].fpfn = 0;
1267 nvbo->busy_placements[i].lpfn = mappable;
1270 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1273 ret = nouveau_bo_validate(nvbo, false, false);
1274 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
1275 return VM_FAULT_NOPAGE;
1276 else if (unlikely(ret))
1277 return VM_FAULT_SIGBUS;
1279 ttm_bo_move_to_lru_tail_unlocked(bo);
1284 nouveau_ttm_tt_populate(struct ttm_bo_device *bdev,
1285 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1287 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1288 struct nouveau_drm *drm;
1290 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1292 if (ttm_tt_is_populated(ttm))
1295 if (slave && ttm->sg) {
1296 /* make userspace faulting work */
1297 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1298 ttm_dma->dma_address, ttm->num_pages);
1299 ttm_tt_set_populated(ttm);
1303 drm = nouveau_bdev(bdev);
1304 dev = drm->dev->dev;
1306 #if IS_ENABLED(CONFIG_AGP)
1307 if (drm->agp.bridge) {
1308 return ttm_pool_populate(ttm, ctx);
1312 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1313 if (swiotlb_nr_tbl()) {
1314 return ttm_dma_populate((void *)ttm, dev, ctx);
1317 return ttm_populate_and_map_pages(dev, ttm_dma, ctx);
1321 nouveau_ttm_tt_unpopulate(struct ttm_bo_device *bdev,
1324 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1325 struct nouveau_drm *drm;
1327 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1332 drm = nouveau_bdev(bdev);
1333 dev = drm->dev->dev;
1335 #if IS_ENABLED(CONFIG_AGP)
1336 if (drm->agp.bridge) {
1337 ttm_pool_unpopulate(ttm);
1342 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1343 if (swiotlb_nr_tbl()) {
1344 ttm_dma_unpopulate((void *)ttm, dev);
1349 ttm_unmap_and_unpopulate_pages(dev, ttm_dma);
1353 nouveau_ttm_tt_destroy(struct ttm_bo_device *bdev,
1356 #if IS_ENABLED(CONFIG_AGP)
1357 struct nouveau_drm *drm = nouveau_bdev(bdev);
1358 if (drm->agp.bridge) {
1359 ttm_agp_unbind(ttm);
1360 ttm_tt_destroy_common(bdev, ttm);
1361 ttm_agp_destroy(ttm);
1365 nouveau_sgdma_destroy(bdev, ttm);
1369 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1371 struct dma_resv *resv = nvbo->bo.base.resv;
1374 dma_resv_add_excl_fence(resv, &fence->base);
1376 dma_resv_add_shared_fence(resv, &fence->base);
1379 struct ttm_bo_driver nouveau_bo_driver = {
1380 .ttm_tt_create = &nouveau_ttm_tt_create,
1381 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1382 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1383 .ttm_tt_bind = &nouveau_ttm_tt_bind,
1384 .ttm_tt_unbind = &nouveau_ttm_tt_unbind,
1385 .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1386 .eviction_valuable = ttm_bo_eviction_valuable,
1387 .evict_flags = nouveau_bo_evict_flags,
1388 .move_notify = nouveau_bo_move_ntfy,
1389 .move = nouveau_bo_move,
1390 .verify_access = nouveau_bo_verify_access,
1391 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1392 .io_mem_free = &nouveau_ttm_io_mem_free,