drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/swiotlb.h>
  32
  33 #include "nouveau_drv.h"
  34 #include "nouveau_chan.h"
  35 #include "nouveau_fence.h"
  36
  37 #include "nouveau_bo.h"
  38 #include "nouveau_ttm.h"
  39 #include "nouveau_gem.h"
  40 #include "nouveau_mem.h"
  41 #include "nouveau_vmm.h"
  42
  43 #include <nvif/class.h>
  44 #include <nvif/if500b.h>
  45 #include <nvif/if900b.h>
  46
  47 /*
  48  * NV10-NV40 tiling helpers
  49  */
  50
  51 static void
  52 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
  53                            u32 addr, u32 size, u32 pitch, u32 flags)
  54 {
  55         struct nouveau_drm *drm = nouveau_drm(dev);
  56         int i = reg - drm->tile.reg;
  57         struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
  58         struct nvkm_fb_tile *tile = &fb->tile.region[i];
  59
  60         nouveau_fence_unref(&reg->fence);
  61
  62         if (tile->pitch)
  63                 nvkm_fb_tile_fini(fb, i, tile);
  64
  65         if (pitch)
  66                 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
  67
  68         nvkm_fb_tile_prog(fb, i, tile);
  69 }
  70
  71 static struct nouveau_drm_tile *
  72 nv10_bo_get_tile_region(struct drm_device *dev, int i)
  73 {
  74         struct nouveau_drm *drm = nouveau_drm(dev);
  75         struct nouveau_drm_tile *tile = &drm->tile.reg[i];
  76
  77         spin_lock(&drm->tile.lock);
  78
  79         if (!tile->used &&
  80             (!tile->fence || nouveau_fence_done(tile->fence)))
  81                 tile->used = true;
  82         else
  83                 tile = NULL;
  84
  85         spin_unlock(&drm->tile.lock);
  86         return tile;
  87 }
  88
  89 static void
  90 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
  91                         struct dma_fence *fence)
  92 {
  93         struct nouveau_drm *drm = nouveau_drm(dev);
  94
  95         if (tile) {
  96                 spin_lock(&drm->tile.lock);
  97                 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
  98                 tile->used = false;
  99                 spin_unlock(&drm->tile.lock);
 100         }
 101 }
 102
 103 static struct nouveau_drm_tile *
 104 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
 105                    u32 size, u32 pitch, u32 zeta)
 106 {
 107         struct nouveau_drm *drm = nouveau_drm(dev);
 108         struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
 109         struct nouveau_drm_tile *tile, *found = NULL;
 110         int i;
 111
 112         for (i = 0; i < fb->tile.regions; i++) {
 113                 tile = nv10_bo_get_tile_region(dev, i);
 114
 115                 if (pitch && !found) {
 116                         found = tile;
 117                         continue;
 118
 119                 } else if (tile && fb->tile.region[i].pitch) {
 120                         /* Kill an unused tile region. */
 121                         nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
 122                 }
 123
 124                 nv10_bo_put_tile_region(dev, tile, NULL);
 125         }
 126
 127         if (found)
 128                 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
 129         return found;
 130 }
 131
 132 static void
 133 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
 134 {
 135         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 136         struct drm_device *dev = drm->dev;
 137         struct nouveau_bo *nvbo = nouveau_bo(bo);
 138
 139         WARN_ON(nvbo->pin_refcnt > 0);
 140         nouveau_bo_del_io_reserve_lru(bo);
 141         nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
 142
 143         /*
 144          * If nouveau_bo_new() allocated this buffer, the GEM object was never
 145          * initialized, so don't attempt to release it.
 146          */
 147         if (bo->base.dev)
 148                 drm_gem_object_release(&bo->base);
 149
 150         kfree(nvbo);
 151 }
 152
 153 static inline u64
 154 roundup_64(u64 x, u32 y)
 155 {
 156         x += y - 1;
 157         do_div(x, y);
 158         return x * y;
 159 }
 160
 161 static void
 162 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
 163 {
 164         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 165         struct nvif_device *device = &drm->client.device;
 166
 167         if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
 168                 if (nvbo->mode) {
 169                         if (device->info.chipset >= 0x40) {
 170                                 *align = 65536;
 171                                 *size = roundup_64(*size, 64 * nvbo->mode);
 172
 173                         } else if (device->info.chipset >= 0x30) {
 174                                 *align = 32768;
 175                                 *size = roundup_64(*size, 64 * nvbo->mode);
 176
 177                         } else if (device->info.chipset >= 0x20) {
 178                                 *align = 16384;
 179                                 *size = roundup_64(*size, 64 * nvbo->mode);
 180
 181                         } else if (device->info.chipset >= 0x10) {
 182                                 *align = 16384;
 183                                 *size = roundup_64(*size, 32 * nvbo->mode);
 184                         }
 185                 }
 186         } else {
 187                 *size = roundup_64(*size, (1 << nvbo->page));
 188                 *align = max((1 <<  nvbo->page), *align);
 189         }
 190
 191         *size = roundup_64(*size, PAGE_SIZE);
 192 }
 193
 194 struct nouveau_bo *
 195 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
 196                  u32 tile_mode, u32 tile_flags)
 197 {
 198         struct nouveau_drm *drm = cli->drm;
 199         struct nouveau_bo *nvbo;
 200         struct nvif_mmu *mmu = &cli->mmu;
 201         struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
 202         int i, pi = -1;
 203
 204         if (!*size) {
 205                 NV_WARN(drm, "skipped size %016llx\n", *size);
 206                 return ERR_PTR(-EINVAL);
 207         }
 208
 209         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 210         if (!nvbo)
 211                 return ERR_PTR(-ENOMEM);
 212         INIT_LIST_HEAD(&nvbo->head);
 213         INIT_LIST_HEAD(&nvbo->entry);
 214         INIT_LIST_HEAD(&nvbo->vma_list);
 215         nvbo->bo.bdev = &drm->ttm.bdev;
 216
 217         /* This is confusing, and doesn't actually mean we want an uncached
 218          * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
 219          * into in nouveau_gem_new().
 220          */
 221         if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
 222                 /* Determine if we can get a cache-coherent map, forcing
 223                  * uncached mapping if we can't.
 224                  */
 225                 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
 226                         nvbo->force_coherent = true;
 227         }
 228
 229         if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
 230                 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
 231                 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
 232                         kfree(nvbo);
 233                         return ERR_PTR(-EINVAL);
 234                 }
 235
 236                 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
 237         } else
 238         if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
 239                 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
 240                 nvbo->comp = (tile_flags & 0x00030000) >> 16;
 241                 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
 242                         kfree(nvbo);
 243                         return ERR_PTR(-EINVAL);
 244                 }
 245         } else {
 246                 nvbo->zeta = (tile_flags & 0x00000007);
 247         }
 248         nvbo->mode = tile_mode;
 249         nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
 250
 251         /* Determine the desirable target GPU page size for the buffer. */
 252         for (i = 0; i < vmm->page_nr; i++) {
 253                 /* Because we cannot currently allow VMM maps to fail
 254                  * during buffer migration, we need to determine page
 255                  * size for the buffer up-front, and pre-allocate its
 256                  * page tables.
 257                  *
 258                  * Skip page sizes that can't support needed domains.
 259                  */
 260                 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
 261                     (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
 262                         continue;
 263                 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
 264                     (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
 265                         continue;
 266
 267                 /* Select this page size if it's the first that supports
 268                  * the potential memory domains, or when it's compatible
 269                  * with the requested compression settings.
 270                  */
 271                 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
 272                         pi = i;
 273
 274                 /* Stop once the buffer is larger than the current page size. */
 275                 if (*size >= 1ULL << vmm->page[i].shift)
 276                         break;
 277         }
 278
 279         if (WARN_ON(pi < 0))
 280                 return ERR_PTR(-EINVAL);
 281
 282         /* Disable compression if suitable settings couldn't be found. */
 283         if (nvbo->comp && !vmm->page[pi].comp) {
 284                 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
 285                         nvbo->kind = mmu->kind[nvbo->kind];
 286                 nvbo->comp = 0;
 287         }
 288         nvbo->page = vmm->page[pi].shift;
 289
 290         nouveau_bo_fixup_align(nvbo, align, size);
 291
 292         return nvbo;
 293 }
 294
 295 int
 296 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
 297                 struct sg_table *sg, struct dma_resv *robj)
 298 {
 299         int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
 300         size_t acc_size;
 301         int ret;
 302
 303         acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo));
 304
 305         nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
 306         nouveau_bo_placement_set(nvbo, domain, 0);
 307         INIT_LIST_HEAD(&nvbo->io_reserve_lru);
 308
 309         ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type,
 310                           &nvbo->placement, align >> PAGE_SHIFT, false,
 311                           acc_size, sg, robj, nouveau_bo_del_ttm);
 312         if (ret) {
 313                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 314                 return ret;
 315         }
 316
 317         return 0;
 318 }
 319
 320 int
 321 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
 322                uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
 323                struct sg_table *sg, struct dma_resv *robj,
 324                struct nouveau_bo **pnvbo)
 325 {
 326         struct nouveau_bo *nvbo;
 327         int ret;
 328
 329         nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
 330                                 tile_flags);
 331         if (IS_ERR(nvbo))
 332                 return PTR_ERR(nvbo);
 333
 334         ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
 335         if (ret)
 336                 return ret;
 337
 338         *pnvbo = nvbo;
 339         return 0;
 340 }
 341
 342 static void
 343 set_placement_list(struct nouveau_drm *drm, struct ttm_place *pl, unsigned *n,
 344                    uint32_t domain, uint32_t flags)
 345 {
 346         *n = 0;
 347
 348         if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
 349                 struct nvif_mmu *mmu = &drm->client.mmu;
 350                 const u8 type = mmu->type[drm->ttm.type_vram].type;
 351
 352                 pl[*n].mem_type = TTM_PL_VRAM;
 353                 pl[*n].flags = flags & ~TTM_PL_FLAG_CACHED;
 354
 355                 /* Some BARs do not support being ioremapped WC */
 356                 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
 357                     type & NVIF_MEM_UNCACHED)
 358                         pl[*n].flags &= ~TTM_PL_FLAG_WC;
 359
 360                 (*n)++;
 361         }
 362         if (domain & NOUVEAU_GEM_DOMAIN_GART) {
 363                 pl[*n].mem_type = TTM_PL_TT;
 364                 pl[*n].flags = flags;
 365
 366                 if (drm->agp.bridge)
 367                         pl[*n].flags &= ~TTM_PL_FLAG_CACHED;
 368
 369                 (*n)++;
 370         }
 371         if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
 372                 pl[*n].mem_type = TTM_PL_SYSTEM;
 373                 pl[(*n)++].flags = flags;
 374         }
 375 }
 376
 377 static void
 378 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
 379 {
 380         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 381         u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
 382         unsigned i, fpfn, lpfn;
 383
 384         if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
 385             nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
 386             nvbo->bo.mem.num_pages < vram_pages / 4) {
 387                 /*
 388                  * Make sure that the color and depth buffers are handled
 389                  * by independent memory controller units. Up to a 9x
 390                  * speed up when alpha-blending and depth-test are enabled
 391                  * at the same time.
 392                  */
 393                 if (nvbo->zeta) {
 394                         fpfn = vram_pages / 2;
 395                         lpfn = ~0;
 396                 } else {
 397                         fpfn = 0;
 398                         lpfn = vram_pages / 2;
 399                 }
 400                 for (i = 0; i < nvbo->placement.num_placement; ++i) {
 401                         nvbo->placements[i].fpfn = fpfn;
 402                         nvbo->placements[i].lpfn = lpfn;
 403                 }
 404                 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
 405                         nvbo->busy_placements[i].fpfn = fpfn;
 406                         nvbo->busy_placements[i].lpfn = lpfn;
 407                 }
 408         }
 409 }
 410
 411 void
 412 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
 413                          uint32_t busy)
 414 {
 415         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 416         struct ttm_placement *pl = &nvbo->placement;
 417         uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
 418                                                  TTM_PL_MASK_CACHING) |
 419                          (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
 420
 421         pl->placement = nvbo->placements;
 422         set_placement_list(drm, nvbo->placements, &pl->num_placement,
 423                            domain, flags);
 424
 425         pl->busy_placement = nvbo->busy_placements;
 426         set_placement_list(drm, nvbo->busy_placements, &pl->num_busy_placement,
 427                            domain | busy, flags);
 428
 429         set_placement_range(nvbo, domain);
 430 }
 431
 432 int
 433 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
 434 {
 435         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 436         struct ttm_buffer_object *bo = &nvbo->bo;
 437         bool force = false, evict = false;
 438         int ret;
 439
 440         ret = ttm_bo_reserve(bo, false, false, NULL);
 441         if (ret)
 442                 return ret;
 443
 444         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
 445             domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
 446                 if (!nvbo->contig) {
 447                         nvbo->contig = true;
 448                         force = true;
 449                         evict = true;
 450                 }
 451         }
 452
 453         if (nvbo->pin_refcnt) {
 454                 bool error = evict;
 455
 456                 switch (bo->mem.mem_type) {
 457                 case TTM_PL_VRAM:
 458                         error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
 459                         break;
 460                 case TTM_PL_TT:
 461                         error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
 462                 default:
 463                         break;
 464                 }
 465
 466                 if (error) {
 467                         NV_ERROR(drm, "bo %p pinned elsewhere: "
 468                                       "0x%08x vs 0x%08x\n", bo,
 469                                  bo->mem.mem_type, domain);
 470                         ret = -EBUSY;
 471                 }
 472                 nvbo->pin_refcnt++;
 473                 goto out;
 474         }
 475
 476         if (evict) {
 477                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
 478                 ret = nouveau_bo_validate(nvbo, false, false);
 479                 if (ret)
 480                         goto out;
 481         }
 482
 483         nvbo->pin_refcnt++;
 484         nouveau_bo_placement_set(nvbo, domain, 0);
 485
 486         /* drop pin_refcnt temporarily, so we don't trip the assertion
 487          * in nouveau_bo_move() that makes sure we're not trying to
 488          * move a pinned buffer
 489          */
 490         nvbo->pin_refcnt--;
 491         ret = nouveau_bo_validate(nvbo, false, false);
 492         if (ret)
 493                 goto out;
 494         nvbo->pin_refcnt++;
 495
 496         switch (bo->mem.mem_type) {
 497         case TTM_PL_VRAM:
 498                 drm->gem.vram_available -= bo->mem.size;
 499                 break;
 500         case TTM_PL_TT:
 501                 drm->gem.gart_available -= bo->mem.size;
 502                 break;
 503         default:
 504                 break;
 505         }
 506
 507 out:
 508         if (force && ret)
 509                 nvbo->contig = false;
 510         ttm_bo_unreserve(bo);
 511         return ret;
 512 }
 513
 514 int
 515 nouveau_bo_unpin(struct nouveau_bo *nvbo)
 516 {
 517         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 518         struct ttm_buffer_object *bo = &nvbo->bo;
 519         int ret, ref;
 520
 521         ret = ttm_bo_reserve(bo, false, false, NULL);
 522         if (ret)
 523                 return ret;
 524
 525         ref = --nvbo->pin_refcnt;
 526         WARN_ON_ONCE(ref < 0);
 527         if (ref)
 528                 goto out;
 529
 530         switch (bo->mem.mem_type) {
 531         case TTM_PL_VRAM:
 532                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
 533                 break;
 534         case TTM_PL_TT:
 535                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
 536                 break;
 537         default:
 538                 break;
 539         }
 540
 541         ret = nouveau_bo_validate(nvbo, false, false);
 542         if (ret == 0) {
 543                 switch (bo->mem.mem_type) {
 544                 case TTM_PL_VRAM:
 545                         drm->gem.vram_available += bo->mem.size;
 546                         break;
 547                 case TTM_PL_TT:
 548                         drm->gem.gart_available += bo->mem.size;
 549                         break;
 550                 default:
 551                         break;
 552                 }
 553         }
 554
 555 out:
 556         ttm_bo_unreserve(bo);
 557         return ret;
 558 }
 559
 560 int
 561 nouveau_bo_map(struct nouveau_bo *nvbo)
 562 {
 563         int ret;
 564
 565         ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
 566         if (ret)
 567                 return ret;
 568
 569         ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
 570
 571         ttm_bo_unreserve(&nvbo->bo);
 572         return ret;
 573 }
 574
 575 void
 576 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 577 {
 578         if (!nvbo)
 579                 return;
 580
 581         ttm_bo_kunmap(&nvbo->kmap);
 582 }
 583
 584 void
 585 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
 586 {
 587         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 588         struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
 589         int i;
 590
 591         if (!ttm_dma)
 592                 return;
 593
 594         /* Don't waste time looping if the object is coherent */
 595         if (nvbo->force_coherent)
 596                 return;
 597
 598         for (i = 0; i < ttm_dma->ttm.num_pages; i++)
 599                 dma_sync_single_for_device(drm->dev->dev,
 600                                            ttm_dma->dma_address[i],
 601                                            PAGE_SIZE, DMA_TO_DEVICE);
 602 }
 603
 604 void
 605 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
 606 {
 607         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 608         struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
 609         int i;
 610
 611         if (!ttm_dma)
 612                 return;
 613
 614         /* Don't waste time looping if the object is coherent */
 615         if (nvbo->force_coherent)
 616                 return;
 617
 618         for (i = 0; i < ttm_dma->ttm.num_pages; i++)
 619                 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
 620                                         PAGE_SIZE, DMA_FROM_DEVICE);
 621 }
 622
 623 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
 624 {
 625         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 626         struct nouveau_bo *nvbo = nouveau_bo(bo);
 627
 628         mutex_lock(&drm->ttm.io_reserve_mutex);
 629         list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
 630         mutex_unlock(&drm->ttm.io_reserve_mutex);
 631 }
 632
 633 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
 634 {
 635         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 636         struct nouveau_bo *nvbo = nouveau_bo(bo);
 637
 638         mutex_lock(&drm->ttm.io_reserve_mutex);
 639         list_del_init(&nvbo->io_reserve_lru);
 640         mutex_unlock(&drm->ttm.io_reserve_mutex);
 641 }
 642
 643 int
 644 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
 645                     bool no_wait_gpu)
 646 {
 647         struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
 648         int ret;
 649
 650         ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
 651         if (ret)
 652                 return ret;
 653
 654         nouveau_bo_sync_for_device(nvbo);
 655
 656         return 0;
 657 }
 658
 659 void
 660 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 661 {
 662         bool is_iomem;
 663         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 664
 665         mem += index;
 666
 667         if (is_iomem)
 668                 iowrite16_native(val, (void __force __iomem *)mem);
 669         else
 670                 *mem = val;
 671 }
 672
 673 u32
 674 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 675 {
 676         bool is_iomem;
 677         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 678
 679         mem += index;
 680
 681         if (is_iomem)
 682                 return ioread32_native((void __force __iomem *)mem);
 683         else
 684                 return *mem;
 685 }
 686
 687 void
 688 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 689 {
 690         bool is_iomem;
 691         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 692
 693         mem += index;
 694
 695         if (is_iomem)
 696                 iowrite32_native(val, (void __force __iomem *)mem);
 697         else
 698                 *mem = val;
 699 }
 700
 701 static struct ttm_tt *
 702 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
 703 {
 704 #if IS_ENABLED(CONFIG_AGP)
 705         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 706
 707         if (drm->agp.bridge) {
 708                 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
 709         }
 710 #endif
 711
 712         return nouveau_sgdma_create_ttm(bo, page_flags);
 713 }
 714
 715 static int
 716 nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm,
 717                     struct ttm_resource *reg)
 718 {
 719 #if IS_ENABLED(CONFIG_AGP)
 720         struct nouveau_drm *drm = nouveau_bdev(bdev);
 721 #endif
 722         if (!reg)
 723                 return -EINVAL;
 724 #if IS_ENABLED(CONFIG_AGP)
 725         if (drm->agp.bridge)
 726                 return ttm_agp_bind(ttm, reg);
 727 #endif
 728         return nouveau_sgdma_bind(bdev, ttm, reg);
 729 }
 730
 731 static void
 732 nouveau_ttm_tt_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
 733 {
 734 #if IS_ENABLED(CONFIG_AGP)
 735         struct nouveau_drm *drm = nouveau_bdev(bdev);
 736
 737         if (drm->agp.bridge) {
 738                 ttm_agp_unbind(ttm);
 739                 return;
 740         }
 741 #endif
 742         nouveau_sgdma_unbind(bdev, ttm);
 743 }
 744
 745 static void
 746 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 747 {
 748         struct nouveau_bo *nvbo = nouveau_bo(bo);
 749
 750         switch (bo->mem.mem_type) {
 751         case TTM_PL_VRAM:
 752                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
 753                                          NOUVEAU_GEM_DOMAIN_CPU);
 754                 break;
 755         default:
 756                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
 757                 break;
 758         }
 759
 760         *pl = nvbo->placement;
 761 }
 762
 763 static int
 764 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
 765                      struct ttm_resource *reg)
 766 {
 767         struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
 768         struct nouveau_mem *new_mem = nouveau_mem(reg);
 769         struct nvif_vmm *vmm = &drm->client.vmm.vmm;
 770         int ret;
 771
 772         ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
 773                            old_mem->mem.size, &old_mem->vma[0]);
 774         if (ret)
 775                 return ret;
 776
 777         ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
 778                            new_mem->mem.size, &old_mem->vma[1]);
 779         if (ret)
 780                 goto done;
 781
 782         ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
 783         if (ret)
 784                 goto done;
 785
 786         ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
 787 done:
 788         if (ret) {
 789                 nvif_vmm_put(vmm, &old_mem->vma[1]);
 790                 nvif_vmm_put(vmm, &old_mem->vma[0]);
 791         }
 792         return 0;
 793 }
 794
 795 static int
 796 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
 797                      bool no_wait_gpu, struct ttm_resource *new_reg)
 798 {
 799         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 800         struct nouveau_channel *chan = drm->ttm.chan;
 801         struct nouveau_cli *cli = (void *)chan->user.client;
 802         struct nouveau_fence *fence;
 803         int ret;
 804
 805         /* create temporary vmas for the transfer and attach them to the
 806          * old nvkm_mem node, these will get cleaned up after ttm has
 807          * destroyed the ttm_resource
 808          */
 809         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
 810                 ret = nouveau_bo_move_prep(drm, bo, new_reg);
 811                 if (ret)
 812                         return ret;
 813         }
 814
 815         mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
 816         ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
 817         if (ret == 0) {
 818                 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
 819                 if (ret == 0) {
 820                         ret = nouveau_fence_new(chan, false, &fence);
 821                         if (ret == 0) {
 822                                 ret = ttm_bo_move_accel_cleanup(bo,
 823                                                                 &fence->base,
 824                                                                 evict,
 825                                                                 new_reg);
 826                                 nouveau_fence_unref(&fence);
 827                         }
 828                 }
 829         }
 830         mutex_unlock(&cli->mutex);
 831         return ret;
 832 }
 833
 834 void
 835 nouveau_bo_move_init(struct nouveau_drm *drm)
 836 {
 837         static const struct _method_table {
 838                 const char *name;
 839                 int engine;
 840                 s32 oclass;
 841                 int (*exec)(struct nouveau_channel *,
 842                             struct ttm_buffer_object *,
 843                             struct ttm_resource *, struct ttm_resource *);
 844                 int (*init)(struct nouveau_channel *, u32 handle);
 845         } _methods[] = {
 846                 {  "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
 847                 {  "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
 848                 {  "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
 849                 {  "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
 850                 {  "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
 851                 {  "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
 852                 {  "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
 853                 {  "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
 854                 {  "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
 855                 {  "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
 856                 {  "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
 857                 {  "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
 858                 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
 859                 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
 860                 {  "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
 861                 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
 862                 {  "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
 863                 {  "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
 864                 {  "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
 865                 {},
 866         };
 867         const struct _method_table *mthd = _methods;
 868         const char *name = "CPU";
 869         int ret;
 870
 871         do {
 872                 struct nouveau_channel *chan;
 873
 874                 if (mthd->engine)
 875                         chan = drm->cechan;
 876                 else
 877                         chan = drm->channel;
 878                 if (chan == NULL)
 879                         continue;
 880
 881                 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
 882                                        mthd->oclass | (mthd->engine << 16),
 883                                        mthd->oclass, NULL, 0,
 884                                        &drm->ttm.copy);
 885                 if (ret == 0) {
 886                         ret = mthd->init(chan, drm->ttm.copy.handle);
 887                         if (ret) {
 888                                 nvif_object_dtor(&drm->ttm.copy);
 889                                 continue;
 890                         }
 891
 892                         drm->ttm.move = mthd->exec;
 893                         drm->ttm.chan = chan;
 894                         name = mthd->name;
 895                         break;
 896                 }
 897         } while ((++mthd)->exec);
 898
 899         NV_INFO(drm, "MM: using %s for buffer copies\n", name);
 900 }
 901
 902 static int
 903 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
 904                       bool no_wait_gpu, struct ttm_resource *new_reg)
 905 {
 906         struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
 907         struct ttm_place placement_memtype = {
 908                 .fpfn = 0,
 909                 .lpfn = 0,
 910                 .mem_type = TTM_PL_TT,
 911                 .flags = TTM_PL_MASK_CACHING
 912         };
 913         struct ttm_placement placement;
 914         struct ttm_resource tmp_reg;
 915         int ret;
 916
 917         placement.num_placement = placement.num_busy_placement = 1;
 918         placement.placement = placement.busy_placement = &placement_memtype;
 919
 920         tmp_reg = *new_reg;
 921         tmp_reg.mm_node = NULL;
 922         ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
 923         if (ret)
 924                 return ret;
 925
 926         ret = ttm_tt_populate(bo->bdev, bo->ttm, &ctx);
 927         if (ret)
 928                 goto out;
 929
 930         ret = ttm_bo_tt_bind(bo, &tmp_reg);
 931         if (ret)
 932                 goto out;
 933
 934         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg);
 935         if (ret)
 936                 goto out;
 937
 938         ret = ttm_bo_move_ttm(bo, &ctx, new_reg);
 939 out:
 940         ttm_resource_free(bo, &tmp_reg);
 941         return ret;
 942 }
 943
 944 static int
 945 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
 946                       bool no_wait_gpu, struct ttm_resource *new_reg)
 947 {
 948         struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
 949         struct ttm_place placement_memtype = {
 950                 .fpfn = 0,
 951                 .lpfn = 0,
 952                 .mem_type = TTM_PL_TT,
 953                 .flags = TTM_PL_MASK_CACHING
 954         };
 955         struct ttm_placement placement;
 956         struct ttm_resource tmp_reg;
 957         int ret;
 958
 959         placement.num_placement = placement.num_busy_placement = 1;
 960         placement.placement = placement.busy_placement = &placement_memtype;
 961
 962         tmp_reg = *new_reg;
 963         tmp_reg.mm_node = NULL;
 964         ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
 965         if (ret)
 966                 return ret;
 967
 968         ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg);
 969         if (ret)
 970                 goto out;
 971
 972         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg);
 973         if (ret)
 974                 goto out;
 975
 976 out:
 977         ttm_resource_free(bo, &tmp_reg);
 978         return ret;
 979 }
 980
 981 static void
 982 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict,
 983                      struct ttm_resource *new_reg)
 984 {
 985         struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
 986         struct nouveau_bo *nvbo = nouveau_bo(bo);
 987         struct nouveau_vma *vma;
 988
 989         /* ttm can now (stupidly) pass the driver bos it didn't create... */
 990         if (bo->destroy != nouveau_bo_del_ttm)
 991                 return;
 992
 993         nouveau_bo_del_io_reserve_lru(bo);
 994
 995         if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
 996             mem->mem.page == nvbo->page) {
 997                 list_for_each_entry(vma, &nvbo->vma_list, head) {
 998                         nouveau_vma_map(vma, mem);
 999                 }
1000         } else {
1001                 list_for_each_entry(vma, &nvbo->vma_list, head) {
1002                         WARN_ON(ttm_bo_wait(bo, false, false));
1003                         nouveau_vma_unmap(vma);
1004                 }
1005         }
1006
1007         if (new_reg) {
1008                 if (new_reg->mm_node)
1009                         nvbo->offset = (new_reg->start << PAGE_SHIFT);
1010                 else
1011                         nvbo->offset = 0;
1012         }
1013
1014 }
1015
1016 static int
1017 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
1018                    struct nouveau_drm_tile **new_tile)
1019 {
1020         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1021         struct drm_device *dev = drm->dev;
1022         struct nouveau_bo *nvbo = nouveau_bo(bo);
1023         u64 offset = new_reg->start << PAGE_SHIFT;
1024
1025         *new_tile = NULL;
1026         if (new_reg->mem_type != TTM_PL_VRAM)
1027                 return 0;
1028
1029         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1030                 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size,
1031                                                nvbo->mode, nvbo->zeta);
1032         }
1033
1034         return 0;
1035 }
1036
1037 static void
1038 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1039                       struct nouveau_drm_tile *new_tile,
1040                       struct nouveau_drm_tile **old_tile)
1041 {
1042         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1043         struct drm_device *dev = drm->dev;
1044         struct dma_fence *fence = dma_resv_get_excl(bo->base.resv);
1045
1046         nv10_bo_put_tile_region(dev, *old_tile, fence);
1047         *old_tile = new_tile;
1048 }
1049
1050 static int
1051 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1052                 struct ttm_operation_ctx *ctx,
1053                 struct ttm_resource *new_reg)
1054 {
1055         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1056         struct nouveau_bo *nvbo = nouveau_bo(bo);
1057         struct ttm_resource *old_reg = &bo->mem;
1058         struct nouveau_drm_tile *new_tile = NULL;
1059         int ret = 0;
1060
1061         ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1062         if (ret)
1063                 return ret;
1064
1065         if (nvbo->pin_refcnt)
1066                 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1067
1068         if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1069                 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1070                 if (ret)
1071                         return ret;
1072         }
1073
1074         /* Fake bo copy. */
1075         if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1076                 ttm_bo_move_null(bo, new_reg);
1077                 goto out;
1078         }
1079
1080         /* Hardware assisted copy. */
1081         if (drm->ttm.move) {
1082                 if (new_reg->mem_type == TTM_PL_SYSTEM)
1083                         ret = nouveau_bo_move_flipd(bo, evict,
1084                                                     ctx->interruptible,
1085                                                     ctx->no_wait_gpu, new_reg);
1086                 else if (old_reg->mem_type == TTM_PL_SYSTEM)
1087                         ret = nouveau_bo_move_flips(bo, evict,
1088                                                     ctx->interruptible,
1089                                                     ctx->no_wait_gpu, new_reg);
1090                 else
1091                         ret = nouveau_bo_move_m2mf(bo, evict,
1092                                                    ctx->interruptible,
1093                                                    ctx->no_wait_gpu, new_reg);
1094                 if (!ret)
1095                         goto out;
1096         }
1097
1098         /* Fallback to software copy. */
1099         ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1100         if (ret == 0)
1101                 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1102
1103 out:
1104         if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1105                 if (ret)
1106                         nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1107                 else
1108                         nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1109         }
1110
1111         return ret;
1112 }
1113
1114 static int
1115 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1116 {
1117         struct nouveau_bo *nvbo = nouveau_bo(bo);
1118
1119         return drm_vma_node_verify_access(&nvbo->bo.base.vma_node,
1120                                           filp->private_data);
1121 }
1122
1123 static void
1124 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1125                                struct ttm_resource *reg)
1126 {
1127         struct nouveau_mem *mem = nouveau_mem(reg);
1128
1129         if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1130                 switch (reg->mem_type) {
1131                 case TTM_PL_TT:
1132                         if (mem->kind)
1133                                 nvif_object_unmap_handle(&mem->mem.object);
1134                         break;
1135                 case TTM_PL_VRAM:
1136                         nvif_object_unmap_handle(&mem->mem.object);
1137                         break;
1138                 default:
1139                         break;
1140                 }
1141         }
1142 }
1143
1144 static int
1145 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg)
1146 {
1147         struct nouveau_drm *drm = nouveau_bdev(bdev);
1148         struct nvkm_device *device = nvxx_device(&drm->client.device);
1149         struct nouveau_mem *mem = nouveau_mem(reg);
1150         int ret;
1151
1152         mutex_lock(&drm->ttm.io_reserve_mutex);
1153 retry:
1154         switch (reg->mem_type) {
1155         case TTM_PL_SYSTEM:
1156                 /* System memory */
1157                 ret = 0;
1158                 goto out;
1159         case TTM_PL_TT:
1160 #if IS_ENABLED(CONFIG_AGP)
1161                 if (drm->agp.bridge) {
1162                         reg->bus.offset = (reg->start << PAGE_SHIFT) +
1163                                 drm->agp.base;
1164                         reg->bus.is_iomem = !drm->agp.cma;
1165                 }
1166 #endif
1167                 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1168                     !mem->kind) {
1169                         /* untiled */
1170                         ret = 0;
1171                         break;
1172                 }
1173                 fallthrough;    /* tiled memory */
1174         case TTM_PL_VRAM:
1175                 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1176                         device->func->resource_addr(device, 1);
1177                 reg->bus.is_iomem = true;
1178                 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1179                         union {
1180                                 struct nv50_mem_map_v0 nv50;
1181                                 struct gf100_mem_map_v0 gf100;
1182                         } args;
1183                         u64 handle, length;
1184                         u32 argc = 0;
1185
1186                         switch (mem->mem.object.oclass) {
1187                         case NVIF_CLASS_MEM_NV50:
1188                                 args.nv50.version = 0;
1189                                 args.nv50.ro = 0;
1190                                 args.nv50.kind = mem->kind;
1191                                 args.nv50.comp = mem->comp;
1192                                 argc = sizeof(args.nv50);
1193                                 break;
1194                         case NVIF_CLASS_MEM_GF100:
1195                                 args.gf100.version = 0;
1196                                 args.gf100.ro = 0;
1197                                 args.gf100.kind = mem->kind;
1198                                 argc = sizeof(args.gf100);
1199                                 break;
1200                         default:
1201                                 WARN_ON(1);
1202                                 break;
1203                         }
1204
1205                         ret = nvif_object_map_handle(&mem->mem.object,
1206                                                      &args, argc,
1207                                                      &handle, &length);
1208                         if (ret != 1) {
1209                                 if (WARN_ON(ret == 0))
1210                                         ret = -EINVAL;
1211                                 goto out;
1212                         }
1213
1214                         reg->bus.offset = handle;
1215                         ret = 0;
1216                 }
1217                 break;
1218         default:
1219                 ret = -EINVAL;
1220         }
1221
1222 out:
1223         if (ret == -ENOSPC) {
1224                 struct nouveau_bo *nvbo;
1225
1226                 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1227                                                 typeof(*nvbo),
1228                                                 io_reserve_lru);
1229                 if (nvbo) {
1230                         list_del_init(&nvbo->io_reserve_lru);
1231                         drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1232                                            bdev->dev_mapping);
1233                         nouveau_ttm_io_mem_free_locked(drm, &nvbo->bo.mem);
1234                         goto retry;
1235                 }
1236
1237         }
1238         mutex_unlock(&drm->ttm.io_reserve_mutex);
1239         return ret;
1240 }
1241
1242 static void
1243 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_resource *reg)
1244 {
1245         struct nouveau_drm *drm = nouveau_bdev(bdev);
1246
1247         mutex_lock(&drm->ttm.io_reserve_mutex);
1248         nouveau_ttm_io_mem_free_locked(drm, reg);
1249         mutex_unlock(&drm->ttm.io_reserve_mutex);
1250 }
1251
1252 static int
1253 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1254 {
1255         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1256         struct nouveau_bo *nvbo = nouveau_bo(bo);
1257         struct nvkm_device *device = nvxx_device(&drm->client.device);
1258         u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1259         int i, ret;
1260
1261         /* as long as the bo isn't in vram, and isn't tiled, we've got
1262          * nothing to do here.
1263          */
1264         if (bo->mem.mem_type != TTM_PL_VRAM) {
1265                 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1266                     !nvbo->kind)
1267                         return 0;
1268
1269                 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1270                         nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
1271                                                  0);
1272
1273                         ret = nouveau_bo_validate(nvbo, false, false);
1274                         if (ret)
1275                                 return ret;
1276                 }
1277                 return 0;
1278         }
1279
1280         /* make sure bo is in mappable vram */
1281         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1282             bo->mem.start + bo->mem.num_pages < mappable)
1283                 return 0;
1284
1285         for (i = 0; i < nvbo->placement.num_placement; ++i) {
1286                 nvbo->placements[i].fpfn = 0;
1287                 nvbo->placements[i].lpfn = mappable;
1288         }
1289
1290         for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1291                 nvbo->busy_placements[i].fpfn = 0;
1292                 nvbo->busy_placements[i].lpfn = mappable;
1293         }
1294
1295         nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1296         return nouveau_bo_validate(nvbo, false, false);
1297 }
1298
1299 static int
1300 nouveau_ttm_tt_populate(struct ttm_bo_device *bdev,
1301                         struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1302 {
1303         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1304         struct nouveau_drm *drm;
1305         struct device *dev;
1306         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1307
1308         if (ttm_tt_is_populated(ttm))
1309                 return 0;
1310
1311         if (slave && ttm->sg) {
1312                 /* make userspace faulting work */
1313                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1314                                                  ttm_dma->dma_address, ttm->num_pages);
1315                 ttm_tt_set_populated(ttm);
1316                 return 0;
1317         }
1318
1319         drm = nouveau_bdev(bdev);
1320         dev = drm->dev->dev;
1321
1322 #if IS_ENABLED(CONFIG_AGP)
1323         if (drm->agp.bridge) {
1324                 return ttm_pool_populate(ttm, ctx);
1325         }
1326 #endif
1327
1328 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1329         if (swiotlb_nr_tbl()) {
1330                 return ttm_dma_populate((void *)ttm, dev, ctx);
1331         }
1332 #endif
1333         return ttm_populate_and_map_pages(dev, ttm_dma, ctx);
1334 }
1335
1336 static void
1337 nouveau_ttm_tt_unpopulate(struct ttm_bo_device *bdev,
1338                           struct ttm_tt *ttm)
1339 {
1340         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1341         struct nouveau_drm *drm;
1342         struct device *dev;
1343         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1344
1345         if (slave)
1346                 return;
1347
1348         drm = nouveau_bdev(bdev);
1349         dev = drm->dev->dev;
1350
1351 #if IS_ENABLED(CONFIG_AGP)
1352         if (drm->agp.bridge) {
1353                 ttm_pool_unpopulate(ttm);
1354                 return;
1355         }
1356 #endif
1357
1358 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1359         if (swiotlb_nr_tbl()) {
1360                 ttm_dma_unpopulate((void *)ttm, dev);
1361                 return;
1362         }
1363 #endif
1364
1365         ttm_unmap_and_unpopulate_pages(dev, ttm_dma);
1366 }
1367
1368 static void
1369 nouveau_ttm_tt_destroy(struct ttm_bo_device *bdev,
1370                        struct ttm_tt *ttm)
1371 {
1372 #if IS_ENABLED(CONFIG_AGP)
1373         struct nouveau_drm *drm = nouveau_bdev(bdev);
1374         if (drm->agp.bridge) {
1375                 ttm_tt_destroy_common(bdev, ttm);
1376                 ttm_agp_destroy(ttm);
1377                 return;
1378         }
1379 #endif
1380         nouveau_sgdma_destroy(bdev, ttm);
1381 }
1382
1383 void
1384 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1385 {
1386         struct dma_resv *resv = nvbo->bo.base.resv;
1387
1388         if (exclusive)
1389                 dma_resv_add_excl_fence(resv, &fence->base);
1390         else if (fence)
1391                 dma_resv_add_shared_fence(resv, &fence->base);
1392 }
1393
1394 struct ttm_bo_driver nouveau_bo_driver = {
1395         .ttm_tt_create = &nouveau_ttm_tt_create,
1396         .ttm_tt_populate = &nouveau_ttm_tt_populate,
1397         .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1398         .ttm_tt_bind = &nouveau_ttm_tt_bind,
1399         .ttm_tt_unbind = &nouveau_ttm_tt_unbind,
1400         .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1401         .eviction_valuable = ttm_bo_eviction_valuable,
1402         .evict_flags = nouveau_bo_evict_flags,
1403         .move_notify = nouveau_bo_move_ntfy,
1404         .move = nouveau_bo_move,
1405         .verify_access = nouveau_bo_verify_access,
1406         .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1407         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1408         .io_mem_free = &nouveau_ttm_io_mem_free,
1409 };