drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/swiotlb.h>
  32
  33 #include "nouveau_drv.h"
  34 #include "nouveau_dma.h"
  35 #include "nouveau_fence.h"
  36
  37 #include "nouveau_bo.h"
  38 #include "nouveau_ttm.h"
  39 #include "nouveau_gem.h"
  40
  41 /*
  42  * NV10-NV40 tiling helpers
  43  */
  44
  45 static void
  46 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
  47                            u32 addr, u32 size, u32 pitch, u32 flags)
  48 {
  49         struct nouveau_drm *drm = nouveau_drm(dev);
  50         int i = reg - drm->tile.reg;
  51         struct nvkm_device *device = nvxx_device(&drm->device);
  52         struct nvkm_fb *fb = device->fb;
  53         struct nvkm_fb_tile *tile = &fb->tile.region[i];
  54
  55         nouveau_fence_unref(&reg->fence);
  56
  57         if (tile->pitch)
  58                 nvkm_fb_tile_fini(fb, i, tile);
  59
  60         if (pitch)
  61                 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
  62
  63         nvkm_fb_tile_prog(fb, i, tile);
  64 }
  65
  66 static struct nouveau_drm_tile *
  67 nv10_bo_get_tile_region(struct drm_device *dev, int i)
  68 {
  69         struct nouveau_drm *drm = nouveau_drm(dev);
  70         struct nouveau_drm_tile *tile = &drm->tile.reg[i];
  71
  72         spin_lock(&drm->tile.lock);
  73
  74         if (!tile->used &&
  75             (!tile->fence || nouveau_fence_done(tile->fence)))
  76                 tile->used = true;
  77         else
  78                 tile = NULL;
  79
  80         spin_unlock(&drm->tile.lock);
  81         return tile;
  82 }
  83
  84 static void
  85 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
  86                         struct fence *fence)
  87 {
  88         struct nouveau_drm *drm = nouveau_drm(dev);
  89
  90         if (tile) {
  91                 spin_lock(&drm->tile.lock);
  92                 tile->fence = (struct nouveau_fence *)fence_get(fence);
  93                 tile->used = false;
  94                 spin_unlock(&drm->tile.lock);
  95         }
  96 }
  97
  98 static struct nouveau_drm_tile *
  99 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
 100                    u32 size, u32 pitch, u32 flags)
 101 {
 102         struct nouveau_drm *drm = nouveau_drm(dev);
 103         struct nvkm_fb *fb = nvxx_fb(&drm->device);
 104         struct nouveau_drm_tile *tile, *found = NULL;
 105         int i;
 106
 107         for (i = 0; i < fb->tile.regions; i++) {
 108                 tile = nv10_bo_get_tile_region(dev, i);
 109
 110                 if (pitch && !found) {
 111                         found = tile;
 112                         continue;
 113
 114                 } else if (tile && fb->tile.region[i].pitch) {
 115                         /* Kill an unused tile region. */
 116                         nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
 117                 }
 118
 119                 nv10_bo_put_tile_region(dev, tile, NULL);
 120         }
 121
 122         if (found)
 123                 nv10_bo_update_tile_region(dev, found, addr, size,
 124                                             pitch, flags);
 125         return found;
 126 }
 127
 128 static void
 129 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
 130 {
 131         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 132         struct drm_device *dev = drm->dev;
 133         struct nouveau_bo *nvbo = nouveau_bo(bo);
 134
 135         if (unlikely(nvbo->gem.filp))
 136                 DRM_ERROR("bo %p still attached to GEM object\n", bo);
 137         WARN_ON(nvbo->pin_refcnt > 0);
 138         nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
 139         kfree(nvbo);
 140 }
 141
 142 static void
 143 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
 144                        int *align, int *size)
 145 {
 146         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 147         struct nvif_device *device = &drm->device;
 148
 149         if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
 150                 if (nvbo->tile_mode) {
 151                         if (device->info.chipset >= 0x40) {
 152                                 *align = 65536;
 153                                 *size = roundup(*size, 64 * nvbo->tile_mode);
 154
 155                         } else if (device->info.chipset >= 0x30) {
 156                                 *align = 32768;
 157                                 *size = roundup(*size, 64 * nvbo->tile_mode);
 158
 159                         } else if (device->info.chipset >= 0x20) {
 160                                 *align = 16384;
 161                                 *size = roundup(*size, 64 * nvbo->tile_mode);
 162
 163                         } else if (device->info.chipset >= 0x10) {
 164                                 *align = 16384;
 165                                 *size = roundup(*size, 32 * nvbo->tile_mode);
 166                         }
 167                 }
 168         } else {
 169                 *size = roundup(*size, (1 << nvbo->page_shift));
 170                 *align = max((1 <<  nvbo->page_shift), *align);
 171         }
 172
 173         *size = roundup(*size, PAGE_SIZE);
 174 }
 175
 176 int
 177 nouveau_bo_new(struct drm_device *dev, int size, int align,
 178                uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
 179                struct sg_table *sg, struct reservation_object *robj,
 180                struct nouveau_bo **pnvbo)
 181 {
 182         struct nouveau_drm *drm = nouveau_drm(dev);
 183         struct nouveau_bo *nvbo;
 184         size_t acc_size;
 185         int ret;
 186         int type = ttm_bo_type_device;
 187         int lpg_shift = 12;
 188         int max_size;
 189
 190         if (drm->client.vm)
 191                 lpg_shift = drm->client.vm->mmu->lpg_shift;
 192         max_size = INT_MAX & ~((1 << lpg_shift) - 1);
 193
 194         if (size <= 0 || size > max_size) {
 195                 NV_WARN(drm, "skipped size %x\n", (u32)size);
 196                 return -EINVAL;
 197         }
 198
 199         if (sg)
 200                 type = ttm_bo_type_sg;
 201
 202         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 203         if (!nvbo)
 204                 return -ENOMEM;
 205         INIT_LIST_HEAD(&nvbo->head);
 206         INIT_LIST_HEAD(&nvbo->entry);
 207         INIT_LIST_HEAD(&nvbo->vma_list);
 208         nvbo->tile_mode = tile_mode;
 209         nvbo->tile_flags = tile_flags;
 210         nvbo->bo.bdev = &drm->ttm.bdev;
 211
 212         nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED;
 213
 214         nvbo->page_shift = 12;
 215         if (drm->client.vm) {
 216                 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
 217                         nvbo->page_shift = drm->client.vm->mmu->lpg_shift;
 218         }
 219
 220         nouveau_bo_fixup_align(nvbo, flags, &align, &size);
 221         nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
 222         nouveau_bo_placement_set(nvbo, flags, 0);
 223
 224         acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
 225                                        sizeof(struct nouveau_bo));
 226
 227         ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
 228                           type, &nvbo->placement,
 229                           align >> PAGE_SHIFT, false, NULL, acc_size, sg,
 230                           robj, nouveau_bo_del_ttm);
 231         if (ret) {
 232                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 233                 return ret;
 234         }
 235
 236         *pnvbo = nvbo;
 237         return 0;
 238 }
 239
 240 static void
 241 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
 242 {
 243         *n = 0;
 244
 245         if (type & TTM_PL_FLAG_VRAM)
 246                 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
 247         if (type & TTM_PL_FLAG_TT)
 248                 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
 249         if (type & TTM_PL_FLAG_SYSTEM)
 250                 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
 251 }
 252
 253 static void
 254 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
 255 {
 256         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 257         u32 vram_pages = drm->device.info.ram_size >> PAGE_SHIFT;
 258         unsigned i, fpfn, lpfn;
 259
 260         if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
 261             nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
 262             nvbo->bo.mem.num_pages < vram_pages / 4) {
 263                 /*
 264                  * Make sure that the color and depth buffers are handled
 265                  * by independent memory controller units. Up to a 9x
 266                  * speed up when alpha-blending and depth-test are enabled
 267                  * at the same time.
 268                  */
 269                 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
 270                         fpfn = vram_pages / 2;
 271                         lpfn = ~0;
 272                 } else {
 273                         fpfn = 0;
 274                         lpfn = vram_pages / 2;
 275                 }
 276                 for (i = 0; i < nvbo->placement.num_placement; ++i) {
 277                         nvbo->placements[i].fpfn = fpfn;
 278                         nvbo->placements[i].lpfn = lpfn;
 279                 }
 280                 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
 281                         nvbo->busy_placements[i].fpfn = fpfn;
 282                         nvbo->busy_placements[i].lpfn = lpfn;
 283                 }
 284         }
 285 }
 286
 287 void
 288 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
 289 {
 290         struct ttm_placement *pl = &nvbo->placement;
 291         uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
 292                                                  TTM_PL_MASK_CACHING) |
 293                          (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
 294
 295         pl->placement = nvbo->placements;
 296         set_placement_list(nvbo->placements, &pl->num_placement,
 297                            type, flags);
 298
 299         pl->busy_placement = nvbo->busy_placements;
 300         set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
 301                            type | busy, flags);
 302
 303         set_placement_range(nvbo, type);
 304 }
 305
 306 int
 307 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
 308 {
 309         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 310         struct ttm_buffer_object *bo = &nvbo->bo;
 311         bool force = false, evict = false;
 312         int ret;
 313
 314         ret = ttm_bo_reserve(bo, false, false, NULL);
 315         if (ret)
 316                 return ret;
 317
 318         if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
 319             memtype == TTM_PL_FLAG_VRAM && contig) {
 320                 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) {
 321                         if (bo->mem.mem_type == TTM_PL_VRAM) {
 322                                 struct nvkm_mem *mem = bo->mem.mm_node;
 323                                 if (!list_is_singular(&mem->regions))
 324                                         evict = true;
 325                         }
 326                         nvbo->tile_flags &= ~NOUVEAU_GEM_TILE_NONCONTIG;
 327                         force = true;
 328                 }
 329         }
 330
 331         if (nvbo->pin_refcnt) {
 332                 if (!(memtype & (1 << bo->mem.mem_type)) || evict) {
 333                         NV_ERROR(drm, "bo %p pinned elsewhere: "
 334                                       "0x%08x vs 0x%08x\n", bo,
 335                                  1 << bo->mem.mem_type, memtype);
 336                         ret = -EBUSY;
 337                 }
 338                 nvbo->pin_refcnt++;
 339                 goto out;
 340         }
 341
 342         if (evict) {
 343                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0);
 344                 ret = nouveau_bo_validate(nvbo, false, false);
 345                 if (ret)
 346                         goto out;
 347         }
 348
 349         nvbo->pin_refcnt++;
 350         nouveau_bo_placement_set(nvbo, memtype, 0);
 351
 352         /* drop pin_refcnt temporarily, so we don't trip the assertion
 353          * in nouveau_bo_move() that makes sure we're not trying to
 354          * move a pinned buffer
 355          */
 356         nvbo->pin_refcnt--;
 357         ret = nouveau_bo_validate(nvbo, false, false);
 358         if (ret)
 359                 goto out;
 360         nvbo->pin_refcnt++;
 361
 362         switch (bo->mem.mem_type) {
 363         case TTM_PL_VRAM:
 364                 drm->gem.vram_available -= bo->mem.size;
 365                 break;
 366         case TTM_PL_TT:
 367                 drm->gem.gart_available -= bo->mem.size;
 368                 break;
 369         default:
 370                 break;
 371         }
 372
 373 out:
 374         if (force && ret)
 375                 nvbo->tile_flags |= NOUVEAU_GEM_TILE_NONCONTIG;
 376         ttm_bo_unreserve(bo);
 377         return ret;
 378 }
 379
 380 int
 381 nouveau_bo_unpin(struct nouveau_bo *nvbo)
 382 {
 383         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 384         struct ttm_buffer_object *bo = &nvbo->bo;
 385         int ret, ref;
 386
 387         ret = ttm_bo_reserve(bo, false, false, NULL);
 388         if (ret)
 389                 return ret;
 390
 391         ref = --nvbo->pin_refcnt;
 392         WARN_ON_ONCE(ref < 0);
 393         if (ref)
 394                 goto out;
 395
 396         nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
 397
 398         ret = nouveau_bo_validate(nvbo, false, false);
 399         if (ret == 0) {
 400                 switch (bo->mem.mem_type) {
 401                 case TTM_PL_VRAM:
 402                         drm->gem.vram_available += bo->mem.size;
 403                         break;
 404                 case TTM_PL_TT:
 405                         drm->gem.gart_available += bo->mem.size;
 406                         break;
 407                 default:
 408                         break;
 409                 }
 410         }
 411
 412 out:
 413         ttm_bo_unreserve(bo);
 414         return ret;
 415 }
 416
 417 int
 418 nouveau_bo_map(struct nouveau_bo *nvbo)
 419 {
 420         int ret;
 421
 422         ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
 423         if (ret)
 424                 return ret;
 425
 426         ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
 427
 428         ttm_bo_unreserve(&nvbo->bo);
 429         return ret;
 430 }
 431
 432 void
 433 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 434 {
 435         if (!nvbo)
 436                 return;
 437
 438         ttm_bo_kunmap(&nvbo->kmap);
 439 }
 440
 441 void
 442 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
 443 {
 444         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 445         struct nvkm_device *device = nvxx_device(&drm->device);
 446         struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
 447         int i;
 448
 449         if (!ttm_dma)
 450                 return;
 451
 452         /* Don't waste time looping if the object is coherent */
 453         if (nvbo->force_coherent)
 454                 return;
 455
 456         for (i = 0; i < ttm_dma->ttm.num_pages; i++)
 457                 dma_sync_single_for_device(device->dev, ttm_dma->dma_address[i],
 458                                            PAGE_SIZE, DMA_TO_DEVICE);
 459 }
 460
 461 void
 462 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
 463 {
 464         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 465         struct nvkm_device *device = nvxx_device(&drm->device);
 466         struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
 467         int i;
 468
 469         if (!ttm_dma)
 470                 return;
 471
 472         /* Don't waste time looping if the object is coherent */
 473         if (nvbo->force_coherent)
 474                 return;
 475
 476         for (i = 0; i < ttm_dma->ttm.num_pages; i++)
 477                 dma_sync_single_for_cpu(device->dev, ttm_dma->dma_address[i],
 478                                         PAGE_SIZE, DMA_FROM_DEVICE);
 479 }
 480
 481 int
 482 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
 483                     bool no_wait_gpu)
 484 {
 485         int ret;
 486
 487         ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
 488                               interruptible, no_wait_gpu);
 489         if (ret)
 490                 return ret;
 491
 492         nouveau_bo_sync_for_device(nvbo);
 493
 494         return 0;
 495 }
 496
 497 void
 498 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 499 {
 500         bool is_iomem;
 501         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 502
 503         mem += index;
 504
 505         if (is_iomem)
 506                 iowrite16_native(val, (void __force __iomem *)mem);
 507         else
 508                 *mem = val;
 509 }
 510
 511 u32
 512 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 513 {
 514         bool is_iomem;
 515         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 516
 517         mem += index;
 518
 519         if (is_iomem)
 520                 return ioread32_native((void __force __iomem *)mem);
 521         else
 522                 return *mem;
 523 }
 524
 525 void
 526 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 527 {
 528         bool is_iomem;
 529         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 530
 531         mem += index;
 532
 533         if (is_iomem)
 534                 iowrite32_native(val, (void __force __iomem *)mem);
 535         else
 536                 *mem = val;
 537 }
 538
 539 static struct ttm_tt *
 540 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
 541                       uint32_t page_flags, struct page *dummy_read)
 542 {
 543 #if IS_ENABLED(CONFIG_AGP)
 544         struct nouveau_drm *drm = nouveau_bdev(bdev);
 545
 546         if (drm->agp.bridge) {
 547                 return ttm_agp_tt_create(bdev, drm->agp.bridge, size,
 548                                          page_flags, dummy_read);
 549         }
 550 #endif
 551
 552         return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
 553 }
 554
 555 static int
 556 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 557 {
 558         /* We'll do this from user space. */
 559         return 0;
 560 }
 561
 562 static int
 563 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 564                          struct ttm_mem_type_manager *man)
 565 {
 566         struct nouveau_drm *drm = nouveau_bdev(bdev);
 567
 568         switch (type) {
 569         case TTM_PL_SYSTEM:
 570                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 571                 man->available_caching = TTM_PL_MASK_CACHING;
 572                 man->default_caching = TTM_PL_FLAG_CACHED;
 573                 break;
 574         case TTM_PL_VRAM:
 575                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 576                              TTM_MEMTYPE_FLAG_MAPPABLE;
 577                 man->available_caching = TTM_PL_FLAG_UNCACHED |
 578                                          TTM_PL_FLAG_WC;
 579                 man->default_caching = TTM_PL_FLAG_WC;
 580
 581                 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
 582                         /* Some BARs do not support being ioremapped WC */
 583                         if (nvxx_bar(&drm->device)->iomap_uncached) {
 584                                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 585                                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 586                         }
 587
 588                         man->func = &nouveau_vram_manager;
 589                         man->io_reserve_fastpath = false;
 590                         man->use_io_reserve_lru = true;
 591                 } else {
 592                         man->func = &ttm_bo_manager_func;
 593                 }
 594                 break;
 595         case TTM_PL_TT:
 596                 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA)
 597                         man->func = &nouveau_gart_manager;
 598                 else
 599                 if (!drm->agp.bridge)
 600                         man->func = &nv04_gart_manager;
 601                 else
 602                         man->func = &ttm_bo_manager_func;
 603
 604                 if (drm->agp.bridge) {
 605                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 606                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 607                                 TTM_PL_FLAG_WC;
 608                         man->default_caching = TTM_PL_FLAG_WC;
 609                 } else {
 610                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
 611                                      TTM_MEMTYPE_FLAG_CMA;
 612                         man->available_caching = TTM_PL_MASK_CACHING;
 613                         man->default_caching = TTM_PL_FLAG_CACHED;
 614                 }
 615
 616                 break;
 617         default:
 618                 return -EINVAL;
 619         }
 620         return 0;
 621 }
 622
 623 static void
 624 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 625 {
 626         struct nouveau_bo *nvbo = nouveau_bo(bo);
 627
 628         switch (bo->mem.mem_type) {
 629         case TTM_PL_VRAM:
 630                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
 631                                          TTM_PL_FLAG_SYSTEM);
 632                 break;
 633         default:
 634                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
 635                 break;
 636         }
 637
 638         *pl = nvbo->placement;
 639 }
 640
 641
 642 static int
 643 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
 644 {
 645         int ret = RING_SPACE(chan, 2);
 646         if (ret == 0) {
 647                 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
 648                 OUT_RING  (chan, handle & 0x0000ffff);
 649                 FIRE_RING (chan);
 650         }
 651         return ret;
 652 }
 653
 654 static int
 655 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 656                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 657 {
 658         struct nvkm_mem *node = old_mem->mm_node;
 659         int ret = RING_SPACE(chan, 10);
 660         if (ret == 0) {
 661                 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
 662                 OUT_RING  (chan, upper_32_bits(node->vma[0].offset));
 663                 OUT_RING  (chan, lower_32_bits(node->vma[0].offset));
 664                 OUT_RING  (chan, upper_32_bits(node->vma[1].offset));
 665                 OUT_RING  (chan, lower_32_bits(node->vma[1].offset));
 666                 OUT_RING  (chan, PAGE_SIZE);
 667                 OUT_RING  (chan, PAGE_SIZE);
 668                 OUT_RING  (chan, PAGE_SIZE);
 669                 OUT_RING  (chan, new_mem->num_pages);
 670                 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
 671         }
 672         return ret;
 673 }
 674
 675 static int
 676 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
 677 {
 678         int ret = RING_SPACE(chan, 2);
 679         if (ret == 0) {
 680                 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
 681                 OUT_RING  (chan, handle);
 682         }
 683         return ret;
 684 }
 685
 686 static int
 687 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 688                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 689 {
 690         struct nvkm_mem *node = old_mem->mm_node;
 691         u64 src_offset = node->vma[0].offset;
 692         u64 dst_offset = node->vma[1].offset;
 693         u32 page_count = new_mem->num_pages;
 694         int ret;
 695
 696         page_count = new_mem->num_pages;
 697         while (page_count) {
 698                 int line_count = (page_count > 8191) ? 8191 : page_count;
 699
 700                 ret = RING_SPACE(chan, 11);
 701                 if (ret)
 702                         return ret;
 703
 704                 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
 705                 OUT_RING  (chan, upper_32_bits(src_offset));
 706                 OUT_RING  (chan, lower_32_bits(src_offset));
 707                 OUT_RING  (chan, upper_32_bits(dst_offset));
 708                 OUT_RING  (chan, lower_32_bits(dst_offset));
 709                 OUT_RING  (chan, PAGE_SIZE);
 710                 OUT_RING  (chan, PAGE_SIZE);
 711                 OUT_RING  (chan, PAGE_SIZE);
 712                 OUT_RING  (chan, line_count);
 713                 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
 714                 OUT_RING  (chan, 0x00000110);
 715
 716                 page_count -= line_count;
 717                 src_offset += (PAGE_SIZE * line_count);
 718                 dst_offset += (PAGE_SIZE * line_count);
 719         }
 720
 721         return 0;
 722 }
 723
 724 static int
 725 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 726                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 727 {
 728         struct nvkm_mem *node = old_mem->mm_node;
 729         u64 src_offset = node->vma[0].offset;
 730         u64 dst_offset = node->vma[1].offset;
 731         u32 page_count = new_mem->num_pages;
 732         int ret;
 733
 734         page_count = new_mem->num_pages;
 735         while (page_count) {
 736                 int line_count = (page_count > 2047) ? 2047 : page_count;
 737
 738                 ret = RING_SPACE(chan, 12);
 739                 if (ret)
 740                         return ret;
 741
 742                 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
 743                 OUT_RING  (chan, upper_32_bits(dst_offset));
 744                 OUT_RING  (chan, lower_32_bits(dst_offset));
 745                 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
 746                 OUT_RING  (chan, upper_32_bits(src_offset));
 747                 OUT_RING  (chan, lower_32_bits(src_offset));
 748                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
 749                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
 750                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
 751                 OUT_RING  (chan, line_count);
 752                 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
 753                 OUT_RING  (chan, 0x00100110);
 754
 755                 page_count -= line_count;
 756                 src_offset += (PAGE_SIZE * line_count);
 757                 dst_offset += (PAGE_SIZE * line_count);
 758         }
 759
 760         return 0;
 761 }
 762
 763 static int
 764 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 765                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 766 {
 767         struct nvkm_mem *node = old_mem->mm_node;
 768         u64 src_offset = node->vma[0].offset;
 769         u64 dst_offset = node->vma[1].offset;
 770         u32 page_count = new_mem->num_pages;
 771         int ret;
 772
 773         page_count = new_mem->num_pages;
 774         while (page_count) {
 775                 int line_count = (page_count > 8191) ? 8191 : page_count;
 776
 777                 ret = RING_SPACE(chan, 11);
 778                 if (ret)
 779                         return ret;
 780
 781                 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
 782                 OUT_RING  (chan, upper_32_bits(src_offset));
 783                 OUT_RING  (chan, lower_32_bits(src_offset));
 784                 OUT_RING  (chan, upper_32_bits(dst_offset));
 785                 OUT_RING  (chan, lower_32_bits(dst_offset));
 786                 OUT_RING  (chan, PAGE_SIZE);
 787                 OUT_RING  (chan, PAGE_SIZE);
 788                 OUT_RING  (chan, PAGE_SIZE);
 789                 OUT_RING  (chan, line_count);
 790                 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
 791                 OUT_RING  (chan, 0x00000110);
 792
 793                 page_count -= line_count;
 794                 src_offset += (PAGE_SIZE * line_count);
 795                 dst_offset += (PAGE_SIZE * line_count);
 796         }
 797
 798         return 0;
 799 }
 800
 801 static int
 802 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 803                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 804 {
 805         struct nvkm_mem *node = old_mem->mm_node;
 806         int ret = RING_SPACE(chan, 7);
 807         if (ret == 0) {
 808                 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
 809                 OUT_RING  (chan, upper_32_bits(node->vma[0].offset));
 810                 OUT_RING  (chan, lower_32_bits(node->vma[0].offset));
 811                 OUT_RING  (chan, upper_32_bits(node->vma[1].offset));
 812                 OUT_RING  (chan, lower_32_bits(node->vma[1].offset));
 813                 OUT_RING  (chan, 0x00000000 /* COPY */);
 814                 OUT_RING  (chan, new_mem->num_pages << PAGE_SHIFT);
 815         }
 816         return ret;
 817 }
 818
 819 static int
 820 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 821                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 822 {
 823         struct nvkm_mem *node = old_mem->mm_node;
 824         int ret = RING_SPACE(chan, 7);
 825         if (ret == 0) {
 826                 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
 827                 OUT_RING  (chan, new_mem->num_pages << PAGE_SHIFT);
 828                 OUT_RING  (chan, upper_32_bits(node->vma[0].offset));
 829                 OUT_RING  (chan, lower_32_bits(node->vma[0].offset));
 830                 OUT_RING  (chan, upper_32_bits(node->vma[1].offset));
 831                 OUT_RING  (chan, lower_32_bits(node->vma[1].offset));
 832                 OUT_RING  (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
 833         }
 834         return ret;
 835 }
 836
 837 static int
 838 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
 839 {
 840         int ret = RING_SPACE(chan, 6);
 841         if (ret == 0) {
 842                 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
 843                 OUT_RING  (chan, handle);
 844                 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
 845                 OUT_RING  (chan, chan->drm->ntfy.handle);
 846                 OUT_RING  (chan, chan->vram.handle);
 847                 OUT_RING  (chan, chan->vram.handle);
 848         }
 849
 850         return ret;
 851 }
 852
 853 static int
 854 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 855                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 856 {
 857         struct nvkm_mem *node = old_mem->mm_node;
 858         u64 length = (new_mem->num_pages << PAGE_SHIFT);
 859         u64 src_offset = node->vma[0].offset;
 860         u64 dst_offset = node->vma[1].offset;
 861         int src_tiled = !!node->memtype;
 862         int dst_tiled = !!((struct nvkm_mem *)new_mem->mm_node)->memtype;
 863         int ret;
 864
 865         while (length) {
 866                 u32 amount, stride, height;
 867
 868                 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
 869                 if (ret)
 870                         return ret;
 871
 872                 amount  = min(length, (u64)(4 * 1024 * 1024));
 873                 stride  = 16 * 4;
 874                 height  = amount / stride;
 875
 876                 if (src_tiled) {
 877                         BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
 878                         OUT_RING  (chan, 0);
 879                         OUT_RING  (chan, 0);
 880                         OUT_RING  (chan, stride);
 881                         OUT_RING  (chan, height);
 882                         OUT_RING  (chan, 1);
 883                         OUT_RING  (chan, 0);
 884                         OUT_RING  (chan, 0);
 885                 } else {
 886                         BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
 887                         OUT_RING  (chan, 1);
 888                 }
 889                 if (dst_tiled) {
 890                         BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
 891                         OUT_RING  (chan, 0);
 892                         OUT_RING  (chan, 0);
 893                         OUT_RING  (chan, stride);
 894                         OUT_RING  (chan, height);
 895                         OUT_RING  (chan, 1);
 896                         OUT_RING  (chan, 0);
 897                         OUT_RING  (chan, 0);
 898                 } else {
 899                         BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
 900                         OUT_RING  (chan, 1);
 901                 }
 902
 903                 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
 904                 OUT_RING  (chan, upper_32_bits(src_offset));
 905                 OUT_RING  (chan, upper_32_bits(dst_offset));
 906                 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
 907                 OUT_RING  (chan, lower_32_bits(src_offset));
 908                 OUT_RING  (chan, lower_32_bits(dst_offset));
 909                 OUT_RING  (chan, stride);
 910                 OUT_RING  (chan, stride);
 911                 OUT_RING  (chan, stride);
 912                 OUT_RING  (chan, height);
 913                 OUT_RING  (chan, 0x00000101);
 914                 OUT_RING  (chan, 0x00000000);
 915                 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 916                 OUT_RING  (chan, 0);
 917
 918                 length -= amount;
 919                 src_offset += amount;
 920                 dst_offset += amount;
 921         }
 922
 923         return 0;
 924 }
 925
 926 static int
 927 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
 928 {
 929         int ret = RING_SPACE(chan, 4);
 930         if (ret == 0) {
 931                 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
 932                 OUT_RING  (chan, handle);
 933                 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
 934                 OUT_RING  (chan, chan->drm->ntfy.handle);
 935         }
 936
 937         return ret;
 938 }
 939
 940 static inline uint32_t
 941 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
 942                       struct nouveau_channel *chan, struct ttm_mem_reg *mem)
 943 {
 944         if (mem->mem_type == TTM_PL_TT)
 945                 return NvDmaTT;
 946         return chan->vram.handle;
 947 }
 948
 949 static int
 950 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 951                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 952 {
 953         u32 src_offset = old_mem->start << PAGE_SHIFT;
 954         u32 dst_offset = new_mem->start << PAGE_SHIFT;
 955         u32 page_count = new_mem->num_pages;
 956         int ret;
 957
 958         ret = RING_SPACE(chan, 3);
 959         if (ret)
 960                 return ret;
 961
 962         BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
 963         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
 964         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
 965
 966         page_count = new_mem->num_pages;
 967         while (page_count) {
 968                 int line_count = (page_count > 2047) ? 2047 : page_count;
 969
 970                 ret = RING_SPACE(chan, 11);
 971                 if (ret)
 972                         return ret;
 973
 974                 BEGIN_NV04(chan, NvSubCopy,
 975                                  NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 976                 OUT_RING  (chan, src_offset);
 977                 OUT_RING  (chan, dst_offset);
 978                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
 979                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
 980                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
 981                 OUT_RING  (chan, line_count);
 982                 OUT_RING  (chan, 0x00000101);
 983                 OUT_RING  (chan, 0x00000000);
 984                 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 985                 OUT_RING  (chan, 0);
 986
 987                 page_count -= line_count;
 988                 src_offset += (PAGE_SIZE * line_count);
 989                 dst_offset += (PAGE_SIZE * line_count);
 990         }
 991
 992         return 0;
 993 }
 994
 995 static int
 996 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
 997                      struct ttm_mem_reg *mem)
 998 {
 999         struct nvkm_mem *old_node = bo->mem.mm_node;
1000         struct nvkm_mem *new_node = mem->mm_node;
1001         u64 size = (u64)mem->num_pages << PAGE_SHIFT;
1002         int ret;
1003
1004         ret = nvkm_vm_get(drm->client.vm, size, old_node->page_shift,
1005                           NV_MEM_ACCESS_RW, &old_node->vma[0]);
1006         if (ret)
1007                 return ret;
1008
1009         ret = nvkm_vm_get(drm->client.vm, size, new_node->page_shift,
1010                           NV_MEM_ACCESS_RW, &old_node->vma[1]);
1011         if (ret) {
1012                 nvkm_vm_put(&old_node->vma[0]);
1013                 return ret;
1014         }
1015
1016         nvkm_vm_map(&old_node->vma[0], old_node);
1017         nvkm_vm_map(&old_node->vma[1], new_node);
1018         return 0;
1019 }
1020
1021 static int
1022 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
1023                      bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1024 {
1025         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1026         struct nouveau_channel *chan = drm->ttm.chan;
1027         struct nouveau_cli *cli = (void *)chan->user.client;
1028         struct nouveau_fence *fence;
1029         int ret;
1030
1031         /* create temporary vmas for the transfer and attach them to the
1032          * old nvkm_mem node, these will get cleaned up after ttm has
1033          * destroyed the ttm_mem_reg
1034          */
1035         if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1036                 ret = nouveau_bo_move_prep(drm, bo, new_mem);
1037                 if (ret)
1038                         return ret;
1039         }
1040
1041         mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
1042         ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
1043         if (ret == 0) {
1044                 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
1045                 if (ret == 0) {
1046                         ret = nouveau_fence_new(chan, false, &fence);
1047                         if (ret == 0) {
1048                                 ret = ttm_bo_move_accel_cleanup(bo,
1049                                                                 &fence->base,
1050                                                                 evict,
1051                                                                 new_mem);
1052                                 nouveau_fence_unref(&fence);
1053                         }
1054                 }
1055         }
1056         mutex_unlock(&cli->mutex);
1057         return ret;
1058 }
1059
1060 void
1061 nouveau_bo_move_init(struct nouveau_drm *drm)
1062 {
1063         static const struct {
1064                 const char *name;
1065                 int engine;
1066                 s32 oclass;
1067                 int (*exec)(struct nouveau_channel *,
1068                             struct ttm_buffer_object *,
1069                             struct ttm_mem_reg *, struct ttm_mem_reg *);
1070                 int (*init)(struct nouveau_channel *, u32 handle);
1071         } _methods[] = {
1072                 {  "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
1073                 {  "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
1074                 {  "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
1075                 {  "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1076                 {  "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
1077                 {  "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1078                 {  "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1079                 {  "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1080                 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1081                 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1082                 {  "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1083                 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1084                 {  "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1085                 {  "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1086                 {  "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1087                 {},
1088                 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1089         }, *mthd = _methods;
1090         const char *name = "CPU";
1091         int ret;
1092
1093         do {
1094                 struct nouveau_channel *chan;
1095
1096                 if (mthd->engine)
1097                         chan = drm->cechan;
1098                 else
1099                         chan = drm->channel;
1100                 if (chan == NULL)
1101                         continue;
1102
1103                 ret = nvif_object_init(&chan->user,
1104                                        mthd->oclass | (mthd->engine << 16),
1105                                        mthd->oclass, NULL, 0,
1106                                        &drm->ttm.copy);
1107                 if (ret == 0) {
1108                         ret = mthd->init(chan, drm->ttm.copy.handle);
1109                         if (ret) {
1110                                 nvif_object_fini(&drm->ttm.copy);
1111                                 continue;
1112                         }
1113
1114                         drm->ttm.move = mthd->exec;
1115                         drm->ttm.chan = chan;
1116                         name = mthd->name;
1117                         break;
1118                 }
1119         } while ((++mthd)->exec);
1120
1121         NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1122 }
1123
1124 static int
1125 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1126                       bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1127 {
1128         struct ttm_place placement_memtype = {
1129                 .fpfn = 0,
1130                 .lpfn = 0,
1131                 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1132         };
1133         struct ttm_placement placement;
1134         struct ttm_mem_reg tmp_mem;
1135         int ret;
1136
1137         placement.num_placement = placement.num_busy_placement = 1;
1138         placement.placement = placement.busy_placement = &placement_memtype;
1139
1140         tmp_mem = *new_mem;
1141         tmp_mem.mm_node = NULL;
1142         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1143         if (ret)
1144                 return ret;
1145
1146         ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1147         if (ret)
1148                 goto out;
1149
1150         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1151         if (ret)
1152                 goto out;
1153
1154         ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1155 out:
1156         ttm_bo_mem_put(bo, &tmp_mem);
1157         return ret;
1158 }
1159
1160 static int
1161 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1162                       bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1163 {
1164         struct ttm_place placement_memtype = {
1165                 .fpfn = 0,
1166                 .lpfn = 0,
1167                 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1168         };
1169         struct ttm_placement placement;
1170         struct ttm_mem_reg tmp_mem;
1171         int ret;
1172
1173         placement.num_placement = placement.num_busy_placement = 1;
1174         placement.placement = placement.busy_placement = &placement_memtype;
1175
1176         tmp_mem = *new_mem;
1177         tmp_mem.mm_node = NULL;
1178         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1179         if (ret)
1180                 return ret;
1181
1182         ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1183         if (ret)
1184                 goto out;
1185
1186         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1187         if (ret)
1188                 goto out;
1189
1190 out:
1191         ttm_bo_mem_put(bo, &tmp_mem);
1192         return ret;
1193 }
1194
1195 static void
1196 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1197 {
1198         struct nouveau_bo *nvbo = nouveau_bo(bo);
1199         struct nvkm_vma *vma;
1200
1201         /* ttm can now (stupidly) pass the driver bos it didn't create... */
1202         if (bo->destroy != nouveau_bo_del_ttm)
1203                 return;
1204
1205         list_for_each_entry(vma, &nvbo->vma_list, head) {
1206                 if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
1207                               (new_mem->mem_type == TTM_PL_VRAM ||
1208                                nvbo->page_shift != vma->vm->mmu->lpg_shift)) {
1209                         nvkm_vm_map(vma, new_mem->mm_node);
1210                 } else {
1211                         nvkm_vm_unmap(vma);
1212                 }
1213         }
1214 }
1215
1216 static int
1217 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1218                    struct nouveau_drm_tile **new_tile)
1219 {
1220         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1221         struct drm_device *dev = drm->dev;
1222         struct nouveau_bo *nvbo = nouveau_bo(bo);
1223         u64 offset = new_mem->start << PAGE_SHIFT;
1224
1225         *new_tile = NULL;
1226         if (new_mem->mem_type != TTM_PL_VRAM)
1227                 return 0;
1228
1229         if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1230                 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1231                                                 nvbo->tile_mode,
1232                                                 nvbo->tile_flags);
1233         }
1234
1235         return 0;
1236 }
1237
1238 static void
1239 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1240                       struct nouveau_drm_tile *new_tile,
1241                       struct nouveau_drm_tile **old_tile)
1242 {
1243         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1244         struct drm_device *dev = drm->dev;
1245         struct fence *fence = reservation_object_get_excl(bo->resv);
1246
1247         nv10_bo_put_tile_region(dev, *old_tile, fence);
1248         *old_tile = new_tile;
1249 }
1250
1251 static int
1252 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1253                 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1254 {
1255         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1256         struct nouveau_bo *nvbo = nouveau_bo(bo);
1257         struct ttm_mem_reg *old_mem = &bo->mem;
1258         struct nouveau_drm_tile *new_tile = NULL;
1259         int ret = 0;
1260
1261         ret = ttm_bo_wait(bo, intr, no_wait_gpu);
1262         if (ret)
1263                 return ret;
1264
1265         if (nvbo->pin_refcnt)
1266                 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1267
1268         if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1269                 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1270                 if (ret)
1271                         return ret;
1272         }
1273
1274         /* Fake bo copy. */
1275         if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1276                 BUG_ON(bo->mem.mm_node != NULL);
1277                 bo->mem = *new_mem;
1278                 new_mem->mm_node = NULL;
1279                 goto out;
1280         }
1281
1282         /* Hardware assisted copy. */
1283         if (drm->ttm.move) {
1284                 if (new_mem->mem_type == TTM_PL_SYSTEM)
1285                         ret = nouveau_bo_move_flipd(bo, evict, intr,
1286                                                     no_wait_gpu, new_mem);
1287                 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1288                         ret = nouveau_bo_move_flips(bo, evict, intr,
1289                                                     no_wait_gpu, new_mem);
1290                 else
1291                         ret = nouveau_bo_move_m2mf(bo, evict, intr,
1292                                                    no_wait_gpu, new_mem);
1293                 if (!ret)
1294                         goto out;
1295         }
1296
1297         /* Fallback to software copy. */
1298         ret = ttm_bo_wait(bo, intr, no_wait_gpu);
1299         if (ret == 0)
1300                 ret = ttm_bo_move_memcpy(bo, evict, intr, no_wait_gpu, new_mem);
1301
1302 out:
1303         if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1304                 if (ret)
1305                         nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1306                 else
1307                         nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1308         }
1309
1310         return ret;
1311 }
1312
1313 static int
1314 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1315 {
1316         struct nouveau_bo *nvbo = nouveau_bo(bo);
1317
1318         return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp);
1319 }
1320
1321 static int
1322 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1323 {
1324         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1325         struct nouveau_drm *drm = nouveau_bdev(bdev);
1326         struct nvkm_device *device = nvxx_device(&drm->device);
1327         struct nvkm_mem *node = mem->mm_node;
1328         int ret;
1329
1330         mem->bus.addr = NULL;
1331         mem->bus.offset = 0;
1332         mem->bus.size = mem->num_pages << PAGE_SHIFT;
1333         mem->bus.base = 0;
1334         mem->bus.is_iomem = false;
1335         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1336                 return -EINVAL;
1337         switch (mem->mem_type) {
1338         case TTM_PL_SYSTEM:
1339                 /* System memory */
1340                 return 0;
1341         case TTM_PL_TT:
1342 #if IS_ENABLED(CONFIG_AGP)
1343                 if (drm->agp.bridge) {
1344                         mem->bus.offset = mem->start << PAGE_SHIFT;
1345                         mem->bus.base = drm->agp.base;
1346                         mem->bus.is_iomem = !drm->agp.cma;
1347                 }
1348 #endif
1349                 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype)
1350                         /* untiled */
1351                         break;
1352                 /* fallthrough, tiled memory */
1353         case TTM_PL_VRAM:
1354                 mem->bus.offset = mem->start << PAGE_SHIFT;
1355                 mem->bus.base = device->func->resource_addr(device, 1);
1356                 mem->bus.is_iomem = true;
1357                 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1358                         struct nvkm_bar *bar = nvxx_bar(&drm->device);
1359                         int page_shift = 12;
1360                         if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI)
1361                                 page_shift = node->page_shift;
1362
1363                         ret = nvkm_bar_umap(bar, node->size << 12, page_shift,
1364                                             &node->bar_vma);
1365                         if (ret)
1366                                 return ret;
1367
1368                         nvkm_vm_map(&node->bar_vma, node);
1369                         mem->bus.offset = node->bar_vma.offset;
1370                 }
1371                 break;
1372         default:
1373                 return -EINVAL;
1374         }
1375         return 0;
1376 }
1377
1378 static void
1379 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1380 {
1381         struct nvkm_mem *node = mem->mm_node;
1382
1383         if (!node->bar_vma.node)
1384                 return;
1385
1386         nvkm_vm_unmap(&node->bar_vma);
1387         nvkm_vm_put(&node->bar_vma);
1388 }
1389
1390 static int
1391 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1392 {
1393         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1394         struct nouveau_bo *nvbo = nouveau_bo(bo);
1395         struct nvkm_device *device = nvxx_device(&drm->device);
1396         u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1397         int i, ret;
1398
1399         /* as long as the bo isn't in vram, and isn't tiled, we've got
1400          * nothing to do here.
1401          */
1402         if (bo->mem.mem_type != TTM_PL_VRAM) {
1403                 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1404                     !nouveau_bo_tile_layout(nvbo))
1405                         return 0;
1406
1407                 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1408                         nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1409
1410                         ret = nouveau_bo_validate(nvbo, false, false);
1411                         if (ret)
1412                                 return ret;
1413                 }
1414                 return 0;
1415         }
1416
1417         /* make sure bo is in mappable vram */
1418         if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1419             bo->mem.start + bo->mem.num_pages < mappable)
1420                 return 0;
1421
1422         for (i = 0; i < nvbo->placement.num_placement; ++i) {
1423                 nvbo->placements[i].fpfn = 0;
1424                 nvbo->placements[i].lpfn = mappable;
1425         }
1426
1427         for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1428                 nvbo->busy_placements[i].fpfn = 0;
1429                 nvbo->busy_placements[i].lpfn = mappable;
1430         }
1431
1432         nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1433         return nouveau_bo_validate(nvbo, false, false);
1434 }
1435
1436 static int
1437 nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1438 {
1439         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1440         struct nouveau_drm *drm;
1441         struct nvkm_device *device;
1442         struct drm_device *dev;
1443         struct device *pdev;
1444         unsigned i;
1445         int r;
1446         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1447
1448         if (ttm->state != tt_unpopulated)
1449                 return 0;
1450
1451         if (slave && ttm->sg) {
1452                 /* make userspace faulting work */
1453                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1454                                                  ttm_dma->dma_address, ttm->num_pages);
1455                 ttm->state = tt_unbound;
1456                 return 0;
1457         }
1458
1459         drm = nouveau_bdev(ttm->bdev);
1460         device = nvxx_device(&drm->device);
1461         dev = drm->dev;
1462         pdev = device->dev;
1463
1464 #if IS_ENABLED(CONFIG_AGP)
1465         if (drm->agp.bridge) {
1466                 return ttm_agp_tt_populate(ttm);
1467         }
1468 #endif
1469
1470 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1471         if (swiotlb_nr_tbl()) {
1472                 return ttm_dma_populate((void *)ttm, dev->dev);
1473         }
1474 #endif
1475
1476         r = ttm_pool_populate(ttm);
1477         if (r) {
1478                 return r;
1479         }
1480
1481         for (i = 0; i < ttm->num_pages; i++) {
1482                 dma_addr_t addr;
1483
1484                 addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE,
1485                                     DMA_BIDIRECTIONAL);
1486
1487                 if (dma_mapping_error(pdev, addr)) {
1488                         while (i--) {
1489                                 dma_unmap_page(pdev, ttm_dma->dma_address[i],
1490                                                PAGE_SIZE, DMA_BIDIRECTIONAL);
1491                                 ttm_dma->dma_address[i] = 0;
1492                         }
1493                         ttm_pool_unpopulate(ttm);
1494                         return -EFAULT;
1495                 }
1496
1497                 ttm_dma->dma_address[i] = addr;
1498         }
1499         return 0;
1500 }
1501
1502 static void
1503 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1504 {
1505         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1506         struct nouveau_drm *drm;
1507         struct nvkm_device *device;
1508         struct drm_device *dev;
1509         struct device *pdev;
1510         unsigned i;
1511         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1512
1513         if (slave)
1514                 return;
1515
1516         drm = nouveau_bdev(ttm->bdev);
1517         device = nvxx_device(&drm->device);
1518         dev = drm->dev;
1519         pdev = device->dev;
1520
1521 #if IS_ENABLED(CONFIG_AGP)
1522         if (drm->agp.bridge) {
1523                 ttm_agp_tt_unpopulate(ttm);
1524                 return;
1525         }
1526 #endif
1527
1528 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1529         if (swiotlb_nr_tbl()) {
1530                 ttm_dma_unpopulate((void *)ttm, dev->dev);
1531                 return;
1532         }
1533 #endif
1534
1535         for (i = 0; i < ttm->num_pages; i++) {
1536                 if (ttm_dma->dma_address[i]) {
1537                         dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE,
1538                                        DMA_BIDIRECTIONAL);
1539                 }
1540         }
1541
1542         ttm_pool_unpopulate(ttm);
1543 }
1544
1545 void
1546 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1547 {
1548         struct reservation_object *resv = nvbo->bo.resv;
1549
1550         if (exclusive)
1551                 reservation_object_add_excl_fence(resv, &fence->base);
1552         else if (fence)
1553                 reservation_object_add_shared_fence(resv, &fence->base);
1554 }
1555
1556 struct ttm_bo_driver nouveau_bo_driver = {
1557         .ttm_tt_create = &nouveau_ttm_tt_create,
1558         .ttm_tt_populate = &nouveau_ttm_tt_populate,
1559         .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1560         .invalidate_caches = nouveau_bo_invalidate_caches,
1561         .init_mem_type = nouveau_bo_init_mem_type,
1562         .evict_flags = nouveau_bo_evict_flags,
1563         .move_notify = nouveau_bo_move_ntfy,
1564         .move = nouveau_bo_move,
1565         .verify_access = nouveau_bo_verify_access,
1566         .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1567         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1568         .io_mem_free = &nouveau_ttm_io_mem_free,
1569         .lru_tail = &ttm_bo_default_lru_tail,
1570         .swap_lru_tail = &ttm_bo_default_swap_lru_tail,
1571 };
1572
1573 struct nvkm_vma *
1574 nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nvkm_vm *vm)
1575 {
1576         struct nvkm_vma *vma;
1577         list_for_each_entry(vma, &nvbo->vma_list, head) {
1578                 if (vma->vm == vm)
1579                         return vma;
1580         }
1581
1582         return NULL;
1583 }
1584
1585 int
1586 nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nvkm_vm *vm,
1587                    struct nvkm_vma *vma)
1588 {
1589         const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1590         int ret;
1591
1592         ret = nvkm_vm_get(vm, size, nvbo->page_shift,
1593                              NV_MEM_ACCESS_RW, vma);
1594         if (ret)
1595                 return ret;
1596
1597         if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
1598             (nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
1599              nvbo->page_shift != vma->vm->mmu->lpg_shift))
1600                 nvkm_vm_map(vma, nvbo->bo.mem.mm_node);
1601
1602         list_add_tail(&vma->head, &nvbo->vma_list);
1603         vma->refcount = 1;
1604         return 0;
1605 }
1606
1607 void
1608 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nvkm_vma *vma)
1609 {
1610         if (vma->node) {
1611                 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1612                         nvkm_vm_unmap(vma);
1613                 nvkm_vm_put(vma);
1614                 list_del(&vma->head);
1615         }
1616 }