1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __NVIF_CLASS_H__
3 #define __NVIF_CLASS_H__
5 /* these class numbers are made up by us, and not nvidia-assigned */
6 #define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000
8 #define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001
10 #define NVIF_CLASS_PERFMON /* if0002.h */ -0x00000002
11 #define NVIF_CLASS_PERFDOM /* if0003.h */ -0x00000003
13 #define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004
14 #define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005
15 #define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006
16 #define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007
18 #define NVIF_CLASS_MMU /* if0008.h */ 0x80000008
19 #define NVIF_CLASS_MMU_NV04 /* if0008.h */ 0x80000009
20 #define NVIF_CLASS_MMU_NV50 /* if0008.h */ 0x80005009
21 #define NVIF_CLASS_MMU_GF100 /* if0008.h */ 0x80009009
23 #define NVIF_CLASS_MEM /* if000a.h */ 0x8000000a
24 #define NVIF_CLASS_MEM_NV04 /* if000b.h */ 0x8000000b
25 #define NVIF_CLASS_MEM_NV50 /* if500b.h */ 0x8000500b
26 #define NVIF_CLASS_MEM_GF100 /* if900b.h */ 0x8000900b
28 #define NVIF_CLASS_VMM /* if000c.h */ 0x8000000c
29 #define NVIF_CLASS_VMM_NV04 /* if000d.h */ 0x8000000d
30 #define NVIF_CLASS_VMM_NV50 /* if500d.h */ 0x8000500d
31 #define NVIF_CLASS_VMM_GF100 /* if900d.h */ 0x8000900d
32 #define NVIF_CLASS_VMM_GM200 /* ifb00d.h */ 0x8000b00d
33 #define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d
35 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
36 #define NV_NULL_CLASS 0x00000030
38 #define NV_DEVICE /* cl0080.h */ 0x00000080
40 #define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002
41 #define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003
42 #define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d
44 #define NV50_TWOD 0x0000502d
45 #define FERMI_TWOD_A 0x0000902d
47 #define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
48 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
50 #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
51 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
53 #define NV04_DISP /* cl0046.h */ 0x00000046
55 #define VOLTA_USERMODE_A 0x0000c361
57 #define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b
58 #define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e
59 #define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e
60 #define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e
61 #define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e
62 #define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e
64 #define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f
65 #define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f
66 #define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f
67 #define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f
68 #define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f
69 #define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f
70 #define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f
71 #define VOLTA_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c36f
72 #define TURING_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c46f
74 #define NV50_DISP /* cl5070.h */ 0x00005070
75 #define G82_DISP /* cl5070.h */ 0x00008270
76 #define GT200_DISP /* cl5070.h */ 0x00008370
77 #define GT214_DISP /* cl5070.h */ 0x00008570
78 #define GT206_DISP /* cl5070.h */ 0x00008870
79 #define GF110_DISP /* cl5070.h */ 0x00009070
80 #define GK104_DISP /* cl5070.h */ 0x00009170
81 #define GK110_DISP /* cl5070.h */ 0x00009270
82 #define GM107_DISP /* cl5070.h */ 0x00009470
83 #define GM200_DISP /* cl5070.h */ 0x00009570
84 #define GP100_DISP /* cl5070.h */ 0x00009770
85 #define GP102_DISP /* cl5070.h */ 0x00009870
86 #define GV100_DISP /* cl5070.h */ 0x0000c370
87 #define TU102_DISP /* cl5070.h */ 0x0000c570
89 #define NV31_MPEG 0x00003174
90 #define G82_MPEG 0x00008274
92 #define NV74_VP2 0x00007476
94 #define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a
95 #define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a
96 #define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a
97 #define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a
98 #define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a
99 #define GV100_DISP_CURSOR /* cl507a.h */ 0x0000c37a
100 #define TU102_DISP_CURSOR /* cl507a.h */ 0x0000c57a
102 #define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b
103 #define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b
104 #define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b
105 #define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b
106 #define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b
108 #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c37b
109 #define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c57b
111 #define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c
112 #define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c
113 #define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c
114 #define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c
115 #define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c
116 #define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c
117 #define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c
119 #define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d
120 #define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d
121 #define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d
122 #define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d
123 #define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d
124 #define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d
125 #define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d
126 #define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d
127 #define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d
128 #define GM200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d
129 #define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d
130 #define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d
131 #define GV100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c37d
132 #define TU102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c57d
134 #define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e
135 #define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e
136 #define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e
137 #define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e
138 #define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e
139 #define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e
141 #define GV100_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c37e
142 #define TU102_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c57e
144 #define NV50_TESLA 0x00005097
145 #define G82_TESLA 0x00008297
146 #define GT200_TESLA 0x00008397
147 #define GT214_TESLA 0x00008597
148 #define GT21A_TESLA 0x00008697
150 #define FERMI_A /* cl9097.h */ 0x00009097
151 #define FERMI_B /* cl9097.h */ 0x00009197
152 #define FERMI_C /* cl9097.h */ 0x00009297
154 #define KEPLER_A /* cl9097.h */ 0x0000a097
155 #define KEPLER_B /* cl9097.h */ 0x0000a197
156 #define KEPLER_C /* cl9097.h */ 0x0000a297
158 #define MAXWELL_A /* cl9097.h */ 0x0000b097
159 #define MAXWELL_B /* cl9097.h */ 0x0000b197
161 #define PASCAL_A /* cl9097.h */ 0x0000c097
162 #define PASCAL_B /* cl9097.h */ 0x0000c197
164 #define VOLTA_A /* cl9097.h */ 0x0000c397
166 #define NV74_BSP 0x000074b0
168 #define GT212_MSVLD 0x000085b1
169 #define IGT21A_MSVLD 0x000086b1
170 #define G98_MSVLD 0x000088b1
171 #define GF100_MSVLD 0x000090b1
172 #define GK104_MSVLD 0x000095b1
174 #define GT212_MSPDEC 0x000085b2
175 #define G98_MSPDEC 0x000088b2
176 #define GF100_MSPDEC 0x000090b2
177 #define GK104_MSPDEC 0x000095b2
179 #define GT212_MSPPP 0x000085b3
180 #define G98_MSPPP 0x000088b3
181 #define GF100_MSPPP 0x000090b3
183 #define G98_SEC 0x000088b4
185 #define GT212_DMA 0x000085b5
186 #define FERMI_DMA 0x000090b5
187 #define KEPLER_DMA_COPY_A 0x0000a0b5
188 #define MAXWELL_DMA_COPY_A 0x0000b0b5
189 #define PASCAL_DMA_COPY_A 0x0000c0b5
190 #define PASCAL_DMA_COPY_B 0x0000c1b5
191 #define VOLTA_DMA_COPY_A 0x0000c3b5
192 #define TURING_DMA_COPY_A 0x0000c5b5
194 #define FERMI_DECOMPRESS 0x000090b8
196 #define NV50_COMPUTE 0x000050c0
197 #define GT214_COMPUTE 0x000085c0
198 #define FERMI_COMPUTE_A 0x000090c0
199 #define FERMI_COMPUTE_B 0x000091c0
200 #define KEPLER_COMPUTE_A 0x0000a0c0
201 #define KEPLER_COMPUTE_B 0x0000a1c0
202 #define MAXWELL_COMPUTE_A 0x0000b0c0
203 #define MAXWELL_COMPUTE_B 0x0000b1c0
204 #define PASCAL_COMPUTE_A 0x0000c0c0
205 #define PASCAL_COMPUTE_B 0x0000c1c0
206 #define VOLTA_COMPUTE_A 0x0000c3c0
208 #define NV74_CIPHER 0x000074c1