2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
31 #include <linux/dma-mapping.h>
32 #include <linux/hdmi.h>
33 #include <linux/component.h>
35 #include <drm/drm_atomic.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_dp_helper.h>
38 #include <drm/drm_edid.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_plane_helper.h>
41 #include <drm/drm_probe_helper.h>
42 #include <drm/drm_scdc_helper.h>
43 #include <drm/drm_vblank.h>
45 #include <nvif/push507c.h>
47 #include <nvif/class.h>
48 #include <nvif/cl0002.h>
49 #include <nvif/cl5070.h>
50 #include <nvif/cl507d.h>
51 #include <nvif/event.h>
52 #include <nvif/timer.h>
54 #include <nvhw/class/cl507c.h>
55 #include <nvhw/class/cl507d.h>
56 #include <nvhw/class/cl837d.h>
57 #include <nvhw/class/cl887d.h>
58 #include <nvhw/class/cl907d.h>
59 #include <nvhw/class/cl917d.h>
61 #include "nouveau_drv.h"
62 #include "nouveau_dma.h"
63 #include "nouveau_gem.h"
64 #include "nouveau_connector.h"
65 #include "nouveau_encoder.h"
66 #include "nouveau_fence.h"
67 #include "nouveau_fbcon.h"
69 #include <subdev/bios/dp.h>
71 /******************************************************************************
73 *****************************************************************************/
76 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
77 const s32 *oclass, u8 head, void *data, u32 size,
78 struct nv50_chan *chan)
80 struct nvif_sclass *sclass;
83 chan->device = device;
85 ret = n = nvif_object_sclass_get(disp, &sclass);
90 for (i = 0; i < n; i++) {
91 if (sclass[i].oclass == oclass[0]) {
92 ret = nvif_object_ctor(disp, "kmsChan", 0,
93 oclass[0], data, size,
96 nvif_object_map(&chan->user, NULL, 0);
97 nvif_object_sclass_put(&sclass);
104 nvif_object_sclass_put(&sclass);
109 nv50_chan_destroy(struct nv50_chan *chan)
111 nvif_object_dtor(&chan->user);
114 /******************************************************************************
116 *****************************************************************************/
119 nv50_dmac_destroy(struct nv50_dmac *dmac)
121 nvif_object_dtor(&dmac->vram);
122 nvif_object_dtor(&dmac->sync);
124 nv50_chan_destroy(&dmac->base);
126 nvif_mem_dtor(&dmac->_push.mem);
130 nv50_dmac_kick(struct nvif_push *push)
132 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
134 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
135 if (dmac->put != dmac->cur) {
136 /* Push buffer fetches are not coherent with BAR1, we need to ensure
137 * writes have been flushed right through to VRAM before writing PUT.
139 if (dmac->push->mem.type & NVIF_MEM_VRAM) {
140 struct nvif_device *device = dmac->base.device;
141 nvif_wr32(&device->object, 0x070000, 0x00000001);
142 nvif_msec(device, 2000,
143 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
148 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
149 dmac->put = dmac->cur;
152 push->bgn = push->cur;
156 nv50_dmac_free(struct nv50_dmac *dmac)
158 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
159 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
160 return get - dmac->cur - 5;
161 return dmac->max - dmac->cur;
165 nv50_dmac_wind(struct nv50_dmac *dmac)
167 /* Wait for GET to depart from the beginning of the push buffer to
168 * prevent writing PUT == GET, which would be ignored by HW.
170 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
172 /* Corner-case, HW idle, but non-committed work pending. */
174 nv50_dmac_kick(dmac->push);
176 if (nvif_msec(dmac->base.device, 2000,
177 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
183 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
189 nv50_dmac_wait(struct nvif_push *push, u32 size)
191 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
194 if (WARN_ON(size > dmac->max))
197 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
198 if (dmac->cur + size >= dmac->max) {
199 int ret = nv50_dmac_wind(dmac);
203 push->cur = dmac->_push.mem.object.map.ptr;
204 push->cur = push->cur + dmac->cur;
205 nv50_dmac_kick(push);
208 if (nvif_msec(dmac->base.device, 2000,
209 if ((free = nv50_dmac_free(dmac)) >= size)
216 push->bgn = dmac->_push.mem.object.map.ptr;
217 push->bgn = push->bgn + dmac->cur;
218 push->cur = push->bgn;
219 push->end = push->cur + free;
223 MODULE_PARM_DESC(kms_vram_pushbuf, "Place EVO/NVD push buffers in VRAM (default: auto)");
224 static int nv50_dmac_vram_pushbuf = -1;
225 module_param_named(kms_vram_pushbuf, nv50_dmac_vram_pushbuf, int, 0400);
228 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
229 const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf,
230 struct nv50_dmac *dmac)
232 struct nouveau_cli *cli = (void *)device->object.client;
233 struct nv50_disp_core_channel_dma_v0 *args = data;
234 u8 type = NVIF_MEM_COHERENT;
237 mutex_init(&dmac->lock);
239 /* Pascal added support for 47-bit physical addresses, but some
240 * parts of EVO still only accept 40-bit PAs.
242 * To avoid issues on systems with large amounts of RAM, and on
243 * systems where an IOMMU maps pages at a high address, we need
244 * to allocate push buffers in VRAM instead.
246 * This appears to match NVIDIA's behaviour on Pascal.
248 if ((nv50_dmac_vram_pushbuf > 0) ||
249 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL))
250 type |= NVIF_MEM_VRAM;
252 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
257 dmac->ptr = dmac->_push.mem.object.map.ptr;
258 dmac->_push.wait = nv50_dmac_wait;
259 dmac->_push.kick = nv50_dmac_kick;
260 dmac->push = &dmac->_push;
261 dmac->push->bgn = dmac->_push.mem.object.map.ptr;
262 dmac->push->cur = dmac->push->bgn;
263 dmac->push->end = dmac->push->bgn;
264 dmac->max = 0x1000/4 - 1;
266 /* EVO channels are affected by a HW bug where the last 12 DWORDs
267 * of the push buffer aren't able to be used safely.
269 if (disp->oclass < GV100_DISP)
272 args->pushbuf = nvif_handle(&dmac->_push.mem.object);
274 ret = nv50_chan_create(device, disp, oclass, head, data, size,
282 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
284 &(struct nv_dma_v0) {
285 .target = NV_DMA_V0_TARGET_VRAM,
286 .access = NV_DMA_V0_ACCESS_RDWR,
287 .start = syncbuf + 0x0000,
288 .limit = syncbuf + 0x0fff,
289 }, sizeof(struct nv_dma_v0),
294 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
296 &(struct nv_dma_v0) {
297 .target = NV_DMA_V0_TARGET_VRAM,
298 .access = NV_DMA_V0_ACCESS_RDWR,
300 .limit = device->info.ram_user - 1,
301 }, sizeof(struct nv_dma_v0),
309 /******************************************************************************
310 * Output path helpers
311 *****************************************************************************/
313 nv50_outp_dump_caps(struct nouveau_drm *drm,
314 struct nouveau_encoder *outp)
316 NV_DEBUG(drm, "%s caps: dp_interlace=%d\n",
317 outp->base.base.name, outp->caps.dp_interlace);
321 nv50_outp_release(struct nouveau_encoder *nv_encoder)
323 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
325 struct nv50_disp_mthd_v1 base;
328 .base.method = NV50_DISP_MTHD_V1_RELEASE,
329 .base.hasht = nv_encoder->dcb->hasht,
330 .base.hashm = nv_encoder->dcb->hashm,
333 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
335 nv_encoder->link = 0;
339 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda)
341 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
342 struct nv50_disp *disp = nv50_disp(drm->dev);
344 struct nv50_disp_mthd_v1 base;
345 struct nv50_disp_acquire_v0 info;
348 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
349 .base.hasht = nv_encoder->dcb->hasht,
350 .base.hashm = nv_encoder->dcb->hashm,
355 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
357 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
361 nv_encoder->or = args.info.or;
362 nv_encoder->link = args.info.link;
367 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
368 struct drm_crtc_state *crtc_state,
369 struct drm_connector_state *conn_state,
370 struct drm_display_mode *native_mode)
372 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
373 struct drm_display_mode *mode = &crtc_state->mode;
374 struct drm_connector *connector = conn_state->connector;
375 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
376 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
378 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
379 asyc->scaler.full = false;
383 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
384 switch (connector->connector_type) {
385 case DRM_MODE_CONNECTOR_LVDS:
386 case DRM_MODE_CONNECTOR_eDP:
387 /* Don't force scaler for EDID modes with
388 * same size as the native one (e.g. different
391 if (mode->hdisplay == native_mode->hdisplay &&
392 mode->vdisplay == native_mode->vdisplay &&
393 mode->type & DRM_MODE_TYPE_DRIVER)
396 asyc->scaler.full = true;
405 if (!drm_mode_equal(adjusted_mode, mode)) {
406 drm_mode_copy(adjusted_mode, mode);
407 crtc_state->mode_changed = true;
414 nv50_outp_atomic_check(struct drm_encoder *encoder,
415 struct drm_crtc_state *crtc_state,
416 struct drm_connector_state *conn_state)
418 struct drm_connector *connector = conn_state->connector;
419 struct nouveau_connector *nv_connector = nouveau_connector(connector);
420 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
423 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
424 nv_connector->native_mode);
428 if (crtc_state->mode_changed || crtc_state->connectors_changed)
429 asyh->or.bpc = connector->display_info.bpc;
434 struct nouveau_connector *
435 nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
437 struct drm_connector *connector;
438 struct drm_connector_state *connector_state;
439 struct drm_encoder *encoder = to_drm_encoder(outp);
442 for_each_new_connector_in_state(state, connector, connector_state, i) {
443 if (connector_state->best_encoder == encoder)
444 return nouveau_connector(connector);
450 struct nouveau_connector *
451 nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
453 struct drm_connector *connector;
454 struct drm_connector_state *connector_state;
455 struct drm_encoder *encoder = to_drm_encoder(outp);
458 for_each_old_connector_in_state(state, connector, connector_state, i) {
459 if (connector_state->best_encoder == encoder)
460 return nouveau_connector(connector);
466 static struct nouveau_crtc *
467 nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp)
469 struct drm_crtc *crtc;
470 struct drm_crtc_state *crtc_state;
471 const u32 mask = drm_encoder_mask(&outp->base.base);
474 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
475 if (crtc_state->encoder_mask & mask)
476 return nouveau_crtc(crtc);
482 /******************************************************************************
484 *****************************************************************************/
486 nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
488 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
489 struct nv50_core *core = nv50_disp(encoder->dev)->core;
490 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
492 core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL);
493 nv_encoder->crtc = NULL;
494 nv50_outp_release(nv_encoder);
498 nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
500 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
501 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
502 struct nv50_head_atom *asyh =
503 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
504 struct nv50_core *core = nv50_disp(encoder->dev)->core;
507 switch (nv_crtc->index) {
508 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
509 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
510 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
511 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
517 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
519 nv50_outp_acquire(nv_encoder, false);
521 core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh);
524 nv_encoder->crtc = &nv_crtc->base;
527 static enum drm_connector_status
528 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
530 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
531 struct nv50_disp *disp = nv50_disp(encoder->dev);
533 struct nv50_disp_mthd_v1 base;
534 struct nv50_disp_dac_load_v0 load;
537 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
538 .base.hasht = nv_encoder->dcb->hasht,
539 .base.hashm = nv_encoder->dcb->hashm,
543 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
544 if (args.load.data == 0)
545 args.load.data = 340;
547 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
548 if (ret || !args.load.load)
549 return connector_status_disconnected;
551 return connector_status_connected;
554 static const struct drm_encoder_helper_funcs
556 .atomic_check = nv50_outp_atomic_check,
557 .atomic_enable = nv50_dac_atomic_enable,
558 .atomic_disable = nv50_dac_atomic_disable,
559 .detect = nv50_dac_detect
563 nv50_dac_destroy(struct drm_encoder *encoder)
565 drm_encoder_cleanup(encoder);
569 static const struct drm_encoder_funcs
571 .destroy = nv50_dac_destroy,
575 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
577 struct nouveau_drm *drm = nouveau_drm(connector->dev);
578 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
579 struct nvkm_i2c_bus *bus;
580 struct nouveau_encoder *nv_encoder;
581 struct drm_encoder *encoder;
582 int type = DRM_MODE_ENCODER_DAC;
584 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
587 nv_encoder->dcb = dcbe;
589 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
591 nv_encoder->i2c = &bus->i2c;
593 encoder = to_drm_encoder(nv_encoder);
594 encoder->possible_crtcs = dcbe->heads;
595 encoder->possible_clones = 0;
596 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
597 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
598 drm_encoder_helper_add(encoder, &nv50_dac_help);
600 drm_connector_attach_encoder(connector, encoder);
605 * audio component binding for ELD notification
608 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
611 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
612 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
617 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
618 bool *enabled, unsigned char *buf, int max_bytes)
620 struct drm_device *drm_dev = dev_get_drvdata(kdev);
621 struct nouveau_drm *drm = nouveau_drm(drm_dev);
622 struct drm_encoder *encoder;
623 struct nouveau_encoder *nv_encoder;
624 struct nouveau_crtc *nv_crtc;
629 mutex_lock(&drm->audio.lock);
631 drm_for_each_encoder(encoder, drm->dev) {
632 struct nouveau_connector *nv_connector = NULL;
634 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST)
637 nv_encoder = nouveau_encoder(encoder);
638 nv_connector = nouveau_connector(nv_encoder->audio.connector);
639 nv_crtc = nouveau_crtc(nv_encoder->crtc);
641 if (!nv_crtc || nv_encoder->or != port || nv_crtc->index != dev_id)
644 *enabled = nv_encoder->audio.enabled;
646 ret = drm_eld_size(nv_connector->base.eld);
647 memcpy(buf, nv_connector->base.eld,
648 min(max_bytes, ret));
653 mutex_unlock(&drm->audio.lock);
658 static const struct drm_audio_component_ops nv50_audio_component_ops = {
659 .get_eld = nv50_audio_component_get_eld,
663 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
666 struct drm_device *drm_dev = dev_get_drvdata(kdev);
667 struct nouveau_drm *drm = nouveau_drm(drm_dev);
668 struct drm_audio_component *acomp = data;
670 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
673 drm_modeset_lock_all(drm_dev);
674 acomp->ops = &nv50_audio_component_ops;
676 drm->audio.component = acomp;
677 drm_modeset_unlock_all(drm_dev);
682 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
685 struct drm_device *drm_dev = dev_get_drvdata(kdev);
686 struct nouveau_drm *drm = nouveau_drm(drm_dev);
687 struct drm_audio_component *acomp = data;
689 drm_modeset_lock_all(drm_dev);
690 drm->audio.component = NULL;
693 drm_modeset_unlock_all(drm_dev);
696 static const struct component_ops nv50_audio_component_bind_ops = {
697 .bind = nv50_audio_component_bind,
698 .unbind = nv50_audio_component_unbind,
702 nv50_audio_component_init(struct nouveau_drm *drm)
704 if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
707 drm->audio.component_registered = true;
708 mutex_init(&drm->audio.lock);
712 nv50_audio_component_fini(struct nouveau_drm *drm)
714 if (!drm->audio.component_registered)
717 component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
718 drm->audio.component_registered = false;
719 mutex_destroy(&drm->audio.lock);
722 /******************************************************************************
724 *****************************************************************************/
726 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
728 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
729 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
730 struct nv50_disp *disp = nv50_disp(encoder->dev);
732 struct nv50_disp_mthd_v1 base;
733 struct nv50_disp_sor_hda_eld_v0 eld;
736 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
737 .base.hasht = nv_encoder->dcb->hasht,
738 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
739 (0x0100 << nv_crtc->index),
742 mutex_lock(&drm->audio.lock);
743 if (nv_encoder->audio.enabled) {
744 nv_encoder->audio.enabled = false;
745 nv_encoder->audio.connector = NULL;
746 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
748 mutex_unlock(&drm->audio.lock);
750 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
755 nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
756 struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
757 struct drm_display_mode *mode)
759 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
760 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
761 struct nv50_disp *disp = nv50_disp(encoder->dev);
764 struct nv50_disp_mthd_v1 mthd;
765 struct nv50_disp_sor_hda_eld_v0 eld;
767 u8 data[sizeof(nv_connector->base.eld)];
769 .base.mthd.version = 1,
770 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
771 .base.mthd.hasht = nv_encoder->dcb->hasht,
772 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
773 (0x0100 << nv_crtc->index),
776 if (!drm_detect_monitor_audio(nv_connector->edid))
779 mutex_lock(&drm->audio.lock);
781 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
783 nvif_mthd(&disp->disp->object, 0, &args,
784 sizeof(args.base) + drm_eld_size(args.data));
785 nv_encoder->audio.enabled = true;
786 nv_encoder->audio.connector = &nv_connector->base;
788 mutex_unlock(&drm->audio.lock);
790 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
794 /******************************************************************************
796 *****************************************************************************/
798 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
800 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
801 struct nv50_disp *disp = nv50_disp(encoder->dev);
803 struct nv50_disp_mthd_v1 base;
804 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
807 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
808 .base.hasht = nv_encoder->dcb->hasht,
809 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
810 (0x0100 << nv_crtc->index),
813 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
817 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
818 struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
819 struct drm_display_mode *mode)
821 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
822 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
823 struct nv50_disp *disp = nv50_disp(encoder->dev);
825 struct nv50_disp_mthd_v1 base;
826 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
827 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
830 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
831 .base.hasht = nv_encoder->dcb->hasht,
832 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
833 (0x0100 << nv_crtc->index),
835 .pwr.rekey = 56, /* binary driver, and tegra, constant */
837 struct drm_hdmi_info *hdmi;
839 union hdmi_infoframe avi_frame;
840 union hdmi_infoframe vendor_frame;
841 bool high_tmds_clock_ratio = false, scrambling = false;
846 if (!drm_detect_hdmi_monitor(nv_connector->edid))
849 hdmi = &nv_connector->base.display_info.hdmi;
851 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
852 &nv_connector->base, mode);
854 /* We have an AVI InfoFrame, populate it to the display */
855 args.pwr.avi_infoframe_length
856 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
859 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
860 &nv_connector->base, mode);
862 /* We have a Vendor InfoFrame, populate it to the display */
863 args.pwr.vendor_infoframe_length
864 = hdmi_infoframe_pack(&vendor_frame,
866 + args.pwr.avi_infoframe_length,
870 max_ac_packet = mode->htotal - mode->hdisplay;
871 max_ac_packet -= args.pwr.rekey;
872 max_ac_packet -= 18; /* constant from tegra */
873 args.pwr.max_ac_packet = max_ac_packet / 32;
875 if (hdmi->scdc.scrambling.supported) {
876 high_tmds_clock_ratio = mode->clock > 340000;
877 scrambling = high_tmds_clock_ratio ||
878 hdmi->scdc.scrambling.low_rates;
882 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
883 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
885 size = sizeof(args.base)
887 + args.pwr.avi_infoframe_length
888 + args.pwr.vendor_infoframe_length;
889 nvif_mthd(&disp->disp->object, 0, &args, size);
891 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
893 /* If SCDC is supported by the downstream monitor, update
894 * divider / scrambling settings to what we programmed above.
896 if (!hdmi->scdc.scrambling.supported)
899 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
901 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
904 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
905 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
906 config |= SCDC_SCRAMBLING_ENABLE * scrambling;
907 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
909 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
913 /******************************************************************************
915 *****************************************************************************/
916 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
917 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
918 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
921 struct nv50_mstm *mstm;
922 struct drm_dp_mst_port *port;
923 struct drm_connector connector;
925 struct drm_display_mode *native;
930 struct drm_encoder encoder;
932 /* head is statically assigned on msto creation */
933 struct nv50_head *head;
934 struct nv50_mstc *mstc;
938 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder)
940 struct nv50_msto *msto;
942 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
943 return nouveau_encoder(encoder);
945 msto = nv50_msto(encoder);
948 return msto->mstc->mstm->outp;
951 static struct drm_dp_payload *
952 nv50_msto_payload(struct nv50_msto *msto)
954 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
955 struct nv50_mstc *mstc = msto->mstc;
956 struct nv50_mstm *mstm = mstc->mstm;
957 int vcpi = mstc->port->vcpi.vcpi, i;
959 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
961 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
962 for (i = 0; i < mstm->mgr.max_payloads; i++) {
963 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
964 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
965 mstm->outp->base.base.name, i, payload->vcpi,
966 payload->start_slot, payload->num_slots);
969 for (i = 0; i < mstm->mgr.max_payloads; i++) {
970 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
971 if (payload->vcpi == vcpi)
979 nv50_msto_cleanup(struct nv50_msto *msto)
981 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
982 struct nv50_mstc *mstc = msto->mstc;
983 struct nv50_mstm *mstm = mstc->mstm;
988 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
990 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
993 msto->disabled = false;
997 nv50_msto_prepare(struct nv50_msto *msto)
999 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
1000 struct nv50_mstc *mstc = msto->mstc;
1001 struct nv50_mstm *mstm = mstc->mstm;
1003 struct nv50_disp_mthd_v1 base;
1004 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
1007 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
1008 .base.hasht = mstm->outp->dcb->hasht,
1009 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) |
1010 (0x0100 << msto->head->base.index),
1013 mutex_lock(&mstm->mgr.payload_lock);
1015 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
1016 if (mstc->port->vcpi.vcpi > 0) {
1017 struct drm_dp_payload *payload = nv50_msto_payload(msto);
1019 args.vcpi.start_slot = payload->start_slot;
1020 args.vcpi.num_slots = payload->num_slots;
1021 args.vcpi.pbn = mstc->port->vcpi.pbn;
1022 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
1026 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
1027 msto->encoder.name, msto->head->base.base.name,
1028 args.vcpi.start_slot, args.vcpi.num_slots,
1029 args.vcpi.pbn, args.vcpi.aligned_pbn);
1031 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
1032 mutex_unlock(&mstm->mgr.payload_lock);
1036 nv50_msto_atomic_check(struct drm_encoder *encoder,
1037 struct drm_crtc_state *crtc_state,
1038 struct drm_connector_state *conn_state)
1040 struct drm_atomic_state *state = crtc_state->state;
1041 struct drm_connector *connector = conn_state->connector;
1042 struct nv50_mstc *mstc = nv50_mstc(connector);
1043 struct nv50_mstm *mstm = mstc->mstm;
1044 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
1048 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
1053 if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
1057 * When restoring duplicated states, we need to make sure that the bw
1058 * remains the same and avoid recalculating it, as the connector's bpc
1059 * may have changed after the state was duplicated
1061 if (!state->duplicated) {
1062 const int clock = crtc_state->adjusted_mode.clock;
1064 asyh->or.bpc = connector->display_info.bpc;
1065 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
1069 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
1074 asyh->dp.tu = slots;
1080 nv50_dp_bpc_to_depth(unsigned int bpc)
1083 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
1084 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
1086 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
1091 nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1093 struct nv50_msto *msto = nv50_msto(encoder);
1094 struct nv50_head *head = msto->head;
1095 struct nv50_head_atom *asyh =
1096 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base));
1097 struct nv50_mstc *mstc = NULL;
1098 struct nv50_mstm *mstm = NULL;
1099 struct drm_connector *connector;
1100 struct drm_connector_list_iter conn_iter;
1104 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
1105 drm_for_each_connector_iter(connector, &conn_iter) {
1106 if (connector->state->best_encoder == &msto->encoder) {
1107 mstc = nv50_mstc(connector);
1112 drm_connector_list_iter_end(&conn_iter);
1117 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, asyh->dp.pbn, asyh->dp.tu);
1119 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
1122 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/);
1124 if (mstm->outp->link & 1)
1125 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1127 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1129 mstm->outp->update(mstm->outp, head->base.index, asyh, proto,
1130 nv50_dp_bpc_to_depth(asyh->or.bpc));
1133 mstm->modified = true;
1137 nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1139 struct nv50_msto *msto = nv50_msto(encoder);
1140 struct nv50_mstc *mstc = msto->mstc;
1141 struct nv50_mstm *mstm = mstc->mstm;
1143 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
1145 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
1146 mstm->modified = true;
1148 mstm->disabled = true;
1149 msto->disabled = true;
1152 static const struct drm_encoder_helper_funcs
1154 .atomic_disable = nv50_msto_atomic_disable,
1155 .atomic_enable = nv50_msto_atomic_enable,
1156 .atomic_check = nv50_msto_atomic_check,
1160 nv50_msto_destroy(struct drm_encoder *encoder)
1162 struct nv50_msto *msto = nv50_msto(encoder);
1163 drm_encoder_cleanup(&msto->encoder);
1167 static const struct drm_encoder_funcs
1169 .destroy = nv50_msto_destroy,
1172 static struct nv50_msto *
1173 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1175 struct nv50_msto *msto;
1178 msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1180 return ERR_PTR(-ENOMEM);
1182 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1183 DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1186 return ERR_PTR(ret);
1189 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1190 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1195 static struct drm_encoder *
1196 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1197 struct drm_atomic_state *state)
1199 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1201 struct nv50_mstc *mstc = nv50_mstc(connector);
1202 struct drm_crtc *crtc = connector_state->crtc;
1204 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1207 return &nv50_head(crtc)->msto->encoder;
1210 static enum drm_mode_status
1211 nv50_mstc_mode_valid(struct drm_connector *connector,
1212 struct drm_display_mode *mode)
1214 struct nv50_mstc *mstc = nv50_mstc(connector);
1215 struct nouveau_encoder *outp = mstc->mstm->outp;
1217 /* TODO: calculate the PBN from the dotclock and validate against the
1218 * MSTB's max possible PBN
1221 return nv50_dp_mode_valid(connector, outp, mode, NULL);
1225 nv50_mstc_get_modes(struct drm_connector *connector)
1227 struct nv50_mstc *mstc = nv50_mstc(connector);
1230 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1231 drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1233 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1236 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1237 * to 8 to save bandwidth on the topology. In the future, we'll want
1238 * to properly fix this by dynamically selecting the highest possible
1239 * bpc that would fit in the topology
1241 if (connector->display_info.bpc)
1242 connector->display_info.bpc =
1243 clamp(connector->display_info.bpc, 6U, 8U);
1245 connector->display_info.bpc = 8;
1248 drm_mode_destroy(mstc->connector.dev, mstc->native);
1249 mstc->native = nouveau_conn_native_mode(&mstc->connector);
1254 nv50_mstc_atomic_check(struct drm_connector *connector,
1255 struct drm_atomic_state *state)
1257 struct nv50_mstc *mstc = nv50_mstc(connector);
1258 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1259 struct drm_connector_state *new_conn_state =
1260 drm_atomic_get_new_connector_state(state, connector);
1261 struct drm_connector_state *old_conn_state =
1262 drm_atomic_get_old_connector_state(state, connector);
1263 struct drm_crtc_state *crtc_state;
1264 struct drm_crtc *new_crtc = new_conn_state->crtc;
1266 if (!old_conn_state->crtc)
1269 /* We only want to free VCPI if this state disables the CRTC on this
1273 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
1276 !drm_atomic_crtc_needs_modeset(crtc_state) ||
1281 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1285 nv50_mstc_detect(struct drm_connector *connector,
1286 struct drm_modeset_acquire_ctx *ctx, bool force)
1288 struct nv50_mstc *mstc = nv50_mstc(connector);
1291 if (drm_connector_is_unregistered(connector))
1292 return connector_status_disconnected;
1294 ret = pm_runtime_get_sync(connector->dev->dev);
1295 if (ret < 0 && ret != -EACCES) {
1296 pm_runtime_put_autosuspend(connector->dev->dev);
1297 return connector_status_disconnected;
1300 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1302 if (ret != connector_status_connected)
1306 pm_runtime_mark_last_busy(connector->dev->dev);
1307 pm_runtime_put_autosuspend(connector->dev->dev);
1311 static const struct drm_connector_helper_funcs
1313 .get_modes = nv50_mstc_get_modes,
1314 .mode_valid = nv50_mstc_mode_valid,
1315 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1316 .atomic_check = nv50_mstc_atomic_check,
1317 .detect_ctx = nv50_mstc_detect,
1321 nv50_mstc_destroy(struct drm_connector *connector)
1323 struct nv50_mstc *mstc = nv50_mstc(connector);
1325 drm_connector_cleanup(&mstc->connector);
1326 drm_dp_mst_put_port_malloc(mstc->port);
1331 static const struct drm_connector_funcs
1333 .reset = nouveau_conn_reset,
1334 .fill_modes = drm_helper_probe_single_connector_modes,
1335 .destroy = nv50_mstc_destroy,
1336 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1337 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1338 .atomic_set_property = nouveau_conn_atomic_set_property,
1339 .atomic_get_property = nouveau_conn_atomic_get_property,
1343 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1344 const char *path, struct nv50_mstc **pmstc)
1346 struct drm_device *dev = mstm->outp->base.base.dev;
1347 struct drm_crtc *crtc;
1348 struct nv50_mstc *mstc;
1351 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1356 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1357 DRM_MODE_CONNECTOR_DisplayPort);
1364 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1366 mstc->connector.funcs->reset(&mstc->connector);
1367 nouveau_conn_attach_properties(&mstc->connector);
1369 drm_for_each_crtc(crtc, dev) {
1370 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1373 drm_connector_attach_encoder(&mstc->connector,
1374 &nv50_head(crtc)->msto->encoder);
1377 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1378 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1379 drm_connector_set_path_property(&mstc->connector, path);
1380 drm_dp_mst_get_port_malloc(port);
1385 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1387 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1388 struct drm_encoder *encoder;
1391 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1392 ret = drm_dp_check_act_status(&mstm->mgr);
1394 ret = drm_dp_update_payload_part2(&mstm->mgr);
1396 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1397 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1398 struct nv50_msto *msto = nv50_msto(encoder);
1399 struct nv50_mstc *mstc = msto->mstc;
1400 if (mstc && mstc->mstm == mstm)
1401 nv50_msto_cleanup(msto);
1405 mstm->modified = false;
1409 nv50_mstm_prepare(struct nv50_mstm *mstm)
1411 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1412 struct drm_encoder *encoder;
1415 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1416 ret = drm_dp_update_payload_part1(&mstm->mgr);
1418 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1419 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1420 struct nv50_msto *msto = nv50_msto(encoder);
1421 struct nv50_mstc *mstc = msto->mstc;
1422 if (mstc && mstc->mstm == mstm)
1423 nv50_msto_prepare(msto);
1427 if (mstm->disabled) {
1429 nv50_outp_release(mstm->outp);
1430 mstm->disabled = false;
1434 static struct drm_connector *
1435 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1436 struct drm_dp_mst_port *port, const char *path)
1438 struct nv50_mstm *mstm = nv50_mstm(mgr);
1439 struct nv50_mstc *mstc;
1442 ret = nv50_mstc_new(mstm, port, path, &mstc);
1446 return &mstc->connector;
1449 static const struct drm_dp_mst_topology_cbs
1451 .add_connector = nv50_mstm_add_connector,
1455 nv50_mstm_service(struct nouveau_drm *drm,
1456 struct nouveau_connector *nv_connector,
1457 struct nv50_mstm *mstm)
1459 struct drm_dp_aux *aux = &nv_connector->aux;
1460 bool handled = true, ret = true;
1465 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1471 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1475 rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1],
1484 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n",
1485 nv_connector->base.name, rc);
1491 nv50_mstm_remove(struct nv50_mstm *mstm)
1493 mstm->is_mst = false;
1494 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1498 nv50_mstm_enable(struct nv50_mstm *mstm, int state)
1500 struct nouveau_encoder *outp = mstm->outp;
1502 struct nv50_disp_mthd_v1 base;
1503 struct nv50_disp_sor_dp_mst_link_v0 mst;
1506 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1507 .base.hasht = outp->dcb->hasht,
1508 .base.hashm = outp->dcb->hashm,
1511 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1512 struct nvif_object *disp = &drm->display->disp.object;
1514 return nvif_mthd(disp, 0, &args, sizeof(args));
1518 nv50_mstm_detect(struct nouveau_encoder *outp)
1520 struct nv50_mstm *mstm = outp->dp.mstm;
1521 struct drm_dp_aux *aux;
1524 if (!mstm || !mstm->can_mst)
1527 aux = mstm->mgr.aux;
1529 /* Clear any leftover MST state we didn't set ourselves by first
1530 * disabling MST if it was already enabled
1532 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1536 /* And start enabling */
1537 ret = nv50_mstm_enable(mstm, true);
1541 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true);
1543 nv50_mstm_enable(mstm, false);
1547 mstm->is_mst = true;
1552 nv50_mstm_fini(struct nouveau_encoder *outp)
1554 struct nv50_mstm *mstm = outp->dp.mstm;
1559 /* Don't change the MST state of this connector until we've finished
1560 * resuming, since we can't safely grab hpd_irq_lock in our resume
1561 * path to protect mstm->is_mst without potentially deadlocking
1563 mutex_lock(&outp->dp.hpd_irq_lock);
1564 mstm->suspended = true;
1565 mutex_unlock(&outp->dp.hpd_irq_lock);
1568 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1572 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime)
1574 struct nv50_mstm *mstm = outp->dp.mstm;
1581 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1583 nv50_mstm_remove(mstm);
1586 mutex_lock(&outp->dp.hpd_irq_lock);
1587 mstm->suspended = false;
1588 mutex_unlock(&outp->dp.hpd_irq_lock);
1591 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1595 nv50_mstm_del(struct nv50_mstm **pmstm)
1597 struct nv50_mstm *mstm = *pmstm;
1599 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1606 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1607 int conn_base_id, struct nv50_mstm **pmstm)
1609 const int max_payloads = hweight8(outp->dcb->heads);
1610 struct drm_device *dev = outp->base.base.dev;
1611 struct nv50_mstm *mstm;
1614 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1617 mstm->mgr.cbs = &nv50_mstm;
1619 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1620 max_payloads, outp->dcb->dpconf.link_nr,
1621 drm_dp_bw_code_to_link_rate(outp->dcb->dpconf.link_bw),
1629 /******************************************************************************
1631 *****************************************************************************/
1633 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1634 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1636 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1637 struct nv50_core *core = disp->core;
1640 nv_encoder->ctrl &= ~BIT(head);
1641 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1642 nv_encoder->ctrl = 0;
1644 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1645 nv_encoder->ctrl |= BIT(head);
1646 asyh->or.depth = depth;
1649 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1653 nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1655 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1656 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1657 struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder);
1658 struct drm_dp_aux *aux = &nv_connector->aux;
1661 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1662 int ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
1665 pwr &= ~DP_SET_POWER_MASK;
1666 pwr |= DP_SET_POWER_D3;
1667 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);
1671 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1672 nv50_audio_disable(encoder, nv_crtc);
1673 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1674 nv50_outp_release(nv_encoder);
1675 nv_encoder->crtc = NULL;
1679 nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1681 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1682 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1683 struct nv50_head_atom *asyh =
1684 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1685 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1687 struct nv50_disp_mthd_v1 base;
1688 struct nv50_disp_sor_lvds_script_v0 lvds;
1691 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1692 .base.hasht = nv_encoder->dcb->hasht,
1693 .base.hashm = nv_encoder->dcb->hashm,
1695 struct nv50_disp *disp = nv50_disp(encoder->dev);
1696 struct drm_device *dev = encoder->dev;
1697 struct nouveau_drm *drm = nouveau_drm(dev);
1698 struct nouveau_connector *nv_connector;
1699 struct nvbios *bios = &drm->vbios;
1701 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
1702 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
1704 nv_connector = nv50_outp_get_new_connector(state, nv_encoder);
1705 nv_encoder->crtc = &nv_crtc->base;
1707 if ((disp->disp->object.oclass == GT214_DISP ||
1708 disp->disp->object.oclass >= GF110_DISP) &&
1709 drm_detect_monitor_audio(nv_connector->edid))
1711 nv50_outp_acquire(nv_encoder, hda);
1713 switch (nv_encoder->dcb->type) {
1714 case DCB_OUTPUT_TMDS:
1715 if (nv_encoder->link & 1) {
1716 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1717 /* Only enable dual-link if:
1718 * - Need to (i.e. rate > 165MHz)
1720 * - Not an HDMI monitor, since there's no dual-link
1723 if (mode->clock >= 165000 &&
1724 nv_encoder->dcb->duallink_possible &&
1725 !drm_detect_hdmi_monitor(nv_connector->edid))
1726 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1728 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1731 nv50_hdmi_enable(&nv_encoder->base.base, nv_crtc, nv_connector, state, mode);
1733 case DCB_OUTPUT_LVDS:
1734 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1736 if (bios->fp_no_ddc) {
1737 if (bios->fp.dual_link)
1738 lvds.lvds.script |= 0x0100;
1739 if (bios->fp.if_is_24bit)
1740 lvds.lvds.script |= 0x0200;
1742 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1743 if (((u8 *)nv_connector->edid)[121] == 2)
1744 lvds.lvds.script |= 0x0100;
1746 if (mode->clock >= bios->fp.duallink_transition_clk) {
1747 lvds.lvds.script |= 0x0100;
1750 if (lvds.lvds.script & 0x0100) {
1751 if (bios->fp.strapless_is_24bit & 2)
1752 lvds.lvds.script |= 0x0200;
1754 if (bios->fp.strapless_is_24bit & 1)
1755 lvds.lvds.script |= 0x0200;
1758 if (asyh->or.bpc == 8)
1759 lvds.lvds.script |= 0x0200;
1762 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1765 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1767 if (nv_encoder->link & 1)
1768 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1770 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1772 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
1779 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1782 static const struct drm_encoder_helper_funcs
1784 .atomic_check = nv50_outp_atomic_check,
1785 .atomic_enable = nv50_sor_atomic_enable,
1786 .atomic_disable = nv50_sor_atomic_disable,
1790 nv50_sor_destroy(struct drm_encoder *encoder)
1792 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1793 nv50_mstm_del(&nv_encoder->dp.mstm);
1794 drm_encoder_cleanup(encoder);
1796 if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1797 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
1802 static const struct drm_encoder_funcs
1804 .destroy = nv50_sor_destroy,
1807 static bool nv50_has_mst(struct nouveau_drm *drm)
1809 struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1811 u8 ver, hdr, cnt, len;
1813 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1814 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1818 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1820 struct nouveau_connector *nv_connector = nouveau_connector(connector);
1821 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1822 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1823 struct nouveau_encoder *nv_encoder;
1824 struct drm_encoder *encoder;
1825 struct nv50_disp *disp = nv50_disp(connector->dev);
1828 switch (dcbe->type) {
1829 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1830 case DCB_OUTPUT_TMDS:
1833 type = DRM_MODE_ENCODER_TMDS;
1837 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1840 nv_encoder->dcb = dcbe;
1841 nv_encoder->update = nv50_sor_update;
1843 encoder = to_drm_encoder(nv_encoder);
1844 encoder->possible_crtcs = dcbe->heads;
1845 encoder->possible_clones = 0;
1846 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1847 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1848 drm_encoder_helper_add(encoder, &nv50_sor_help);
1850 drm_connector_attach_encoder(connector, encoder);
1852 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1853 nv50_outp_dump_caps(drm, nv_encoder);
1855 if (dcbe->type == DCB_OUTPUT_DP) {
1856 struct nvkm_i2c_aux *aux =
1857 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1859 mutex_init(&nv_encoder->dp.hpd_irq_lock);
1862 if (disp->disp->object.oclass < GF110_DISP) {
1863 /* HW has no support for address-only
1864 * transactions, so we're required to
1865 * use custom I2C-over-AUX code.
1867 nv_encoder->i2c = &aux->i2c;
1869 nv_encoder->i2c = &nv_connector->aux.ddc;
1871 nv_encoder->aux = aux;
1874 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1875 nv50_has_mst(drm)) {
1876 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1877 16, nv_connector->base.base.id,
1878 &nv_encoder->dp.mstm);
1883 struct nvkm_i2c_bus *bus =
1884 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1886 nv_encoder->i2c = &bus->i2c;
1892 /******************************************************************************
1894 *****************************************************************************/
1896 nv50_pior_atomic_check(struct drm_encoder *encoder,
1897 struct drm_crtc_state *crtc_state,
1898 struct drm_connector_state *conn_state)
1900 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1903 crtc_state->adjusted_mode.clock *= 2;
1908 nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1910 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1911 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1912 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
1914 core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL);
1915 nv_encoder->crtc = NULL;
1916 nv50_outp_release(nv_encoder);
1920 nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1922 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1923 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1924 struct nv50_head_atom *asyh =
1925 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1926 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1929 switch (nv_crtc->index) {
1930 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
1931 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
1937 nv50_outp_acquire(nv_encoder, false);
1939 switch (asyh->or.bpc) {
1940 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
1941 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1942 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1943 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1946 switch (nv_encoder->dcb->type) {
1947 case DCB_OUTPUT_TMDS:
1949 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1956 core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh);
1957 nv_encoder->crtc = &nv_crtc->base;
1960 static const struct drm_encoder_helper_funcs
1962 .atomic_check = nv50_pior_atomic_check,
1963 .atomic_enable = nv50_pior_atomic_enable,
1964 .atomic_disable = nv50_pior_atomic_disable,
1968 nv50_pior_destroy(struct drm_encoder *encoder)
1970 drm_encoder_cleanup(encoder);
1974 static const struct drm_encoder_funcs
1976 .destroy = nv50_pior_destroy,
1980 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1982 struct drm_device *dev = connector->dev;
1983 struct nouveau_drm *drm = nouveau_drm(dev);
1984 struct nv50_disp *disp = nv50_disp(dev);
1985 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1986 struct nvkm_i2c_bus *bus = NULL;
1987 struct nvkm_i2c_aux *aux = NULL;
1988 struct i2c_adapter *ddc;
1989 struct nouveau_encoder *nv_encoder;
1990 struct drm_encoder *encoder;
1993 switch (dcbe->type) {
1994 case DCB_OUTPUT_TMDS:
1995 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1996 ddc = bus ? &bus->i2c : NULL;
1997 type = DRM_MODE_ENCODER_TMDS;
2000 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
2001 ddc = aux ? &aux->i2c : NULL;
2002 type = DRM_MODE_ENCODER_TMDS;
2008 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2011 nv_encoder->dcb = dcbe;
2012 nv_encoder->i2c = ddc;
2013 nv_encoder->aux = aux;
2015 encoder = to_drm_encoder(nv_encoder);
2016 encoder->possible_crtcs = dcbe->heads;
2017 encoder->possible_clones = 0;
2018 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
2019 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
2020 drm_encoder_helper_add(encoder, &nv50_pior_help);
2022 drm_connector_attach_encoder(connector, encoder);
2024 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
2025 nv50_outp_dump_caps(drm, nv_encoder);
2030 /******************************************************************************
2032 *****************************************************************************/
2035 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
2037 struct nouveau_drm *drm = nouveau_drm(state->dev);
2038 struct nv50_disp *disp = nv50_disp(drm->dev);
2039 struct nv50_core *core = disp->core;
2040 struct nv50_mstm *mstm;
2041 struct drm_encoder *encoder;
2043 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
2045 drm_for_each_encoder(encoder, drm->dev) {
2046 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2047 mstm = nouveau_encoder(encoder)->dp.mstm;
2048 if (mstm && mstm->modified)
2049 nv50_mstm_prepare(mstm);
2053 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
2054 core->func->update(core, interlock, true);
2055 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
2056 disp->core->chan.base.device))
2057 NV_ERROR(drm, "core notifier timeout\n");
2059 drm_for_each_encoder(encoder, drm->dev) {
2060 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2061 mstm = nouveau_encoder(encoder)->dp.mstm;
2062 if (mstm && mstm->modified)
2063 nv50_mstm_cleanup(mstm);
2069 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
2071 struct drm_plane_state *new_plane_state;
2072 struct drm_plane *plane;
2075 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2076 struct nv50_wndw *wndw = nv50_wndw(plane);
2077 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
2078 if (wndw->func->update)
2079 wndw->func->update(wndw, interlock);
2085 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
2087 struct drm_device *dev = state->dev;
2088 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
2089 struct drm_crtc *crtc;
2090 struct drm_plane_state *new_plane_state;
2091 struct drm_plane *plane;
2092 struct nouveau_drm *drm = nouveau_drm(dev);
2093 struct nv50_disp *disp = nv50_disp(dev);
2094 struct nv50_atom *atom = nv50_atom(state);
2095 struct nv50_core *core = disp->core;
2096 struct nv50_outp_atom *outp, *outt;
2097 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
2099 bool flushed = false;
2101 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
2102 nv50_crc_atomic_stop_reporting(state);
2103 drm_atomic_helper_wait_for_fences(dev, state, false);
2104 drm_atomic_helper_wait_for_dependencies(state);
2105 drm_atomic_helper_update_legacy_modeset_state(dev, state);
2106 drm_atomic_helper_calc_timestamping_constants(state);
2108 if (atom->lock_core)
2109 mutex_lock(&disp->mutex);
2111 /* Disable head(s). */
2112 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2113 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2114 struct nv50_head *head = nv50_head(crtc);
2116 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
2117 asyh->clr.mask, asyh->set.mask);
2119 if (old_crtc_state->active && !new_crtc_state->active) {
2120 pm_runtime_put_noidle(dev->dev);
2121 drm_crtc_vblank_off(crtc);
2124 if (asyh->clr.mask) {
2125 nv50_head_flush_clr(head, asyh, atom->flush_disable);
2126 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2130 /* Disable plane(s). */
2131 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2132 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2133 struct nv50_wndw *wndw = nv50_wndw(plane);
2135 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
2136 asyw->clr.mask, asyw->set.mask);
2137 if (!asyw->clr.mask)
2140 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
2143 /* Disable output path(s). */
2144 list_for_each_entry(outp, &atom->outp, head) {
2145 const struct drm_encoder_helper_funcs *help;
2146 struct drm_encoder *encoder;
2148 encoder = outp->encoder;
2149 help = encoder->helper_private;
2151 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2152 outp->clr.mask, outp->set.mask);
2154 if (outp->clr.mask) {
2155 help->atomic_disable(encoder, state);
2156 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2157 if (outp->flush_disable) {
2158 nv50_disp_atomic_commit_wndw(state, interlock);
2159 nv50_disp_atomic_commit_core(state, interlock);
2160 memset(interlock, 0x00, sizeof(interlock));
2167 /* Flush disable. */
2168 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2169 if (atom->flush_disable) {
2170 nv50_disp_atomic_commit_wndw(state, interlock);
2171 nv50_disp_atomic_commit_core(state, interlock);
2172 memset(interlock, 0x00, sizeof(interlock));
2179 nv50_crc_atomic_release_notifier_contexts(state);
2180 nv50_crc_atomic_init_notifier_contexts(state);
2182 /* Update output path(s). */
2183 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2184 const struct drm_encoder_helper_funcs *help;
2185 struct drm_encoder *encoder;
2187 encoder = outp->encoder;
2188 help = encoder->helper_private;
2190 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2191 outp->set.mask, outp->clr.mask);
2193 if (outp->set.mask) {
2194 help->atomic_enable(encoder, state);
2195 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2198 list_del(&outp->head);
2202 /* Update head(s). */
2203 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2204 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2205 struct nv50_head *head = nv50_head(crtc);
2207 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2208 asyh->set.mask, asyh->clr.mask);
2210 if (asyh->set.mask) {
2211 nv50_head_flush_set(head, asyh);
2212 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2215 if (new_crtc_state->active) {
2216 if (!old_crtc_state->active) {
2217 drm_crtc_vblank_on(crtc);
2218 pm_runtime_get_noresume(dev->dev);
2220 if (new_crtc_state->event)
2221 drm_crtc_vblank_get(crtc);
2225 /* Update window->head assignment.
2227 * This has to happen in an update that's not interlocked with
2228 * any window channels to avoid hitting HW error checks.
2230 *TODO: Proper handling of window ownership (Turing apparently
2231 * supports non-fixed mappings).
2233 if (core->assign_windows) {
2234 core->func->wndw.owner(core);
2235 nv50_disp_atomic_commit_core(state, interlock);
2236 core->assign_windows = false;
2237 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2240 /* Update plane(s). */
2241 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2242 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2243 struct nv50_wndw *wndw = nv50_wndw(plane);
2245 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2246 asyw->set.mask, asyw->clr.mask);
2247 if ( !asyw->set.mask &&
2248 (!asyw->clr.mask || atom->flush_disable))
2251 nv50_wndw_flush_set(wndw, interlock, asyw);
2255 nv50_disp_atomic_commit_wndw(state, interlock);
2257 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2258 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2259 interlock[NV50_DISP_INTERLOCK_OVLY] ||
2260 interlock[NV50_DISP_INTERLOCK_WNDW] ||
2261 !atom->state.legacy_cursor_update)
2262 nv50_disp_atomic_commit_core(state, interlock);
2264 disp->core->func->update(disp->core, interlock, false);
2267 if (atom->lock_core)
2268 mutex_unlock(&disp->mutex);
2270 /* Wait for HW to signal completion. */
2271 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2272 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2273 struct nv50_wndw *wndw = nv50_wndw(plane);
2274 int ret = nv50_wndw_wait_armed(wndw, asyw);
2276 NV_ERROR(drm, "%s: timeout\n", plane->name);
2279 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2280 if (new_crtc_state->event) {
2281 unsigned long flags;
2282 /* Get correct count/ts if racing with vblank irq */
2283 if (new_crtc_state->active)
2284 drm_crtc_accurate_vblank_count(crtc);
2285 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2286 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2287 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2289 new_crtc_state->event = NULL;
2290 if (new_crtc_state->active)
2291 drm_crtc_vblank_put(crtc);
2295 nv50_crc_atomic_start_reporting(state);
2297 nv50_crc_atomic_release_notifier_contexts(state);
2298 drm_atomic_helper_commit_hw_done(state);
2299 drm_atomic_helper_cleanup_planes(dev, state);
2300 drm_atomic_helper_commit_cleanup_done(state);
2301 drm_atomic_state_put(state);
2303 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2304 pm_runtime_mark_last_busy(dev->dev);
2305 pm_runtime_put_autosuspend(dev->dev);
2309 nv50_disp_atomic_commit_work(struct work_struct *work)
2311 struct drm_atomic_state *state =
2312 container_of(work, typeof(*state), commit_work);
2313 nv50_disp_atomic_commit_tail(state);
2317 nv50_disp_atomic_commit(struct drm_device *dev,
2318 struct drm_atomic_state *state, bool nonblock)
2320 struct drm_plane_state *new_plane_state;
2321 struct drm_plane *plane;
2324 ret = pm_runtime_get_sync(dev->dev);
2325 if (ret < 0 && ret != -EACCES) {
2326 pm_runtime_put_autosuspend(dev->dev);
2330 ret = drm_atomic_helper_setup_commit(state, nonblock);
2334 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2336 ret = drm_atomic_helper_prepare_planes(dev, state);
2341 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2346 ret = drm_atomic_helper_swap_state(state, true);
2350 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2351 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2352 struct nv50_wndw *wndw = nv50_wndw(plane);
2354 if (asyw->set.image)
2355 nv50_wndw_ntfy_enable(wndw, asyw);
2358 drm_atomic_state_get(state);
2361 * Grab another RPM ref for the commit tail, which will release the
2362 * ref when it's finished
2364 pm_runtime_get_noresume(dev->dev);
2367 queue_work(system_unbound_wq, &state->commit_work);
2369 nv50_disp_atomic_commit_tail(state);
2373 drm_atomic_helper_cleanup_planes(dev, state);
2375 pm_runtime_put_autosuspend(dev->dev);
2379 static struct nv50_outp_atom *
2380 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2382 struct nv50_outp_atom *outp;
2384 list_for_each_entry(outp, &atom->outp, head) {
2385 if (outp->encoder == encoder)
2389 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2391 return ERR_PTR(-ENOMEM);
2393 list_add(&outp->head, &atom->outp);
2394 outp->encoder = encoder;
2399 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2400 struct drm_connector_state *old_connector_state)
2402 struct drm_encoder *encoder = old_connector_state->best_encoder;
2403 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2404 struct drm_crtc *crtc;
2405 struct nv50_outp_atom *outp;
2407 if (!(crtc = old_connector_state->crtc))
2410 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2411 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2412 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2413 outp = nv50_disp_outp_atomic_add(atom, encoder);
2415 return PTR_ERR(outp);
2417 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2418 outp->flush_disable = true;
2419 atom->flush_disable = true;
2421 outp->clr.ctrl = true;
2422 atom->lock_core = true;
2429 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2430 struct drm_connector_state *connector_state)
2432 struct drm_encoder *encoder = connector_state->best_encoder;
2433 struct drm_crtc_state *new_crtc_state;
2434 struct drm_crtc *crtc;
2435 struct nv50_outp_atom *outp;
2437 if (!(crtc = connector_state->crtc))
2440 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2441 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2442 outp = nv50_disp_outp_atomic_add(atom, encoder);
2444 return PTR_ERR(outp);
2446 outp->set.ctrl = true;
2447 atom->lock_core = true;
2454 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2456 struct nv50_atom *atom = nv50_atom(state);
2457 struct nv50_core *core = nv50_disp(dev)->core;
2458 struct drm_connector_state *old_connector_state, *new_connector_state;
2459 struct drm_connector *connector;
2460 struct drm_crtc_state *new_crtc_state;
2461 struct drm_crtc *crtc;
2462 struct nv50_head *head;
2463 struct nv50_head_atom *asyh;
2466 if (core->assign_windows && core->func->head->static_wndw_map) {
2467 drm_for_each_crtc(crtc, dev) {
2468 new_crtc_state = drm_atomic_get_crtc_state(state,
2470 if (IS_ERR(new_crtc_state))
2471 return PTR_ERR(new_crtc_state);
2473 head = nv50_head(crtc);
2474 asyh = nv50_head_atom(new_crtc_state);
2475 core->func->head->static_wndw_map(head, asyh);
2479 /* We need to handle colour management on a per-plane basis. */
2480 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2481 if (new_crtc_state->color_mgmt_changed) {
2482 ret = drm_atomic_add_affected_planes(state, crtc);
2488 ret = drm_atomic_helper_check(dev, state);
2492 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2493 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2497 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2502 ret = drm_dp_mst_atomic_check(state);
2506 nv50_crc_atomic_check_outp(atom);
2512 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2514 struct nv50_atom *atom = nv50_atom(state);
2515 struct nv50_outp_atom *outp, *outt;
2517 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2518 list_del(&outp->head);
2522 drm_atomic_state_default_clear(state);
2526 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2528 struct nv50_atom *atom = nv50_atom(state);
2529 drm_atomic_state_default_release(&atom->state);
2533 static struct drm_atomic_state *
2534 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2536 struct nv50_atom *atom;
2537 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2538 drm_atomic_state_init(dev, &atom->state) < 0) {
2542 INIT_LIST_HEAD(&atom->outp);
2543 return &atom->state;
2546 static const struct drm_mode_config_funcs
2548 .fb_create = nouveau_user_framebuffer_create,
2549 .output_poll_changed = nouveau_fbcon_output_poll_changed,
2550 .atomic_check = nv50_disp_atomic_check,
2551 .atomic_commit = nv50_disp_atomic_commit,
2552 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2553 .atomic_state_clear = nv50_disp_atomic_state_clear,
2554 .atomic_state_free = nv50_disp_atomic_state_free,
2557 /******************************************************************************
2559 *****************************************************************************/
2562 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend)
2564 struct nouveau_drm *drm = nouveau_drm(dev);
2565 struct drm_encoder *encoder;
2566 struct drm_plane *plane;
2568 drm_for_each_plane(plane, dev) {
2569 struct nv50_wndw *wndw = nv50_wndw(plane);
2570 if (plane->funcs != &nv50_wndw)
2572 nv50_wndw_fini(wndw);
2575 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2576 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
2577 nv50_mstm_fini(nouveau_encoder(encoder));
2581 cancel_work_sync(&drm->hpd_work);
2585 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2587 struct nv50_core *core = nv50_disp(dev)->core;
2588 struct drm_encoder *encoder;
2589 struct drm_plane *plane;
2591 if (resume || runtime)
2592 core->func->init(core);
2594 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2595 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2596 struct nouveau_encoder *nv_encoder =
2597 nouveau_encoder(encoder);
2598 nv50_mstm_init(nv_encoder, runtime);
2602 drm_for_each_plane(plane, dev) {
2603 struct nv50_wndw *wndw = nv50_wndw(plane);
2604 if (plane->funcs != &nv50_wndw)
2606 nv50_wndw_init(wndw);
2613 nv50_display_destroy(struct drm_device *dev)
2615 struct nv50_disp *disp = nv50_disp(dev);
2617 nv50_audio_component_fini(nouveau_drm(dev));
2619 nvif_object_unmap(&disp->caps);
2620 nvif_object_dtor(&disp->caps);
2621 nv50_core_del(&disp->core);
2623 nouveau_bo_unmap(disp->sync);
2625 nouveau_bo_unpin(disp->sync);
2626 nouveau_bo_ref(NULL, &disp->sync);
2628 nouveau_display(dev)->priv = NULL;
2633 nv50_display_create(struct drm_device *dev)
2635 struct nvif_device *device = &nouveau_drm(dev)->client.device;
2636 struct nouveau_drm *drm = nouveau_drm(dev);
2637 struct dcb_table *dcb = &drm->vbios.dcb;
2638 struct drm_connector *connector, *tmp;
2639 struct nv50_disp *disp;
2640 struct dcb_output *dcbe;
2642 bool has_mst = nv50_has_mst(drm);
2644 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2648 mutex_init(&disp->mutex);
2650 nouveau_display(dev)->priv = disp;
2651 nouveau_display(dev)->dtor = nv50_display_destroy;
2652 nouveau_display(dev)->init = nv50_display_init;
2653 nouveau_display(dev)->fini = nv50_display_fini;
2654 disp->disp = &nouveau_display(dev)->disp;
2655 dev->mode_config.funcs = &nv50_disp_func;
2656 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2657 dev->mode_config.normalize_zpos = true;
2659 /* small shared memory area we use for notifiers and semaphores */
2660 ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
2661 NOUVEAU_GEM_DOMAIN_VRAM,
2662 0, 0x0000, NULL, NULL, &disp->sync);
2664 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true);
2666 ret = nouveau_bo_map(disp->sync);
2668 nouveau_bo_unpin(disp->sync);
2671 nouveau_bo_ref(NULL, &disp->sync);
2677 /* allocate master evo channel */
2678 ret = nv50_core_new(drm, &disp->core);
2682 disp->core->func->init(disp->core);
2683 if (disp->core->func->caps_init) {
2684 ret = disp->core->func->caps_init(drm, disp);
2689 /* Assign the correct format modifiers */
2690 if (disp->disp->object.oclass >= TU102_DISP)
2691 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2693 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
2694 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2696 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2698 /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later
2699 * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The
2700 * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to
2701 * small page allocations in prepare_fb(). When this is implemented, we should also force
2702 * large pages (128K) for ovly fbs in order to fix Kepler ovlys.
2703 * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using
2706 if (disp->disp->object.oclass >= GM107_DISP) {
2707 dev->mode_config.cursor_width = 256;
2708 dev->mode_config.cursor_height = 256;
2709 } else if (disp->disp->object.oclass >= GK104_DISP) {
2710 dev->mode_config.cursor_width = 128;
2711 dev->mode_config.cursor_height = 128;
2713 dev->mode_config.cursor_width = 64;
2714 dev->mode_config.cursor_height = 64;
2717 /* create crtc objects to represent the hw heads */
2718 if (disp->disp->object.oclass >= GV100_DISP)
2719 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2721 if (disp->disp->object.oclass >= GF110_DISP)
2722 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2726 for (i = 0; i < fls(crtcs); i++) {
2727 struct nv50_head *head;
2729 if (!(crtcs & (1 << i)))
2732 head = nv50_head_create(dev, i);
2734 ret = PTR_ERR(head);
2739 head->msto = nv50_msto_new(dev, head, i);
2740 if (IS_ERR(head->msto)) {
2741 ret = PTR_ERR(head->msto);
2747 * FIXME: This is a hack to workaround the following
2750 * https://gitlab.gnome.org/GNOME/mutter/issues/759
2751 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
2753 * Once these issues are closed, this should be
2756 head->msto->encoder.possible_crtcs = crtcs;
2760 /* create encoder/connector objects based on VBIOS DCB table */
2761 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2762 connector = nouveau_connector_create(dev, dcbe);
2763 if (IS_ERR(connector))
2766 if (dcbe->location == DCB_LOC_ON_CHIP) {
2767 switch (dcbe->type) {
2768 case DCB_OUTPUT_TMDS:
2769 case DCB_OUTPUT_LVDS:
2771 ret = nv50_sor_create(connector, dcbe);
2773 case DCB_OUTPUT_ANALOG:
2774 ret = nv50_dac_create(connector, dcbe);
2781 ret = nv50_pior_create(connector, dcbe);
2785 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2786 dcbe->location, dcbe->type,
2787 ffs(dcbe->or) - 1, ret);
2792 /* cull any connectors we created that don't have an encoder */
2793 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2794 if (connector->possible_encoders)
2797 NV_WARN(drm, "%s has no encoders, removing\n",
2799 connector->funcs->destroy(connector);
2802 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2803 dev->vblank_disable_immediate = true;
2805 nv50_audio_component_init(drm);
2809 nv50_display_destroy(dev);
2813 /******************************************************************************
2815 *****************************************************************************/
2817 /****************************************************************
2818 * Log2(block height) ----------------------------+ *
2819 * Page Kind ----------------------------------+ | *
2820 * Gob Height/Page Kind Generation ------+ | | *
2821 * Sector layout -------+ | | | *
2822 * Compression ------+ | | | | */
2823 const u64 disp50xx_modifiers[] = { /* | | | | | */
2824 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2825 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2826 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2827 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2828 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2829 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2830 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2831 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2832 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2833 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2834 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2835 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2836 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2837 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2838 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2839 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2840 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2841 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2842 DRM_FORMAT_MOD_LINEAR,
2843 DRM_FORMAT_MOD_INVALID
2846 /****************************************************************
2847 * Log2(block height) ----------------------------+ *
2848 * Page Kind ----------------------------------+ | *
2849 * Gob Height/Page Kind Generation ------+ | | *
2850 * Sector layout -------+ | | | *
2851 * Compression ------+ | | | | */
2852 const u64 disp90xx_modifiers[] = { /* | | | | | */
2853 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2854 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2855 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2856 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2857 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2858 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
2859 DRM_FORMAT_MOD_LINEAR,
2860 DRM_FORMAT_MOD_INVALID