drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29 #include "handles.h"
  30
  31 #include <linux/dma-mapping.h>
  32 #include <linux/hdmi.h>
  33 #include <linux/component.h>
  34 #include <linux/iopoll.h>
  35
  36 #include <drm/display/drm_dp_helper.h>
  37 #include <drm/display/drm_scdc_helper.h>
  38 #include <drm/drm_atomic.h>
  39 #include <drm/drm_atomic_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_fb_helper.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_vblank.h>
  44
  45 #include <nvif/push507c.h>
  46
  47 #include <nvif/class.h>
  48 #include <nvif/cl0002.h>
  49 #include <nvif/event.h>
  50 #include <nvif/if0012.h>
  51 #include <nvif/if0014.h>
  52 #include <nvif/timer.h>
  53
  54 #include <nvhw/class/cl507c.h>
  55 #include <nvhw/class/cl507d.h>
  56 #include <nvhw/class/cl837d.h>
  57 #include <nvhw/class/cl887d.h>
  58 #include <nvhw/class/cl907d.h>
  59 #include <nvhw/class/cl917d.h>
  60
  61 #include "nouveau_drv.h"
  62 #include "nouveau_dma.h"
  63 #include "nouveau_gem.h"
  64 #include "nouveau_connector.h"
  65 #include "nouveau_encoder.h"
  66 #include "nouveau_fence.h"
  67 #include "nv50_display.h"
  68
  69 #include <subdev/bios/dp.h>
  70
  71 /******************************************************************************
  72  * EVO channel
  73  *****************************************************************************/
  74
  75 static int
  76 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  77                  const s32 *oclass, u8 head, void *data, u32 size,
  78                  struct nv50_chan *chan)
  79 {
  80         struct nvif_sclass *sclass;
  81         int ret, i, n;
  82
  83         chan->device = device;
  84
  85         ret = n = nvif_object_sclass_get(disp, &sclass);
  86         if (ret < 0)
  87                 return ret;
  88
  89         while (oclass[0]) {
  90                 for (i = 0; i < n; i++) {
  91                         if (sclass[i].oclass == oclass[0]) {
  92                                 ret = nvif_object_ctor(disp, "kmsChan", 0,
  93                                                        oclass[0], data, size,
  94                                                        &chan->user);
  95                                 if (ret == 0)
  96                                         nvif_object_map(&chan->user, NULL, 0);
  97                                 nvif_object_sclass_put(&sclass);
  98                                 return ret;
  99                         }
 100                 }
 101                 oclass++;
 102         }
 103
 104         nvif_object_sclass_put(&sclass);
 105         return -ENOSYS;
 106 }
 107
 108 static void
 109 nv50_chan_destroy(struct nv50_chan *chan)
 110 {
 111         nvif_object_dtor(&chan->user);
 112 }
 113
 114 /******************************************************************************
 115  * DMA EVO channel
 116  *****************************************************************************/
 117
 118 void
 119 nv50_dmac_destroy(struct nv50_dmac *dmac)
 120 {
 121         nvif_object_dtor(&dmac->vram);
 122         nvif_object_dtor(&dmac->sync);
 123
 124         nv50_chan_destroy(&dmac->base);
 125
 126         nvif_mem_dtor(&dmac->_push.mem);
 127 }
 128
 129 static void
 130 nv50_dmac_kick(struct nvif_push *push)
 131 {
 132         struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
 133
 134         dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr;
 135         if (dmac->put != dmac->cur) {
 136                 /* Push buffer fetches are not coherent with BAR1, we need to ensure
 137                  * writes have been flushed right through to VRAM before writing PUT.
 138                  */
 139                 if (dmac->push->mem.type & NVIF_MEM_VRAM) {
 140                         struct nvif_device *device = dmac->base.device;
 141                         nvif_wr32(&device->object, 0x070000, 0x00000001);
 142                         nvif_msec(device, 2000,
 143                                 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 144                                         break;
 145                         );
 146                 }
 147
 148                 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
 149                 dmac->put = dmac->cur;
 150         }
 151
 152         push->bgn = push->cur;
 153 }
 154
 155 static int
 156 nv50_dmac_free(struct nv50_dmac *dmac)
 157 {
 158         u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
 159         if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
 160                 return get - dmac->cur - 5;
 161         return dmac->max - dmac->cur;
 162 }
 163
 164 static int
 165 nv50_dmac_wind(struct nv50_dmac *dmac)
 166 {
 167         /* Wait for GET to depart from the beginning of the push buffer to
 168          * prevent writing PUT == GET, which would be ignored by HW.
 169          */
 170         u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
 171         if (get == 0) {
 172                 /* Corner-case, HW idle, but non-committed work pending. */
 173                 if (dmac->put == 0)
 174                         nv50_dmac_kick(dmac->push);
 175
 176                 if (nvif_msec(dmac->base.device, 2000,
 177                         if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
 178                                 break;
 179                 ) < 0)
 180                         return -ETIMEDOUT;
 181         }
 182
 183         PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
 184         dmac->cur = 0;
 185         return 0;
 186 }
 187
 188 static int
 189 nv50_dmac_wait(struct nvif_push *push, u32 size)
 190 {
 191         struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
 192         int free;
 193
 194         if (WARN_ON(size > dmac->max))
 195                 return -EINVAL;
 196
 197         dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr;
 198         if (dmac->cur + size >= dmac->max) {
 199                 int ret = nv50_dmac_wind(dmac);
 200                 if (ret)
 201                         return ret;
 202
 203                 push->cur = dmac->_push.mem.object.map.ptr;
 204                 push->cur = push->cur + dmac->cur;
 205                 nv50_dmac_kick(push);
 206         }
 207
 208         if (nvif_msec(dmac->base.device, 2000,
 209                 if ((free = nv50_dmac_free(dmac)) >= size)
 210                         break;
 211         ) < 0) {
 212                 WARN_ON(1);
 213                 return -ETIMEDOUT;
 214         }
 215
 216         push->bgn = dmac->_push.mem.object.map.ptr;
 217         push->bgn = push->bgn + dmac->cur;
 218         push->cur = push->bgn;
 219         push->end = push->cur + free;
 220         return 0;
 221 }
 222
 223 MODULE_PARM_DESC(kms_vram_pushbuf, "Place EVO/NVD push buffers in VRAM (default: auto)");
 224 static int nv50_dmac_vram_pushbuf = -1;
 225 module_param_named(kms_vram_pushbuf, nv50_dmac_vram_pushbuf, int, 0400);
 226
 227 int
 228 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 229                  const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf,
 230                  struct nv50_dmac *dmac)
 231 {
 232         struct nouveau_cli *cli = (void *)device->object.client;
 233         struct nvif_disp_chan_v0 *args = data;
 234         u8 type = NVIF_MEM_COHERENT;
 235         int ret;
 236
 237         mutex_init(&dmac->lock);
 238
 239         /* Pascal added support for 47-bit physical addresses, but some
 240          * parts of EVO still only accept 40-bit PAs.
 241          *
 242          * To avoid issues on systems with large amounts of RAM, and on
 243          * systems where an IOMMU maps pages at a high address, we need
 244          * to allocate push buffers in VRAM instead.
 245          *
 246          * This appears to match NVIDIA's behaviour on Pascal.
 247          */
 248         if ((nv50_dmac_vram_pushbuf > 0) ||
 249             (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL))
 250                 type |= NVIF_MEM_VRAM;
 251
 252         ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
 253                                 &dmac->_push.mem);
 254         if (ret)
 255                 return ret;
 256
 257         dmac->ptr = dmac->_push.mem.object.map.ptr;
 258         dmac->_push.wait = nv50_dmac_wait;
 259         dmac->_push.kick = nv50_dmac_kick;
 260         dmac->push = &dmac->_push;
 261         dmac->push->bgn = dmac->_push.mem.object.map.ptr;
 262         dmac->push->cur = dmac->push->bgn;
 263         dmac->push->end = dmac->push->bgn;
 264         dmac->max = 0x1000/4 - 1;
 265
 266         /* EVO channels are affected by a HW bug where the last 12 DWORDs
 267          * of the push buffer aren't able to be used safely.
 268          */
 269         if (disp->oclass < GV100_DISP)
 270                 dmac->max -= 12;
 271
 272         args->pushbuf = nvif_handle(&dmac->_push.mem.object);
 273
 274         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 275                                &dmac->base);
 276         if (ret)
 277                 return ret;
 278
 279         if (syncbuf < 0)
 280                 return 0;
 281
 282         ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
 283                                NV_DMA_IN_MEMORY,
 284                                &(struct nv_dma_v0) {
 285                                         .target = NV_DMA_V0_TARGET_VRAM,
 286                                         .access = NV_DMA_V0_ACCESS_RDWR,
 287                                         .start = syncbuf + 0x0000,
 288                                         .limit = syncbuf + 0x0fff,
 289                                }, sizeof(struct nv_dma_v0),
 290                                &dmac->sync);
 291         if (ret)
 292                 return ret;
 293
 294         ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
 295                                NV_DMA_IN_MEMORY,
 296                                &(struct nv_dma_v0) {
 297                                         .target = NV_DMA_V0_TARGET_VRAM,
 298                                         .access = NV_DMA_V0_ACCESS_RDWR,
 299                                         .start = 0,
 300                                         .limit = device->info.ram_user - 1,
 301                                }, sizeof(struct nv_dma_v0),
 302                                &dmac->vram);
 303         if (ret)
 304                 return ret;
 305
 306         return ret;
 307 }
 308
 309 /******************************************************************************
 310  * Output path helpers
 311  *****************************************************************************/
 312 static void
 313 nv50_outp_dump_caps(struct nouveau_drm *drm,
 314                     struct nouveau_encoder *outp)
 315 {
 316         NV_DEBUG(drm, "%s caps: dp_interlace=%d\n",
 317                  outp->base.base.name, outp->caps.dp_interlace);
 318 }
 319
 320 static int
 321 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 322                             struct drm_crtc_state *crtc_state,
 323                             struct drm_connector_state *conn_state,
 324                             struct drm_display_mode *native_mode)
 325 {
 326         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 327         struct drm_display_mode *mode = &crtc_state->mode;
 328         struct drm_connector *connector = conn_state->connector;
 329         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 330         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 331
 332         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 333         asyc->scaler.full = false;
 334         if (!native_mode)
 335                 return 0;
 336
 337         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 338                 switch (connector->connector_type) {
 339                 case DRM_MODE_CONNECTOR_LVDS:
 340                 case DRM_MODE_CONNECTOR_eDP:
 341                         /* Don't force scaler for EDID modes with
 342                          * same size as the native one (e.g. different
 343                          * refresh rate)
 344                          */
 345                         if (mode->hdisplay == native_mode->hdisplay &&
 346                             mode->vdisplay == native_mode->vdisplay &&
 347                             mode->type & DRM_MODE_TYPE_DRIVER)
 348                                 break;
 349                         mode = native_mode;
 350                         asyc->scaler.full = true;
 351                         break;
 352                 default:
 353                         break;
 354                 }
 355         } else {
 356                 mode = native_mode;
 357         }
 358
 359         if (!drm_mode_equal(adjusted_mode, mode)) {
 360                 drm_mode_copy(adjusted_mode, mode);
 361                 crtc_state->mode_changed = true;
 362         }
 363
 364         return 0;
 365 }
 366
 367 static void
 368 nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state)
 369 {
 370         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 371         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 372         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
 373         unsigned int max_rate, mode_rate;
 374
 375         switch (nv_encoder->dcb->type) {
 376         case DCB_OUTPUT_DP:
 377                 max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw;
 378
 379                 /* we don't support more than 10 anyway */
 380                 asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
 381
 382                 /* reduce the bpc until it works out */
 383                 while (asyh->or.bpc > 6) {
 384                         mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
 385                         if (mode_rate <= max_rate)
 386                                 break;
 387
 388                         asyh->or.bpc -= 2;
 389                 }
 390                 break;
 391         default:
 392                 break;
 393         }
 394 }
 395
 396 static int
 397 nv50_outp_atomic_check(struct drm_encoder *encoder,
 398                        struct drm_crtc_state *crtc_state,
 399                        struct drm_connector_state *conn_state)
 400 {
 401         struct drm_connector *connector = conn_state->connector;
 402         struct nouveau_connector *nv_connector = nouveau_connector(connector);
 403         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 404         int ret;
 405
 406         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 407                                           nv_connector->native_mode);
 408         if (ret)
 409                 return ret;
 410
 411         if (crtc_state->mode_changed || crtc_state->connectors_changed)
 412                 asyh->or.bpc = connector->display_info.bpc;
 413
 414         /* We might have to reduce the bpc */
 415         nv50_outp_atomic_fix_depth(encoder, crtc_state);
 416
 417         return 0;
 418 }
 419
 420 struct nouveau_connector *
 421 nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
 422 {
 423         struct drm_connector *connector;
 424         struct drm_connector_state *connector_state;
 425         struct drm_encoder *encoder = to_drm_encoder(outp);
 426         int i;
 427
 428         for_each_new_connector_in_state(state, connector, connector_state, i) {
 429                 if (connector_state->best_encoder == encoder)
 430                         return nouveau_connector(connector);
 431         }
 432
 433         return NULL;
 434 }
 435
 436 struct nouveau_connector *
 437 nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
 438 {
 439         struct drm_connector *connector;
 440         struct drm_connector_state *connector_state;
 441         struct drm_encoder *encoder = to_drm_encoder(outp);
 442         int i;
 443
 444         for_each_old_connector_in_state(state, connector, connector_state, i) {
 445                 if (connector_state->best_encoder == encoder)
 446                         return nouveau_connector(connector);
 447         }
 448
 449         return NULL;
 450 }
 451
 452 static struct nouveau_crtc *
 453 nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp)
 454 {
 455         struct drm_crtc *crtc;
 456         struct drm_crtc_state *crtc_state;
 457         const u32 mask = drm_encoder_mask(&outp->base.base);
 458         int i;
 459
 460         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 461                 if (crtc_state->encoder_mask & mask)
 462                         return nouveau_crtc(crtc);
 463         }
 464
 465         return NULL;
 466 }
 467
 468 /******************************************************************************
 469  * DAC
 470  *****************************************************************************/
 471 static void
 472 nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
 473 {
 474         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 475         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 476         const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
 477
 478         core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL);
 479         nv_encoder->crtc = NULL;
 480         nvif_outp_release(&nv_encoder->outp);
 481 }
 482
 483 static void
 484 nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
 485 {
 486         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 487         struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
 488         struct nv50_head_atom *asyh =
 489                 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
 490         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 491         u32 ctrl = 0;
 492
 493         switch (nv_crtc->index) {
 494         case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
 495         case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
 496         case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
 497         case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
 498         default:
 499                 WARN_ON(1);
 500                 break;
 501         }
 502
 503         ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
 504
 505         nvif_outp_acquire_rgb_crt(&nv_encoder->outp);
 506
 507         core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
 508         asyh->or.depth = 0;
 509
 510         nv_encoder->crtc = &nv_crtc->base;
 511 }
 512
 513 static enum drm_connector_status
 514 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 515 {
 516         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 517         u32 loadval;
 518         int ret;
 519
 520         loadval = nouveau_drm(encoder->dev)->vbios.dactestval;
 521         if (loadval == 0)
 522                 loadval = 340;
 523
 524         ret = nvif_outp_load_detect(&nv_encoder->outp, loadval);
 525         if (ret <= 0)
 526                 return connector_status_disconnected;
 527
 528         return connector_status_connected;
 529 }
 530
 531 static const struct drm_encoder_helper_funcs
 532 nv50_dac_help = {
 533         .atomic_check = nv50_outp_atomic_check,
 534         .atomic_enable = nv50_dac_atomic_enable,
 535         .atomic_disable = nv50_dac_atomic_disable,
 536         .detect = nv50_dac_detect
 537 };
 538
 539 static void
 540 nv50_dac_destroy(struct drm_encoder *encoder)
 541 {
 542         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 543
 544         nvif_outp_dtor(&nv_encoder->outp);
 545
 546         drm_encoder_cleanup(encoder);
 547         kfree(encoder);
 548 }
 549
 550 static const struct drm_encoder_funcs
 551 nv50_dac_func = {
 552         .destroy = nv50_dac_destroy,
 553 };
 554
 555 static int
 556 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 557 {
 558         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 559         struct nv50_disp *disp = nv50_disp(connector->dev);
 560         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 561         struct nvkm_i2c_bus *bus;
 562         struct nouveau_encoder *nv_encoder;
 563         struct drm_encoder *encoder;
 564         int type = DRM_MODE_ENCODER_DAC;
 565
 566         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 567         if (!nv_encoder)
 568                 return -ENOMEM;
 569         nv_encoder->dcb = dcbe;
 570
 571         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 572         if (bus)
 573                 nv_encoder->i2c = &bus->i2c;
 574
 575         encoder = to_drm_encoder(nv_encoder);
 576         encoder->possible_crtcs = dcbe->heads;
 577         encoder->possible_clones = 0;
 578         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 579                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 580         drm_encoder_helper_add(encoder, &nv50_dac_help);
 581
 582         drm_connector_attach_encoder(connector, encoder);
 583         return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp);
 584 }
 585
 586 /*
 587  * audio component binding for ELD notification
 588  */
 589 static void
 590 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
 591                                 int dev_id)
 592 {
 593         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 594                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 595                                                  port, dev_id);
 596 }
 597
 598 static int
 599 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
 600                              bool *enabled, unsigned char *buf, int max_bytes)
 601 {
 602         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 603         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 604         struct drm_encoder *encoder;
 605         struct nouveau_encoder *nv_encoder;
 606         struct nouveau_crtc *nv_crtc;
 607         int ret = 0;
 608
 609         *enabled = false;
 610
 611         mutex_lock(&drm->audio.lock);
 612
 613         drm_for_each_encoder(encoder, drm->dev) {
 614                 struct nouveau_connector *nv_connector = NULL;
 615
 616                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST)
 617                         continue; /* TODO */
 618
 619                 nv_encoder = nouveau_encoder(encoder);
 620                 nv_connector = nouveau_connector(nv_encoder->audio.connector);
 621                 nv_crtc = nouveau_crtc(nv_encoder->crtc);
 622
 623                 if (!nv_crtc || nv_encoder->outp.or.id != port || nv_crtc->index != dev_id)
 624                         continue;
 625
 626                 *enabled = nv_encoder->audio.enabled;
 627                 if (*enabled) {
 628                         ret = drm_eld_size(nv_connector->base.eld);
 629                         memcpy(buf, nv_connector->base.eld,
 630                                min(max_bytes, ret));
 631                 }
 632                 break;
 633         }
 634
 635         mutex_unlock(&drm->audio.lock);
 636
 637         return ret;
 638 }
 639
 640 static const struct drm_audio_component_ops nv50_audio_component_ops = {
 641         .get_eld = nv50_audio_component_get_eld,
 642 };
 643
 644 static int
 645 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
 646                           void *data)
 647 {
 648         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 649         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 650         struct drm_audio_component *acomp = data;
 651
 652         if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
 653                 return -ENOMEM;
 654
 655         drm_modeset_lock_all(drm_dev);
 656         acomp->ops = &nv50_audio_component_ops;
 657         acomp->dev = kdev;
 658         drm->audio.component = acomp;
 659         drm_modeset_unlock_all(drm_dev);
 660         return 0;
 661 }
 662
 663 static void
 664 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
 665                             void *data)
 666 {
 667         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 668         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 669         struct drm_audio_component *acomp = data;
 670
 671         drm_modeset_lock_all(drm_dev);
 672         drm->audio.component = NULL;
 673         acomp->ops = NULL;
 674         acomp->dev = NULL;
 675         drm_modeset_unlock_all(drm_dev);
 676 }
 677
 678 static const struct component_ops nv50_audio_component_bind_ops = {
 679         .bind   = nv50_audio_component_bind,
 680         .unbind = nv50_audio_component_unbind,
 681 };
 682
 683 static void
 684 nv50_audio_component_init(struct nouveau_drm *drm)
 685 {
 686         if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
 687                 return;
 688
 689         drm->audio.component_registered = true;
 690         mutex_init(&drm->audio.lock);
 691 }
 692
 693 static void
 694 nv50_audio_component_fini(struct nouveau_drm *drm)
 695 {
 696         if (!drm->audio.component_registered)
 697                 return;
 698
 699         component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
 700         drm->audio.component_registered = false;
 701         mutex_destroy(&drm->audio.lock);
 702 }
 703
 704 /******************************************************************************
 705  * Audio
 706  *****************************************************************************/
 707 static bool
 708 nv50_audio_supported(struct drm_encoder *encoder)
 709 {
 710         struct nv50_disp *disp = nv50_disp(encoder->dev);
 711
 712         if (disp->disp->object.oclass <= GT200_DISP ||
 713             disp->disp->object.oclass == GT206_DISP)
 714                 return false;
 715
 716         return true;
 717 }
 718
 719 static void
 720 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 721 {
 722         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 723         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 724         struct nvif_outp *outp = &nv_encoder->outp;
 725
 726         if (!nv50_audio_supported(encoder))
 727                 return;
 728
 729         mutex_lock(&drm->audio.lock);
 730         if (nv_encoder->audio.enabled) {
 731                 nv_encoder->audio.enabled = false;
 732                 nv_encoder->audio.connector = NULL;
 733                 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, NULL, 0);
 734         }
 735         mutex_unlock(&drm->audio.lock);
 736
 737         nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
 738 }
 739
 740 static void
 741 nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
 742                   struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
 743                   struct drm_display_mode *mode)
 744 {
 745         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 746         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 747         struct nvif_outp *outp = &nv_encoder->outp;
 748
 749         if (!nv50_audio_supported(encoder) || !drm_detect_monitor_audio(nv_connector->edid))
 750                 return;
 751
 752         mutex_lock(&drm->audio.lock);
 753
 754         nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, nv_connector->base.eld,
 755                           drm_eld_size(nv_connector->base.eld));
 756         nv_encoder->audio.enabled = true;
 757         nv_encoder->audio.connector = &nv_connector->base;
 758
 759         mutex_unlock(&drm->audio.lock);
 760
 761         nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
 762 }
 763
 764 /******************************************************************************
 765  * HDMI
 766  *****************************************************************************/
 767 static void
 768 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
 769                  struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
 770                  struct drm_display_mode *mode, bool hda)
 771 {
 772         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 773         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 774         struct drm_hdmi_info *hdmi = &nv_connector->base.display_info.hdmi;
 775         union hdmi_infoframe infoframe = { 0 };
 776         const u8 rekey = 56; /* binary driver, and tegra, constant */
 777         u8 scdc = 0;
 778         u32 max_ac_packet;
 779         struct {
 780                 struct nvif_outp_infoframe_v0 infoframe;
 781                 u8 data[17];
 782         } args = { 0 };
 783         int ret, size;
 784
 785         max_ac_packet  = mode->htotal - mode->hdisplay;
 786         max_ac_packet -= rekey;
 787         max_ac_packet -= 18; /* constant from tegra */
 788         max_ac_packet /= 32;
 789
 790         if (hdmi->scdc.scrambling.supported) {
 791                 const bool high_tmds_clock_ratio = mode->clock > 340000;
 792
 793                 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &scdc);
 794                 if (ret < 0) {
 795                         NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 796                         return;
 797                 }
 798
 799                 scdc &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 800                 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates)
 801                         scdc |= SCDC_SCRAMBLING_ENABLE;
 802                 if (high_tmds_clock_ratio)
 803                         scdc |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
 804
 805                 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, scdc);
 806                 if (ret < 0)
 807                         NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 808                                  scdc, ret);
 809         }
 810
 811         ret = nvif_outp_acquire_tmds(&nv_encoder->outp, nv_crtc->index, true,
 812                                      max_ac_packet, rekey, scdc, hda);
 813         if (ret)
 814                 return;
 815
 816         /* AVI InfoFrame. */
 817         args.infoframe.version = 0;
 818         args.infoframe.head = nv_crtc->index;
 819
 820         if (!drm_hdmi_avi_infoframe_from_display_mode(&infoframe.avi, &nv_connector->base, mode)) {
 821                 drm_hdmi_avi_infoframe_quant_range(&infoframe.avi, &nv_connector->base, mode,
 822                                                    HDMI_QUANTIZATION_RANGE_FULL);
 823
 824                 size = hdmi_infoframe_pack(&infoframe, args.data, ARRAY_SIZE(args.data));
 825         } else {
 826                 size = 0;
 827         }
 828
 829         nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_AVI, &args.infoframe, size);
 830
 831         /* Vendor InfoFrame. */
 832         memset(&args.data, 0, sizeof(args.data));
 833         if (!drm_hdmi_vendor_infoframe_from_display_mode(&infoframe.vendor.hdmi,
 834                                                          &nv_connector->base, mode))
 835                 size = hdmi_infoframe_pack(&infoframe, args.data, ARRAY_SIZE(args.data));
 836         else
 837                 size = 0;
 838
 839         nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_VSI, &args.infoframe, size);
 840
 841         nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
 842 }
 843
 844 /******************************************************************************
 845  * MST
 846  *****************************************************************************/
 847 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 848 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 849 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 850
 851 struct nv50_mstc {
 852         struct nv50_mstm *mstm;
 853         struct drm_dp_mst_port *port;
 854         struct drm_connector connector;
 855
 856         struct drm_display_mode *native;
 857         struct edid *edid;
 858 };
 859
 860 struct nv50_msto {
 861         struct drm_encoder encoder;
 862
 863         /* head is statically assigned on msto creation */
 864         struct nv50_head *head;
 865         struct nv50_mstc *mstc;
 866         bool disabled;
 867         bool enabled;
 868 };
 869
 870 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder)
 871 {
 872         struct nv50_msto *msto;
 873
 874         if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
 875                 return nouveau_encoder(encoder);
 876
 877         msto = nv50_msto(encoder);
 878         if (!msto->mstc)
 879                 return NULL;
 880         return msto->mstc->mstm->outp;
 881 }
 882
 883 static void
 884 nv50_msto_cleanup(struct drm_atomic_state *state,
 885                   struct drm_dp_mst_topology_state *mst_state,
 886                   struct drm_dp_mst_topology_mgr *mgr,
 887                   struct nv50_msto *msto)
 888 {
 889         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 890         struct drm_dp_mst_atomic_payload *payload =
 891                 drm_atomic_get_mst_payload_state(mst_state, msto->mstc->port);
 892
 893         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 894
 895         if (msto->disabled) {
 896                 msto->mstc = NULL;
 897                 msto->disabled = false;
 898         } else if (msto->enabled) {
 899                 drm_dp_add_payload_part2(mgr, state, payload);
 900                 msto->enabled = false;
 901         }
 902 }
 903
 904 static void
 905 nv50_msto_prepare(struct drm_atomic_state *state,
 906                   struct drm_dp_mst_topology_state *mst_state,
 907                   struct drm_dp_mst_topology_mgr *mgr,
 908                   struct nv50_msto *msto)
 909 {
 910         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 911         struct nv50_mstc *mstc = msto->mstc;
 912         struct nv50_mstm *mstm = mstc->mstm;
 913         struct drm_dp_mst_topology_state *old_mst_state;
 914         struct drm_dp_mst_atomic_payload *payload, *old_payload;
 915
 916         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 917
 918         old_mst_state = drm_atomic_get_old_mst_topology_state(state, mgr);
 919
 920         payload = drm_atomic_get_mst_payload_state(mst_state, mstc->port);
 921         old_payload = drm_atomic_get_mst_payload_state(old_mst_state, mstc->port);
 922
 923         // TODO: Figure out if we want to do a better job of handling VCPI allocation failures here?
 924         if (msto->disabled) {
 925                 drm_dp_remove_payload(mgr, mst_state, old_payload, payload);
 926
 927                 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0);
 928         } else {
 929                 if (msto->enabled)
 930                         drm_dp_add_payload_part1(mgr, mst_state, payload);
 931
 932                 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index,
 933                                       payload->vc_start_slot, payload->time_slots,
 934                                       payload->pbn, payload->time_slots * mst_state->pbn_div);
 935         }
 936 }
 937
 938 static int
 939 nv50_msto_atomic_check(struct drm_encoder *encoder,
 940                        struct drm_crtc_state *crtc_state,
 941                        struct drm_connector_state *conn_state)
 942 {
 943         struct drm_atomic_state *state = crtc_state->state;
 944         struct drm_connector *connector = conn_state->connector;
 945         struct drm_dp_mst_topology_state *mst_state;
 946         struct nv50_mstc *mstc = nv50_mstc(connector);
 947         struct nv50_mstm *mstm = mstc->mstm;
 948         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 949         int slots;
 950         int ret;
 951
 952         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 953                                           mstc->native);
 954         if (ret)
 955                 return ret;
 956
 957         if (!drm_atomic_crtc_needs_modeset(crtc_state))
 958                 return 0;
 959
 960         /*
 961          * When restoring duplicated states, we need to make sure that the bw
 962          * remains the same and avoid recalculating it, as the connector's bpc
 963          * may have changed after the state was duplicated
 964          */
 965         if (!state->duplicated) {
 966                 const int clock = crtc_state->adjusted_mode.clock;
 967
 968                 asyh->or.bpc = connector->display_info.bpc;
 969                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
 970                                                     false);
 971         }
 972
 973         mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
 974         if (IS_ERR(mst_state))
 975                 return PTR_ERR(mst_state);
 976
 977         if (!mst_state->pbn_div) {
 978                 struct nouveau_encoder *outp = mstc->mstm->outp;
 979
 980                 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr,
 981                                                               outp->dp.link_bw, outp->dp.link_nr);
 982         }
 983
 984         slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);
 985         if (slots < 0)
 986                 return slots;
 987
 988         asyh->dp.tu = slots;
 989
 990         return 0;
 991 }
 992
 993 static u8
 994 nv50_dp_bpc_to_depth(unsigned int bpc)
 995 {
 996         switch (bpc) {
 997         case  6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
 998         case  8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
 999         case 10:
1000         default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
1001         }
1002 }
1003
1004 static void
1005 nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1006 {
1007         struct nv50_msto *msto = nv50_msto(encoder);
1008         struct nv50_head *head = msto->head;
1009         struct nv50_head_atom *asyh =
1010                 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base));
1011         struct nv50_mstc *mstc = NULL;
1012         struct nv50_mstm *mstm = NULL;
1013         struct drm_connector *connector;
1014         struct drm_connector_list_iter conn_iter;
1015         u8 proto;
1016
1017         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
1018         drm_for_each_connector_iter(connector, &conn_iter) {
1019                 if (connector->state->best_encoder == &msto->encoder) {
1020                         mstc = nv50_mstc(connector);
1021                         mstm = mstc->mstm;
1022                         break;
1023                 }
1024         }
1025         drm_connector_list_iter_end(&conn_iter);
1026
1027         if (WARN_ON(!mstc))
1028                 return;
1029
1030         if (!mstm->links++) {
1031                 /*XXX: MST audio. */
1032                 nvif_outp_acquire_dp(&mstm->outp->outp, mstm->outp->dp.dpcd, 0, 0, false, true);
1033         }
1034
1035         if (mstm->outp->outp.or.link & 1)
1036                 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1037         else
1038                 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1039
1040         mstm->outp->update(mstm->outp, head->base.index, asyh, proto,
1041                            nv50_dp_bpc_to_depth(asyh->or.bpc));
1042
1043         msto->mstc = mstc;
1044         msto->enabled = true;
1045         mstm->modified = true;
1046 }
1047
1048 static void
1049 nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1050 {
1051         struct nv50_msto *msto = nv50_msto(encoder);
1052         struct nv50_mstc *mstc = msto->mstc;
1053         struct nv50_mstm *mstm = mstc->mstm;
1054
1055         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
1056         mstm->modified = true;
1057         if (!--mstm->links)
1058                 mstm->disabled = true;
1059         msto->disabled = true;
1060 }
1061
1062 static const struct drm_encoder_helper_funcs
1063 nv50_msto_help = {
1064         .atomic_disable = nv50_msto_atomic_disable,
1065         .atomic_enable = nv50_msto_atomic_enable,
1066         .atomic_check = nv50_msto_atomic_check,
1067 };
1068
1069 static void
1070 nv50_msto_destroy(struct drm_encoder *encoder)
1071 {
1072         struct nv50_msto *msto = nv50_msto(encoder);
1073         drm_encoder_cleanup(&msto->encoder);
1074         kfree(msto);
1075 }
1076
1077 static const struct drm_encoder_funcs
1078 nv50_msto = {
1079         .destroy = nv50_msto_destroy,
1080 };
1081
1082 static struct nv50_msto *
1083 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1084 {
1085         struct nv50_msto *msto;
1086         int ret;
1087
1088         msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1089         if (!msto)
1090                 return ERR_PTR(-ENOMEM);
1091
1092         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1093                                DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1094         if (ret) {
1095                 kfree(msto);
1096                 return ERR_PTR(ret);
1097         }
1098
1099         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1100         msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1101         msto->head = head;
1102         return msto;
1103 }
1104
1105 static struct drm_encoder *
1106 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1107                               struct drm_atomic_state *state)
1108 {
1109         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1110                                                                                          connector);
1111         struct nv50_mstc *mstc = nv50_mstc(connector);
1112         struct drm_crtc *crtc = connector_state->crtc;
1113
1114         if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1115                 return NULL;
1116
1117         return &nv50_head(crtc)->msto->encoder;
1118 }
1119
1120 static enum drm_mode_status
1121 nv50_mstc_mode_valid(struct drm_connector *connector,
1122                      struct drm_display_mode *mode)
1123 {
1124         struct nv50_mstc *mstc = nv50_mstc(connector);
1125         struct nouveau_encoder *outp = mstc->mstm->outp;
1126
1127         /* TODO: calculate the PBN from the dotclock and validate against the
1128          * MSTB's max possible PBN
1129          */
1130
1131         return nv50_dp_mode_valid(outp, mode, NULL);
1132 }
1133
1134 static int
1135 nv50_mstc_get_modes(struct drm_connector *connector)
1136 {
1137         struct nv50_mstc *mstc = nv50_mstc(connector);
1138         int ret = 0;
1139
1140         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1141         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1142         if (mstc->edid)
1143                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1144
1145         /*
1146          * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1147          * to 8 to save bandwidth on the topology. In the future, we'll want
1148          * to properly fix this by dynamically selecting the highest possible
1149          * bpc that would fit in the topology
1150          */
1151         if (connector->display_info.bpc)
1152                 connector->display_info.bpc =
1153                         clamp(connector->display_info.bpc, 6U, 8U);
1154         else
1155                 connector->display_info.bpc = 8;
1156
1157         if (mstc->native)
1158                 drm_mode_destroy(mstc->connector.dev, mstc->native);
1159         mstc->native = nouveau_conn_native_mode(&mstc->connector);
1160         return ret;
1161 }
1162
1163 static int
1164 nv50_mstc_atomic_check(struct drm_connector *connector,
1165                        struct drm_atomic_state *state)
1166 {
1167         struct nv50_mstc *mstc = nv50_mstc(connector);
1168         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1169
1170         return drm_dp_atomic_release_time_slots(state, mgr, mstc->port);
1171 }
1172
1173 static int
1174 nv50_mstc_detect(struct drm_connector *connector,
1175                  struct drm_modeset_acquire_ctx *ctx, bool force)
1176 {
1177         struct nv50_mstc *mstc = nv50_mstc(connector);
1178         int ret;
1179
1180         if (drm_connector_is_unregistered(connector))
1181                 return connector_status_disconnected;
1182
1183         ret = pm_runtime_get_sync(connector->dev->dev);
1184         if (ret < 0 && ret != -EACCES) {
1185                 pm_runtime_put_autosuspend(connector->dev->dev);
1186                 return connector_status_disconnected;
1187         }
1188
1189         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1190                                      mstc->port);
1191         if (ret != connector_status_connected)
1192                 goto out;
1193
1194 out:
1195         pm_runtime_mark_last_busy(connector->dev->dev);
1196         pm_runtime_put_autosuspend(connector->dev->dev);
1197         return ret;
1198 }
1199
1200 static const struct drm_connector_helper_funcs
1201 nv50_mstc_help = {
1202         .get_modes = nv50_mstc_get_modes,
1203         .mode_valid = nv50_mstc_mode_valid,
1204         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1205         .atomic_check = nv50_mstc_atomic_check,
1206         .detect_ctx = nv50_mstc_detect,
1207 };
1208
1209 static void
1210 nv50_mstc_destroy(struct drm_connector *connector)
1211 {
1212         struct nv50_mstc *mstc = nv50_mstc(connector);
1213
1214         drm_connector_cleanup(&mstc->connector);
1215         drm_dp_mst_put_port_malloc(mstc->port);
1216
1217         kfree(mstc);
1218 }
1219
1220 static const struct drm_connector_funcs
1221 nv50_mstc = {
1222         .reset = nouveau_conn_reset,
1223         .fill_modes = drm_helper_probe_single_connector_modes,
1224         .destroy = nv50_mstc_destroy,
1225         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1226         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1227         .atomic_set_property = nouveau_conn_atomic_set_property,
1228         .atomic_get_property = nouveau_conn_atomic_get_property,
1229 };
1230
1231 static int
1232 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1233               const char *path, struct nv50_mstc **pmstc)
1234 {
1235         struct drm_device *dev = mstm->outp->base.base.dev;
1236         struct drm_crtc *crtc;
1237         struct nv50_mstc *mstc;
1238         int ret;
1239
1240         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1241                 return -ENOMEM;
1242         mstc->mstm = mstm;
1243         mstc->port = port;
1244
1245         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1246                                  DRM_MODE_CONNECTOR_DisplayPort);
1247         if (ret) {
1248                 kfree(*pmstc);
1249                 *pmstc = NULL;
1250                 return ret;
1251         }
1252
1253         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1254
1255         mstc->connector.funcs->reset(&mstc->connector);
1256         nouveau_conn_attach_properties(&mstc->connector);
1257
1258         drm_for_each_crtc(crtc, dev) {
1259                 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1260                         continue;
1261
1262                 drm_connector_attach_encoder(&mstc->connector,
1263                                              &nv50_head(crtc)->msto->encoder);
1264         }
1265
1266         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1267         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1268         drm_connector_set_path_property(&mstc->connector, path);
1269         drm_dp_mst_get_port_malloc(port);
1270         return 0;
1271 }
1272
1273 static void
1274 nv50_mstm_cleanup(struct drm_atomic_state *state,
1275                   struct drm_dp_mst_topology_state *mst_state,
1276                   struct nv50_mstm *mstm)
1277 {
1278         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1279         struct drm_encoder *encoder;
1280
1281         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1282         drm_dp_check_act_status(&mstm->mgr);
1283
1284         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1285                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1286                         struct nv50_msto *msto = nv50_msto(encoder);
1287                         struct nv50_mstc *mstc = msto->mstc;
1288                         if (mstc && mstc->mstm == mstm)
1289                                 nv50_msto_cleanup(state, mst_state, &mstm->mgr, msto);
1290                 }
1291         }
1292
1293         mstm->modified = false;
1294 }
1295
1296 static void
1297 nv50_mstm_prepare(struct drm_atomic_state *state,
1298                   struct drm_dp_mst_topology_state *mst_state,
1299                   struct nv50_mstm *mstm)
1300 {
1301         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1302         struct drm_encoder *encoder;
1303
1304         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1305
1306         /* Disable payloads first */
1307         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1308                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1309                         struct nv50_msto *msto = nv50_msto(encoder);
1310                         struct nv50_mstc *mstc = msto->mstc;
1311                         if (mstc && mstc->mstm == mstm && msto->disabled)
1312                                 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto);
1313                 }
1314         }
1315
1316         /* Add payloads for new heads, while also updating the start slots of any unmodified (but
1317          * active) heads that may have had their VC slots shifted left after the previous step
1318          */
1319         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1320                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1321                         struct nv50_msto *msto = nv50_msto(encoder);
1322                         struct nv50_mstc *mstc = msto->mstc;
1323                         if (mstc && mstc->mstm == mstm && !msto->disabled)
1324                                 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto);
1325                 }
1326         }
1327
1328         if (mstm->disabled) {
1329                 if (!mstm->links)
1330                         nvif_outp_release(&mstm->outp->outp);
1331                 mstm->disabled = false;
1332         }
1333 }
1334
1335 static struct drm_connector *
1336 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1337                         struct drm_dp_mst_port *port, const char *path)
1338 {
1339         struct nv50_mstm *mstm = nv50_mstm(mgr);
1340         struct nv50_mstc *mstc;
1341         int ret;
1342
1343         ret = nv50_mstc_new(mstm, port, path, &mstc);
1344         if (ret)
1345                 return NULL;
1346
1347         return &mstc->connector;
1348 }
1349
1350 static const struct drm_dp_mst_topology_cbs
1351 nv50_mstm = {
1352         .add_connector = nv50_mstm_add_connector,
1353 };
1354
1355 bool
1356 nv50_mstm_service(struct nouveau_drm *drm,
1357                   struct nouveau_connector *nv_connector,
1358                   struct nv50_mstm *mstm)
1359 {
1360         struct drm_dp_aux *aux = &nv_connector->aux;
1361         bool handled = true, ret = true;
1362         int rc;
1363         u8 esi[8] = {};
1364
1365         while (handled) {
1366                 u8 ack[8] = {};
1367
1368                 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1369                 if (rc != 8) {
1370                         ret = false;
1371                         break;
1372                 }
1373
1374                 drm_dp_mst_hpd_irq_handle_event(&mstm->mgr, esi, ack, &handled);
1375                 if (!handled)
1376                         break;
1377
1378                 rc = drm_dp_dpcd_writeb(aux, DP_SINK_COUNT_ESI + 1, ack[1]);
1379
1380                 if (rc != 1) {
1381                         ret = false;
1382                         break;
1383                 }
1384
1385                 drm_dp_mst_hpd_irq_send_new_request(&mstm->mgr);
1386         }
1387
1388         if (!ret)
1389                 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n",
1390                          nv_connector->base.name, rc);
1391
1392         return ret;
1393 }
1394
1395 void
1396 nv50_mstm_remove(struct nv50_mstm *mstm)
1397 {
1398         mstm->is_mst = false;
1399         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1400 }
1401
1402 int
1403 nv50_mstm_detect(struct nouveau_encoder *outp)
1404 {
1405         struct nv50_mstm *mstm = outp->dp.mstm;
1406         struct drm_dp_aux *aux;
1407         int ret;
1408
1409         if (!mstm || !mstm->can_mst)
1410                 return 0;
1411
1412         aux = mstm->mgr.aux;
1413
1414         /* Clear any leftover MST state we didn't set ourselves by first
1415          * disabling MST if it was already enabled
1416          */
1417         ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1418         if (ret < 0)
1419                 return ret;
1420
1421         /* And start enabling */
1422         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true);
1423         if (ret)
1424                 return ret;
1425
1426         mstm->is_mst = true;
1427         return 1;
1428 }
1429
1430 static void
1431 nv50_mstm_fini(struct nouveau_encoder *outp)
1432 {
1433         struct nv50_mstm *mstm = outp->dp.mstm;
1434
1435         if (!mstm)
1436                 return;
1437
1438         /* Don't change the MST state of this connector until we've finished
1439          * resuming, since we can't safely grab hpd_irq_lock in our resume
1440          * path to protect mstm->is_mst without potentially deadlocking
1441          */
1442         mutex_lock(&outp->dp.hpd_irq_lock);
1443         mstm->suspended = true;
1444         mutex_unlock(&outp->dp.hpd_irq_lock);
1445
1446         if (mstm->is_mst)
1447                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1448 }
1449
1450 static void
1451 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime)
1452 {
1453         struct nv50_mstm *mstm = outp->dp.mstm;
1454         int ret = 0;
1455
1456         if (!mstm)
1457                 return;
1458
1459         if (mstm->is_mst) {
1460                 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1461                 if (ret == -1)
1462                         nv50_mstm_remove(mstm);
1463         }
1464
1465         mutex_lock(&outp->dp.hpd_irq_lock);
1466         mstm->suspended = false;
1467         mutex_unlock(&outp->dp.hpd_irq_lock);
1468
1469         if (ret == -1)
1470                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1471 }
1472
1473 static void
1474 nv50_mstm_del(struct nv50_mstm **pmstm)
1475 {
1476         struct nv50_mstm *mstm = *pmstm;
1477         if (mstm) {
1478                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1479                 kfree(*pmstm);
1480                 *pmstm = NULL;
1481         }
1482 }
1483
1484 static int
1485 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1486               int conn_base_id, struct nv50_mstm **pmstm)
1487 {
1488         const int max_payloads = hweight8(outp->dcb->heads);
1489         struct drm_device *dev = outp->base.base.dev;
1490         struct nv50_mstm *mstm;
1491         int ret;
1492
1493         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1494                 return -ENOMEM;
1495         mstm->outp = outp;
1496         mstm->mgr.cbs = &nv50_mstm;
1497
1498         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1499                                            max_payloads, conn_base_id);
1500         if (ret)
1501                 return ret;
1502
1503         return 0;
1504 }
1505
1506 /******************************************************************************
1507  * SOR
1508  *****************************************************************************/
1509 static void
1510 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1511                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1512 {
1513         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1514         struct nv50_core *core = disp->core;
1515
1516         if (!asyh) {
1517                 nv_encoder->ctrl &= ~BIT(head);
1518                 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1519                         nv_encoder->ctrl = 0;
1520         } else {
1521                 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1522                 nv_encoder->ctrl |= BIT(head);
1523                 asyh->or.depth = depth;
1524         }
1525
1526         core->func->sor->ctrl(core, nv_encoder->outp.or.id, nv_encoder->ctrl, asyh);
1527 }
1528
1529 /* TODO: Should we extend this to PWM-only backlights?
1530  * As well, should we add a DRM helper for waiting for the backlight to acknowledge
1531  * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a
1532  * fixed time delay from the vbios…
1533  */
1534 static void
1535 nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1536 {
1537         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1538         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1539         struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder);
1540 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1541         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
1542         struct nouveau_backlight *backlight = nv_connector->backlight;
1543 #endif
1544         struct drm_dp_aux *aux = &nv_connector->aux;
1545         int ret;
1546         u8 pwr;
1547
1548 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1549         if (backlight && backlight->uses_dpcd) {
1550                 ret = drm_edp_backlight_disable(aux, &backlight->edp_info);
1551                 if (ret < 0)
1552                         NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n",
1553                                  nv_connector->base.base.id, nv_connector->base.name, ret);
1554         }
1555 #endif
1556
1557         if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1558                 ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
1559
1560                 if (ret == 0) {
1561                         pwr &= ~DP_SET_POWER_MASK;
1562                         pwr |=  DP_SET_POWER_D3;
1563                         drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);
1564                 }
1565         }
1566
1567         nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1568         nv50_audio_disable(encoder, nv_crtc);
1569         nvif_outp_release(&nv_encoder->outp);
1570         nv_encoder->crtc = NULL;
1571 }
1572
1573 static void
1574 nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1575 {
1576         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1577         struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1578         struct nv50_head_atom *asyh =
1579                 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1580         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1581         struct nv50_disp *disp = nv50_disp(encoder->dev);
1582         struct nvif_outp *outp = &nv_encoder->outp;
1583         struct drm_device *dev = encoder->dev;
1584         struct nouveau_drm *drm = nouveau_drm(dev);
1585         struct nouveau_connector *nv_connector;
1586 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1587         struct nouveau_backlight *backlight;
1588 #endif
1589         struct nvbios *bios = &drm->vbios;
1590         bool lvds_dual = false, lvds_8bpc = false, hda = false;
1591         u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
1592         u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
1593
1594         nv_connector = nv50_outp_get_new_connector(state, nv_encoder);
1595         nv_encoder->crtc = &nv_crtc->base;
1596
1597         if ((disp->disp->object.oclass == GT214_DISP ||
1598              disp->disp->object.oclass >= GF110_DISP) &&
1599             drm_detect_monitor_audio(nv_connector->edid))
1600                 hda = true;
1601
1602         switch (nv_encoder->dcb->type) {
1603         case DCB_OUTPUT_TMDS:
1604                 if (disp->disp->object.oclass == NV50_DISP ||
1605                     !drm_detect_hdmi_monitor(nv_connector->edid))
1606                         nvif_outp_acquire_tmds(outp, nv_crtc->index, false, 0, 0, 0, false);
1607                 else
1608                         nv50_hdmi_enable(encoder, nv_crtc, nv_connector, state, mode, hda);
1609
1610                 if (nv_encoder->outp.or.link & 1) {
1611                         proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1612                         /* Only enable dual-link if:
1613                          *  - Need to (i.e. rate > 165MHz)
1614                          *  - DCB says we can
1615                          *  - Not an HDMI monitor, since there's no dual-link
1616                          *    on HDMI.
1617                          */
1618                         if (mode->clock >= 165000 &&
1619                             nv_encoder->dcb->duallink_possible &&
1620                             !drm_detect_hdmi_monitor(nv_connector->edid))
1621                                 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1622                 } else {
1623                         proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1624                 }
1625                 break;
1626         case DCB_OUTPUT_LVDS:
1627                 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1628
1629                 if (bios->fp_no_ddc) {
1630                         lvds_dual = bios->fp.dual_link;
1631                         lvds_8bpc = bios->fp.if_is_24bit;
1632                 } else {
1633                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1634                                 if (((u8 *)nv_connector->edid)[121] == 2)
1635                                         lvds_dual = true;
1636                         } else
1637                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1638                                 lvds_dual = true;
1639                         }
1640
1641                         if (lvds_dual) {
1642                                 if (bios->fp.strapless_is_24bit & 2)
1643                                         lvds_8bpc = true;
1644                         } else {
1645                                 if (bios->fp.strapless_is_24bit & 1)
1646                                         lvds_8bpc = true;
1647                         }
1648
1649                         if (asyh->or.bpc == 8)
1650                                 lvds_8bpc = true;
1651                 }
1652
1653                 nvif_outp_acquire_lvds(&nv_encoder->outp, lvds_dual, lvds_8bpc);
1654                 break;
1655         case DCB_OUTPUT_DP:
1656                 nvif_outp_acquire_dp(&nv_encoder->outp, nv_encoder->dp.dpcd, 0, 0, hda, false);
1657                 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1658
1659                 if (nv_encoder->outp.or.link & 1)
1660                         proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1661                 else
1662                         proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1663
1664                 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
1665
1666 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1667                 backlight = nv_connector->backlight;
1668                 if (backlight && backlight->uses_dpcd)
1669                         drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info,
1670                                                  (u16)backlight->dev->props.brightness);
1671 #endif
1672
1673                 break;
1674         default:
1675                 BUG();
1676                 break;
1677         }
1678
1679         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1680 }
1681
1682 static const struct drm_encoder_helper_funcs
1683 nv50_sor_help = {
1684         .atomic_check = nv50_outp_atomic_check,
1685         .atomic_enable = nv50_sor_atomic_enable,
1686         .atomic_disable = nv50_sor_atomic_disable,
1687 };
1688
1689 static void
1690 nv50_sor_destroy(struct drm_encoder *encoder)
1691 {
1692         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1693
1694         nvif_outp_dtor(&nv_encoder->outp);
1695
1696         nv50_mstm_del(&nv_encoder->dp.mstm);
1697         drm_encoder_cleanup(encoder);
1698
1699         if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1700                 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
1701
1702         kfree(encoder);
1703 }
1704
1705 static const struct drm_encoder_funcs
1706 nv50_sor_func = {
1707         .destroy = nv50_sor_destroy,
1708 };
1709
1710 bool nv50_has_mst(struct nouveau_drm *drm)
1711 {
1712         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1713         u32 data;
1714         u8 ver, hdr, cnt, len;
1715
1716         data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1717         return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1718 }
1719
1720 static int
1721 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1722 {
1723         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1724         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1725         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1726         struct nouveau_encoder *nv_encoder;
1727         struct drm_encoder *encoder;
1728         struct nv50_disp *disp = nv50_disp(connector->dev);
1729         int type, ret;
1730
1731         switch (dcbe->type) {
1732         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1733         case DCB_OUTPUT_TMDS:
1734         case DCB_OUTPUT_DP:
1735         default:
1736                 type = DRM_MODE_ENCODER_TMDS;
1737                 break;
1738         }
1739
1740         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1741         if (!nv_encoder)
1742                 return -ENOMEM;
1743         nv_encoder->dcb = dcbe;
1744         nv_encoder->update = nv50_sor_update;
1745
1746         encoder = to_drm_encoder(nv_encoder);
1747         encoder->possible_crtcs = dcbe->heads;
1748         encoder->possible_clones = 0;
1749         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1750                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1751         drm_encoder_helper_add(encoder, &nv50_sor_help);
1752
1753         drm_connector_attach_encoder(connector, encoder);
1754
1755         disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1756         nv50_outp_dump_caps(drm, nv_encoder);
1757
1758         if (dcbe->type == DCB_OUTPUT_DP) {
1759                 struct nvkm_i2c_aux *aux =
1760                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1761
1762                 mutex_init(&nv_encoder->dp.hpd_irq_lock);
1763
1764                 if (aux) {
1765                         if (disp->disp->object.oclass < GF110_DISP) {
1766                                 /* HW has no support for address-only
1767                                  * transactions, so we're required to
1768                                  * use custom I2C-over-AUX code.
1769                                  */
1770                                 nv_encoder->i2c = &aux->i2c;
1771                         } else {
1772                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1773                         }
1774                         nv_encoder->aux = aux;
1775                 }
1776
1777                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1778                     nv50_has_mst(drm)) {
1779                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1780                                             16, nv_connector->base.base.id,
1781                                             &nv_encoder->dp.mstm);
1782                         if (ret)
1783                                 return ret;
1784                 }
1785         } else {
1786                 struct nvkm_i2c_bus *bus =
1787                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1788                 if (bus)
1789                         nv_encoder->i2c = &bus->i2c;
1790         }
1791
1792         return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp);
1793 }
1794
1795 /******************************************************************************
1796  * PIOR
1797  *****************************************************************************/
1798 static int
1799 nv50_pior_atomic_check(struct drm_encoder *encoder,
1800                        struct drm_crtc_state *crtc_state,
1801                        struct drm_connector_state *conn_state)
1802 {
1803         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1804         if (ret)
1805                 return ret;
1806         crtc_state->adjusted_mode.clock *= 2;
1807         return 0;
1808 }
1809
1810 static void
1811 nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1812 {
1813         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1814         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1815         const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
1816
1817         core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL);
1818         nv_encoder->crtc = NULL;
1819         nvif_outp_release(&nv_encoder->outp);
1820 }
1821
1822 static void
1823 nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1824 {
1825         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1826         struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1827         struct nv50_head_atom *asyh =
1828                 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1829         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1830         u32 ctrl = 0;
1831
1832         switch (nv_crtc->index) {
1833         case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
1834         case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
1835         default:
1836                 WARN_ON(1);
1837                 break;
1838         }
1839
1840         switch (asyh->or.bpc) {
1841         case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
1842         case  8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1843         case  6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1844         default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1845         }
1846
1847         switch (nv_encoder->dcb->type) {
1848         case DCB_OUTPUT_TMDS:
1849                 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1850                 nvif_outp_acquire_tmds(&nv_encoder->outp, false, false, 0, 0, 0, false);
1851                 break;
1852         case DCB_OUTPUT_DP:
1853                 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1854                 nvif_outp_acquire_dp(&nv_encoder->outp, nv_encoder->dp.dpcd, 0, 0, false, false);
1855                 break;
1856         default:
1857                 BUG();
1858                 break;
1859         }
1860
1861         core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
1862         nv_encoder->crtc = &nv_crtc->base;
1863 }
1864
1865 static const struct drm_encoder_helper_funcs
1866 nv50_pior_help = {
1867         .atomic_check = nv50_pior_atomic_check,
1868         .atomic_enable = nv50_pior_atomic_enable,
1869         .atomic_disable = nv50_pior_atomic_disable,
1870 };
1871
1872 static void
1873 nv50_pior_destroy(struct drm_encoder *encoder)
1874 {
1875         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1876
1877         nvif_outp_dtor(&nv_encoder->outp);
1878
1879         drm_encoder_cleanup(encoder);
1880         kfree(encoder);
1881 }
1882
1883 static const struct drm_encoder_funcs
1884 nv50_pior_func = {
1885         .destroy = nv50_pior_destroy,
1886 };
1887
1888 static int
1889 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1890 {
1891         struct drm_device *dev = connector->dev;
1892         struct nouveau_drm *drm = nouveau_drm(dev);
1893         struct nv50_disp *disp = nv50_disp(dev);
1894         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1895         struct nvkm_i2c_bus *bus = NULL;
1896         struct nvkm_i2c_aux *aux = NULL;
1897         struct i2c_adapter *ddc;
1898         struct nouveau_encoder *nv_encoder;
1899         struct drm_encoder *encoder;
1900         int type;
1901
1902         switch (dcbe->type) {
1903         case DCB_OUTPUT_TMDS:
1904                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1905                 ddc  = bus ? &bus->i2c : NULL;
1906                 type = DRM_MODE_ENCODER_TMDS;
1907                 break;
1908         case DCB_OUTPUT_DP:
1909                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1910                 ddc  = aux ? &aux->i2c : NULL;
1911                 type = DRM_MODE_ENCODER_TMDS;
1912                 break;
1913         default:
1914                 return -ENODEV;
1915         }
1916
1917         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1918         if (!nv_encoder)
1919                 return -ENOMEM;
1920         nv_encoder->dcb = dcbe;
1921         nv_encoder->i2c = ddc;
1922         nv_encoder->aux = aux;
1923
1924         encoder = to_drm_encoder(nv_encoder);
1925         encoder->possible_crtcs = dcbe->heads;
1926         encoder->possible_clones = 0;
1927         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1928                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1929         drm_encoder_helper_add(encoder, &nv50_pior_help);
1930
1931         drm_connector_attach_encoder(connector, encoder);
1932
1933         disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1934         nv50_outp_dump_caps(drm, nv_encoder);
1935
1936         return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp);
1937 }
1938
1939 /******************************************************************************
1940  * Atomic
1941  *****************************************************************************/
1942
1943 static void
1944 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1945 {
1946         struct drm_dp_mst_topology_mgr *mgr;
1947         struct drm_dp_mst_topology_state *mst_state;
1948         struct nouveau_drm *drm = nouveau_drm(state->dev);
1949         struct nv50_disp *disp = nv50_disp(drm->dev);
1950         struct nv50_core *core = disp->core;
1951         struct nv50_mstm *mstm;
1952         int i;
1953
1954         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1955
1956         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
1957                 mstm = nv50_mstm(mgr);
1958                 if (mstm->modified)
1959                         nv50_mstm_prepare(state, mst_state, mstm);
1960         }
1961
1962         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1963         core->func->update(core, interlock, true);
1964         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1965                                        disp->core->chan.base.device))
1966                 NV_ERROR(drm, "core notifier timeout\n");
1967
1968         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
1969                 mstm = nv50_mstm(mgr);
1970                 if (mstm->modified)
1971                         nv50_mstm_cleanup(state, mst_state, mstm);
1972         }
1973 }
1974
1975 static void
1976 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1977 {
1978         struct drm_plane_state *new_plane_state;
1979         struct drm_plane *plane;
1980         int i;
1981
1982         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1983                 struct nv50_wndw *wndw = nv50_wndw(plane);
1984                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1985                         if (wndw->func->update)
1986                                 wndw->func->update(wndw, interlock);
1987                 }
1988         }
1989 }
1990
1991 static void
1992 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1993 {
1994         struct drm_device *dev = state->dev;
1995         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1996         struct drm_crtc *crtc;
1997         struct drm_plane_state *new_plane_state;
1998         struct drm_plane *plane;
1999         struct nouveau_drm *drm = nouveau_drm(dev);
2000         struct nv50_disp *disp = nv50_disp(dev);
2001         struct nv50_atom *atom = nv50_atom(state);
2002         struct nv50_core *core = disp->core;
2003         struct nv50_outp_atom *outp, *outt;
2004         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
2005         int i;
2006         bool flushed = false;
2007
2008         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
2009         nv50_crc_atomic_stop_reporting(state);
2010         drm_atomic_helper_wait_for_fences(dev, state, false);
2011         drm_atomic_helper_wait_for_dependencies(state);
2012         drm_dp_mst_atomic_wait_for_dependencies(state);
2013         drm_atomic_helper_update_legacy_modeset_state(dev, state);
2014         drm_atomic_helper_calc_timestamping_constants(state);
2015
2016         if (atom->lock_core)
2017                 mutex_lock(&disp->mutex);
2018
2019         /* Disable head(s). */
2020         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2021                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2022                 struct nv50_head *head = nv50_head(crtc);
2023
2024                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
2025                           asyh->clr.mask, asyh->set.mask);
2026
2027                 if (old_crtc_state->active && !new_crtc_state->active) {
2028                         pm_runtime_put_noidle(dev->dev);
2029                         drm_crtc_vblank_off(crtc);
2030                 }
2031
2032                 if (asyh->clr.mask) {
2033                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
2034                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2035                 }
2036         }
2037
2038         /* Disable plane(s). */
2039         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2040                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2041                 struct nv50_wndw *wndw = nv50_wndw(plane);
2042
2043                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
2044                           asyw->clr.mask, asyw->set.mask);
2045                 if (!asyw->clr.mask)
2046                         continue;
2047
2048                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
2049         }
2050
2051         /* Disable output path(s). */
2052         list_for_each_entry(outp, &atom->outp, head) {
2053                 const struct drm_encoder_helper_funcs *help;
2054                 struct drm_encoder *encoder;
2055
2056                 encoder = outp->encoder;
2057                 help = encoder->helper_private;
2058
2059                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2060                           outp->clr.mask, outp->set.mask);
2061
2062                 if (outp->clr.mask) {
2063                         help->atomic_disable(encoder, state);
2064                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2065                         if (outp->flush_disable) {
2066                                 nv50_disp_atomic_commit_wndw(state, interlock);
2067                                 nv50_disp_atomic_commit_core(state, interlock);
2068                                 memset(interlock, 0x00, sizeof(interlock));
2069
2070                                 flushed = true;
2071                         }
2072                 }
2073         }
2074
2075         /* Flush disable. */
2076         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2077                 if (atom->flush_disable) {
2078                         nv50_disp_atomic_commit_wndw(state, interlock);
2079                         nv50_disp_atomic_commit_core(state, interlock);
2080                         memset(interlock, 0x00, sizeof(interlock));
2081
2082                         flushed = true;
2083                 }
2084         }
2085
2086         if (flushed)
2087                 nv50_crc_atomic_release_notifier_contexts(state);
2088         nv50_crc_atomic_init_notifier_contexts(state);
2089
2090         /* Update output path(s). */
2091         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2092                 const struct drm_encoder_helper_funcs *help;
2093                 struct drm_encoder *encoder;
2094
2095                 encoder = outp->encoder;
2096                 help = encoder->helper_private;
2097
2098                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2099                           outp->set.mask, outp->clr.mask);
2100
2101                 if (outp->set.mask) {
2102                         help->atomic_enable(encoder, state);
2103                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2104                 }
2105
2106                 list_del(&outp->head);
2107                 kfree(outp);
2108         }
2109
2110         /* Update head(s). */
2111         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2112                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2113                 struct nv50_head *head = nv50_head(crtc);
2114
2115                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2116                           asyh->set.mask, asyh->clr.mask);
2117
2118                 if (asyh->set.mask) {
2119                         nv50_head_flush_set(head, asyh);
2120                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2121                 }
2122
2123                 if (new_crtc_state->active) {
2124                         if (!old_crtc_state->active) {
2125                                 drm_crtc_vblank_on(crtc);
2126                                 pm_runtime_get_noresume(dev->dev);
2127                         }
2128                         if (new_crtc_state->event)
2129                                 drm_crtc_vblank_get(crtc);
2130                 }
2131         }
2132
2133         /* Update window->head assignment.
2134          *
2135          * This has to happen in an update that's not interlocked with
2136          * any window channels to avoid hitting HW error checks.
2137          *
2138          *TODO: Proper handling of window ownership (Turing apparently
2139          *      supports non-fixed mappings).
2140          */
2141         if (core->assign_windows) {
2142                 core->func->wndw.owner(core);
2143                 nv50_disp_atomic_commit_core(state, interlock);
2144                 core->assign_windows = false;
2145                 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2146         }
2147
2148         /* Finish updating head(s)...
2149          *
2150          * NVD is rather picky about both where window assignments can change,
2151          * *and* about certain core and window channel states matching.
2152          *
2153          * The EFI GOP driver on newer GPUs configures window channels with a
2154          * different output format to what we do, and the core channel update
2155          * in the assign_windows case above would result in a state mismatch.
2156          *
2157          * Delay some of the head update until after that point to workaround
2158          * the issue.  This only affects the initial modeset.
2159          *
2160          * TODO: handle this better when adding flexible window mapping
2161          */
2162         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2163                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2164                 struct nv50_head *head = nv50_head(crtc);
2165
2166                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2167                           asyh->set.mask, asyh->clr.mask);
2168
2169                 if (asyh->set.mask) {
2170                         nv50_head_flush_set_wndw(head, asyh);
2171                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2172                 }
2173         }
2174
2175         /* Update plane(s). */
2176         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2177                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2178                 struct nv50_wndw *wndw = nv50_wndw(plane);
2179
2180                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2181                           asyw->set.mask, asyw->clr.mask);
2182                 if ( !asyw->set.mask &&
2183                     (!asyw->clr.mask || atom->flush_disable))
2184                         continue;
2185
2186                 nv50_wndw_flush_set(wndw, interlock, asyw);
2187         }
2188
2189         /* Flush update. */
2190         nv50_disp_atomic_commit_wndw(state, interlock);
2191
2192         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2193                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2194                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
2195                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
2196                     !atom->state.legacy_cursor_update)
2197                         nv50_disp_atomic_commit_core(state, interlock);
2198                 else
2199                         disp->core->func->update(disp->core, interlock, false);
2200         }
2201
2202         if (atom->lock_core)
2203                 mutex_unlock(&disp->mutex);
2204
2205         /* Wait for HW to signal completion. */
2206         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2207                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2208                 struct nv50_wndw *wndw = nv50_wndw(plane);
2209                 int ret = nv50_wndw_wait_armed(wndw, asyw);
2210                 if (ret)
2211                         NV_ERROR(drm, "%s: timeout\n", plane->name);
2212         }
2213
2214         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2215                 if (new_crtc_state->event) {
2216                         unsigned long flags;
2217                         /* Get correct count/ts if racing with vblank irq */
2218                         if (new_crtc_state->active)
2219                                 drm_crtc_accurate_vblank_count(crtc);
2220                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
2221                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2222                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2223
2224                         new_crtc_state->event = NULL;
2225                         if (new_crtc_state->active)
2226                                 drm_crtc_vblank_put(crtc);
2227                 }
2228         }
2229
2230         nv50_crc_atomic_start_reporting(state);
2231         if (!flushed)
2232                 nv50_crc_atomic_release_notifier_contexts(state);
2233
2234         drm_atomic_helper_commit_hw_done(state);
2235         drm_atomic_helper_cleanup_planes(dev, state);
2236         drm_atomic_helper_commit_cleanup_done(state);
2237         drm_atomic_state_put(state);
2238
2239         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2240         pm_runtime_mark_last_busy(dev->dev);
2241         pm_runtime_put_autosuspend(dev->dev);
2242 }
2243
2244 static void
2245 nv50_disp_atomic_commit_work(struct work_struct *work)
2246 {
2247         struct drm_atomic_state *state =
2248                 container_of(work, typeof(*state), commit_work);
2249         nv50_disp_atomic_commit_tail(state);
2250 }
2251
2252 static int
2253 nv50_disp_atomic_commit(struct drm_device *dev,
2254                         struct drm_atomic_state *state, bool nonblock)
2255 {
2256         struct drm_plane_state *new_plane_state;
2257         struct drm_plane *plane;
2258         int ret, i;
2259
2260         ret = pm_runtime_get_sync(dev->dev);
2261         if (ret < 0 && ret != -EACCES) {
2262                 pm_runtime_put_autosuspend(dev->dev);
2263                 return ret;
2264         }
2265
2266         ret = drm_atomic_helper_setup_commit(state, nonblock);
2267         if (ret)
2268                 goto done;
2269
2270         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2271
2272         ret = drm_atomic_helper_prepare_planes(dev, state);
2273         if (ret)
2274                 goto done;
2275
2276         if (!nonblock) {
2277                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2278                 if (ret)
2279                         goto err_cleanup;
2280         }
2281
2282         ret = drm_atomic_helper_swap_state(state, true);
2283         if (ret)
2284                 goto err_cleanup;
2285
2286         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2287                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2288                 struct nv50_wndw *wndw = nv50_wndw(plane);
2289
2290                 if (asyw->set.image)
2291                         nv50_wndw_ntfy_enable(wndw, asyw);
2292         }
2293
2294         drm_atomic_state_get(state);
2295
2296         /*
2297          * Grab another RPM ref for the commit tail, which will release the
2298          * ref when it's finished
2299          */
2300         pm_runtime_get_noresume(dev->dev);
2301
2302         if (nonblock)
2303                 queue_work(system_unbound_wq, &state->commit_work);
2304         else
2305                 nv50_disp_atomic_commit_tail(state);
2306
2307 err_cleanup:
2308         if (ret)
2309                 drm_atomic_helper_cleanup_planes(dev, state);
2310 done:
2311         pm_runtime_put_autosuspend(dev->dev);
2312         return ret;
2313 }
2314
2315 static struct nv50_outp_atom *
2316 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2317 {
2318         struct nv50_outp_atom *outp;
2319
2320         list_for_each_entry(outp, &atom->outp, head) {
2321                 if (outp->encoder == encoder)
2322                         return outp;
2323         }
2324
2325         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2326         if (!outp)
2327                 return ERR_PTR(-ENOMEM);
2328
2329         list_add(&outp->head, &atom->outp);
2330         outp->encoder = encoder;
2331         return outp;
2332 }
2333
2334 static int
2335 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2336                                 struct drm_connector_state *old_connector_state)
2337 {
2338         struct drm_encoder *encoder = old_connector_state->best_encoder;
2339         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2340         struct drm_crtc *crtc;
2341         struct nv50_outp_atom *outp;
2342
2343         if (!(crtc = old_connector_state->crtc))
2344                 return 0;
2345
2346         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2347         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2348         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2349                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2350                 if (IS_ERR(outp))
2351                         return PTR_ERR(outp);
2352
2353                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2354                         outp->flush_disable = true;
2355                         atom->flush_disable = true;
2356                 }
2357                 outp->clr.ctrl = true;
2358                 atom->lock_core = true;
2359         }
2360
2361         return 0;
2362 }
2363
2364 static int
2365 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2366                                 struct drm_connector_state *connector_state)
2367 {
2368         struct drm_encoder *encoder = connector_state->best_encoder;
2369         struct drm_crtc_state *new_crtc_state;
2370         struct drm_crtc *crtc;
2371         struct nv50_outp_atom *outp;
2372
2373         if (!(crtc = connector_state->crtc))
2374                 return 0;
2375
2376         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2377         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2378                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2379                 if (IS_ERR(outp))
2380                         return PTR_ERR(outp);
2381
2382                 outp->set.ctrl = true;
2383                 atom->lock_core = true;
2384         }
2385
2386         return 0;
2387 }
2388
2389 static int
2390 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2391 {
2392         struct nv50_atom *atom = nv50_atom(state);
2393         struct nv50_core *core = nv50_disp(dev)->core;
2394         struct drm_connector_state *old_connector_state, *new_connector_state;
2395         struct drm_connector *connector;
2396         struct drm_crtc_state *new_crtc_state;
2397         struct drm_crtc *crtc;
2398         struct nv50_head *head;
2399         struct nv50_head_atom *asyh;
2400         int ret, i;
2401
2402         if (core->assign_windows && core->func->head->static_wndw_map) {
2403                 drm_for_each_crtc(crtc, dev) {
2404                         new_crtc_state = drm_atomic_get_crtc_state(state,
2405                                                                    crtc);
2406                         if (IS_ERR(new_crtc_state))
2407                                 return PTR_ERR(new_crtc_state);
2408
2409                         head = nv50_head(crtc);
2410                         asyh = nv50_head_atom(new_crtc_state);
2411                         core->func->head->static_wndw_map(head, asyh);
2412                 }
2413         }
2414
2415         /* We need to handle colour management on a per-plane basis. */
2416         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2417                 if (new_crtc_state->color_mgmt_changed) {
2418                         ret = drm_atomic_add_affected_planes(state, crtc);
2419                         if (ret)
2420                                 return ret;
2421                 }
2422         }
2423
2424         ret = drm_atomic_helper_check(dev, state);
2425         if (ret)
2426                 return ret;
2427
2428         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2429                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2430                 if (ret)
2431                         return ret;
2432
2433                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2434                 if (ret)
2435                         return ret;
2436         }
2437
2438         ret = drm_dp_mst_atomic_check(state);
2439         if (ret)
2440                 return ret;
2441
2442         nv50_crc_atomic_check_outp(atom);
2443
2444         return 0;
2445 }
2446
2447 static void
2448 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2449 {
2450         struct nv50_atom *atom = nv50_atom(state);
2451         struct nv50_outp_atom *outp, *outt;
2452
2453         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2454                 list_del(&outp->head);
2455                 kfree(outp);
2456         }
2457
2458         drm_atomic_state_default_clear(state);
2459 }
2460
2461 static void
2462 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2463 {
2464         struct nv50_atom *atom = nv50_atom(state);
2465         drm_atomic_state_default_release(&atom->state);
2466         kfree(atom);
2467 }
2468
2469 static struct drm_atomic_state *
2470 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2471 {
2472         struct nv50_atom *atom;
2473         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2474             drm_atomic_state_init(dev, &atom->state) < 0) {
2475                 kfree(atom);
2476                 return NULL;
2477         }
2478         INIT_LIST_HEAD(&atom->outp);
2479         return &atom->state;
2480 }
2481
2482 static const struct drm_mode_config_funcs
2483 nv50_disp_func = {
2484         .fb_create = nouveau_user_framebuffer_create,
2485         .output_poll_changed = drm_fb_helper_output_poll_changed,
2486         .atomic_check = nv50_disp_atomic_check,
2487         .atomic_commit = nv50_disp_atomic_commit,
2488         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2489         .atomic_state_clear = nv50_disp_atomic_state_clear,
2490         .atomic_state_free = nv50_disp_atomic_state_free,
2491 };
2492
2493 static const struct drm_mode_config_helper_funcs
2494 nv50_disp_helper_func = {
2495         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2496 };
2497
2498 /******************************************************************************
2499  * Init
2500  *****************************************************************************/
2501
2502 static void
2503 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend)
2504 {
2505         struct nouveau_drm *drm = nouveau_drm(dev);
2506         struct drm_encoder *encoder;
2507
2508         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2509                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
2510                         nv50_mstm_fini(nouveau_encoder(encoder));
2511         }
2512
2513         if (!runtime)
2514                 cancel_work_sync(&drm->hpd_work);
2515 }
2516
2517 static int
2518 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2519 {
2520         struct nv50_core *core = nv50_disp(dev)->core;
2521         struct drm_encoder *encoder;
2522
2523         if (resume || runtime)
2524                 core->func->init(core);
2525
2526         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2527                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2528                         struct nouveau_encoder *nv_encoder =
2529                                 nouveau_encoder(encoder);
2530                         nv50_mstm_init(nv_encoder, runtime);
2531                 }
2532         }
2533
2534         return 0;
2535 }
2536
2537 static void
2538 nv50_display_destroy(struct drm_device *dev)
2539 {
2540         struct nv50_disp *disp = nv50_disp(dev);
2541
2542         nv50_audio_component_fini(nouveau_drm(dev));
2543
2544         nvif_object_unmap(&disp->caps);
2545         nvif_object_dtor(&disp->caps);
2546         nv50_core_del(&disp->core);
2547
2548         nouveau_bo_unmap(disp->sync);
2549         if (disp->sync)
2550                 nouveau_bo_unpin(disp->sync);
2551         nouveau_bo_ref(NULL, &disp->sync);
2552
2553         nouveau_display(dev)->priv = NULL;
2554         kfree(disp);
2555 }
2556
2557 int
2558 nv50_display_create(struct drm_device *dev)
2559 {
2560         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2561         struct nouveau_drm *drm = nouveau_drm(dev);
2562         struct dcb_table *dcb = &drm->vbios.dcb;
2563         struct drm_connector *connector, *tmp;
2564         struct nv50_disp *disp;
2565         struct dcb_output *dcbe;
2566         int crtcs, ret, i;
2567         bool has_mst = nv50_has_mst(drm);
2568
2569         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2570         if (!disp)
2571                 return -ENOMEM;
2572
2573         mutex_init(&disp->mutex);
2574
2575         nouveau_display(dev)->priv = disp;
2576         nouveau_display(dev)->dtor = nv50_display_destroy;
2577         nouveau_display(dev)->init = nv50_display_init;
2578         nouveau_display(dev)->fini = nv50_display_fini;
2579         disp->disp = &nouveau_display(dev)->disp;
2580         dev->mode_config.funcs = &nv50_disp_func;
2581         dev->mode_config.helper_private = &nv50_disp_helper_func;
2582         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2583         dev->mode_config.normalize_zpos = true;
2584
2585         /* small shared memory area we use for notifiers and semaphores */
2586         ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
2587                              NOUVEAU_GEM_DOMAIN_VRAM,
2588                              0, 0x0000, NULL, NULL, &disp->sync);
2589         if (!ret) {
2590                 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true);
2591                 if (!ret) {
2592                         ret = nouveau_bo_map(disp->sync);
2593                         if (ret)
2594                                 nouveau_bo_unpin(disp->sync);
2595                 }
2596                 if (ret)
2597                         nouveau_bo_ref(NULL, &disp->sync);
2598         }
2599
2600         if (ret)
2601                 goto out;
2602
2603         /* allocate master evo channel */
2604         ret = nv50_core_new(drm, &disp->core);
2605         if (ret)
2606                 goto out;
2607
2608         disp->core->func->init(disp->core);
2609         if (disp->core->func->caps_init) {
2610                 ret = disp->core->func->caps_init(drm, disp);
2611                 if (ret)
2612                         goto out;
2613         }
2614
2615         /* Assign the correct format modifiers */
2616         if (disp->disp->object.oclass >= TU102_DISP)
2617                 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2618         else
2619         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
2620                 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2621         else
2622                 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2623
2624         /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later
2625          * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The
2626          * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to
2627          * small page allocations in prepare_fb(). When this is implemented, we should also force
2628          * large pages (128K) for ovly fbs in order to fix Kepler ovlys.
2629          * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using
2630          * large pages.
2631          */
2632         if (disp->disp->object.oclass >= GM107_DISP) {
2633                 dev->mode_config.cursor_width = 256;
2634                 dev->mode_config.cursor_height = 256;
2635         } else if (disp->disp->object.oclass >= GK104_DISP) {
2636                 dev->mode_config.cursor_width = 128;
2637                 dev->mode_config.cursor_height = 128;
2638         } else {
2639                 dev->mode_config.cursor_width = 64;
2640                 dev->mode_config.cursor_height = 64;
2641         }
2642
2643         /* create crtc objects to represent the hw heads */
2644         if (disp->disp->object.oclass >= GV100_DISP)
2645                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2646         else
2647         if (disp->disp->object.oclass >= GF110_DISP)
2648                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2649         else
2650                 crtcs = 0x3;
2651
2652         for (i = 0; i < fls(crtcs); i++) {
2653                 struct nv50_head *head;
2654
2655                 if (!(crtcs & (1 << i)))
2656                         continue;
2657
2658                 head = nv50_head_create(dev, i);
2659                 if (IS_ERR(head)) {
2660                         ret = PTR_ERR(head);
2661                         goto out;
2662                 }
2663
2664                 if (has_mst) {
2665                         head->msto = nv50_msto_new(dev, head, i);
2666                         if (IS_ERR(head->msto)) {
2667                                 ret = PTR_ERR(head->msto);
2668                                 head->msto = NULL;
2669                                 goto out;
2670                         }
2671
2672                         /*
2673                          * FIXME: This is a hack to workaround the following
2674                          * issues:
2675                          *
2676                          * https://gitlab.gnome.org/GNOME/mutter/issues/759
2677                          * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
2678                          *
2679                          * Once these issues are closed, this should be
2680                          * removed
2681                          */
2682                         head->msto->encoder.possible_crtcs = crtcs;
2683                 }
2684         }
2685
2686         /* create encoder/connector objects based on VBIOS DCB table */
2687         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2688                 connector = nouveau_connector_create(dev, dcbe);
2689                 if (IS_ERR(connector))
2690                         continue;
2691
2692                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2693                         switch (dcbe->type) {
2694                         case DCB_OUTPUT_TMDS:
2695                         case DCB_OUTPUT_LVDS:
2696                         case DCB_OUTPUT_DP:
2697                                 ret = nv50_sor_create(connector, dcbe);
2698                                 break;
2699                         case DCB_OUTPUT_ANALOG:
2700                                 ret = nv50_dac_create(connector, dcbe);
2701                                 break;
2702                         default:
2703                                 ret = -ENODEV;
2704                                 break;
2705                         }
2706                 } else {
2707                         ret = nv50_pior_create(connector, dcbe);
2708                 }
2709
2710                 if (ret) {
2711                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2712                                      dcbe->location, dcbe->type,
2713                                      ffs(dcbe->or) - 1, ret);
2714                         ret = 0;
2715                 }
2716         }
2717
2718         /* cull any connectors we created that don't have an encoder */
2719         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2720                 if (connector->possible_encoders)
2721                         continue;
2722
2723                 NV_WARN(drm, "%s has no encoders, removing\n",
2724                         connector->name);
2725                 connector->funcs->destroy(connector);
2726         }
2727
2728         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2729         dev->vblank_disable_immediate = true;
2730
2731         nv50_audio_component_init(drm);
2732
2733 out:
2734         if (ret)
2735                 nv50_display_destroy(dev);
2736         return ret;
2737 }
2738
2739 /******************************************************************************
2740  * Format modifiers
2741  *****************************************************************************/
2742
2743 /****************************************************************
2744  *            Log2(block height) ----------------------------+  *
2745  *            Page Kind ----------------------------------+  |  *
2746  *            Gob Height/Page Kind Generation ------+     |  |  *
2747  *                          Sector layout -------+  |     |  |  *
2748  *                          Compression ------+  |  |     |  |  */
2749 const u64 disp50xx_modifiers[] = { /*         |  |  |     |  |  */
2750         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2751         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2752         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2753         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2754         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2755         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2756         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2757         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2758         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2759         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2760         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2761         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2762         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2763         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2764         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2765         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2766         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2767         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2768         DRM_FORMAT_MOD_LINEAR,
2769         DRM_FORMAT_MOD_INVALID
2770 };
2771
2772 /****************************************************************
2773  *            Log2(block height) ----------------------------+  *
2774  *            Page Kind ----------------------------------+  |  *
2775  *            Gob Height/Page Kind Generation ------+     |  |  *
2776  *                          Sector layout -------+  |     |  |  *
2777  *                          Compression ------+  |  |     |  |  */
2778 const u64 disp90xx_modifiers[] = { /*         |  |  |     |  |  */
2779         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2780         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2781         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2782         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2783         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2784         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
2785         DRM_FORMAT_MOD_LINEAR,
2786         DRM_FORMAT_MOD_INVALID
2787 };