2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
25 #include <subdev/i2c.h>
27 struct anx9805_i2c_port {
28 struct nouveau_i2c_port base;
34 anx9805_train(struct nouveau_i2c_port *port, int link_nr, int link_bw, bool enh)
36 struct anx9805_i2c_port *chan = (void *)port;
37 struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent;
40 nv_wri2cr(mast, chan->addr, 0xa0, link_bw);
41 nv_wri2cr(mast, chan->addr, 0xa1, link_nr | (enh ? 0x80 : 0x00));
42 nv_wri2cr(mast, chan->addr, 0xa2, 0x01);
43 nv_wri2cr(mast, chan->addr, 0xa8, 0x01);
46 while ((tmp = nv_rdi2cr(mast, chan->addr, 0xa8)) & 0x01) {
49 nv_error(port, "link training timed out\n");
55 nv_error(port, "link training failed: 0x%02x\n", tmp);
63 anx9805_aux(struct nouveau_i2c_port *port, u8 type, u32 addr, u8 *data, u8 size)
65 struct anx9805_i2c_port *chan = (void *)port;
66 struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent;
67 int i, ret = -ETIMEDOUT;
70 tmp = nv_rdi2cr(mast, chan->ctrl, 0x07) & ~0x04;
71 nv_wri2cr(mast, chan->ctrl, 0x07, tmp | 0x04);
72 nv_wri2cr(mast, chan->ctrl, 0x07, tmp);
73 nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01);
75 nv_wri2cr(mast, chan->addr, 0xe4, 0x80);
76 for (i = 0; !(type & 1) && i < size; i++)
77 nv_wri2cr(mast, chan->addr, 0xf0 + i, data[i]);
78 nv_wri2cr(mast, chan->addr, 0xe5, ((size - 1) << 4) | type);
79 nv_wri2cr(mast, chan->addr, 0xe6, (addr & 0x000ff) >> 0);
80 nv_wri2cr(mast, chan->addr, 0xe7, (addr & 0x0ff00) >> 8);
81 nv_wri2cr(mast, chan->addr, 0xe8, (addr & 0xf0000) >> 16);
82 nv_wri2cr(mast, chan->addr, 0xe9, 0x01);
85 while ((tmp = nv_rdi2cr(mast, chan->addr, 0xe9)) & 0x01) {
91 if ((tmp = nv_rdi2cr(mast, chan->ctrl, 0xf7)) & 0x01) {
96 for (i = 0; (type & 1) && i < size; i++)
97 data[i] = nv_rdi2cr(mast, chan->addr, 0xf0 + i);
100 nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01);
104 static const struct nouveau_i2c_func
107 .lnk_ctl = anx9805_train,
111 anx9805_aux_chan_ctor(struct nouveau_object *parent,
112 struct nouveau_object *engine,
113 struct nouveau_oclass *oclass, void *data, u32 index,
114 struct nouveau_object **pobject)
116 struct nouveau_i2c_port *mast = (void *)parent;
117 struct anx9805_i2c_port *chan;
120 ret = nouveau_i2c_port_create(parent, engine, oclass, index,
121 &nouveau_i2c_aux_algo, &chan);
122 *pobject = nv_object(chan);
126 switch ((oclass->handle & 0xff00) >> 8) {
139 if (mast->adapter.algo == &i2c_bit_algo) {
140 struct i2c_algo_bit_data *algo = mast->adapter.algo_data;
141 algo->udelay = max(algo->udelay, 40);
144 chan->base.func = &anx9805_aux_func;
148 static struct nouveau_ofuncs
149 anx9805_aux_ofuncs = {
150 .ctor = anx9805_aux_chan_ctor,
151 .dtor = _nouveau_i2c_port_dtor,
152 .init = _nouveau_i2c_port_init,
153 .fini = _nouveau_i2c_port_fini,
157 anx9805_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
159 struct anx9805_i2c_port *port = adap->algo_data;
160 struct nouveau_i2c_port *mast = (void *)nv_object(port)->parent;
161 struct i2c_msg *msg = msgs;
162 int ret = -ETIMEDOUT;
164 u8 seg = 0x00, off = 0x00, tmp;
166 tmp = nv_rdi2cr(mast, port->ctrl, 0x07) & ~0x10;
167 nv_wri2cr(mast, port->ctrl, 0x07, tmp | 0x10);
168 nv_wri2cr(mast, port->ctrl, 0x07, tmp);
169 nv_wri2cr(mast, port->addr, 0x43, 0x05);
173 if ( (msg->flags & I2C_M_RD) && msg->addr == 0x50) {
174 nv_wri2cr(mast, port->addr, 0x40, msg->addr << 1);
175 nv_wri2cr(mast, port->addr, 0x41, seg);
176 nv_wri2cr(mast, port->addr, 0x42, off);
177 nv_wri2cr(mast, port->addr, 0x44, msg->len);
178 nv_wri2cr(mast, port->addr, 0x45, 0x00);
179 nv_wri2cr(mast, port->addr, 0x43, 0x01);
180 for (i = 0; i < msg->len; i++) {
182 while (nv_rdi2cr(mast, port->addr, 0x46) & 0x10) {
187 msg->buf[i] = nv_rdi2cr(mast, port->addr, 0x47);
190 if (!(msg->flags & I2C_M_RD)) {
191 if (msg->addr == 0x50 && msg->len == 0x01) {
194 if (msg->addr == 0x30 && msg->len == 0x01) {
206 nv_wri2cr(mast, port->addr, 0x43, 0x00);
211 anx9805_func(struct i2c_adapter *adap)
213 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
216 static const struct i2c_algorithm
218 .master_xfer = anx9805_xfer,
219 .functionality = anx9805_func
222 static const struct nouveau_i2c_func
227 anx9805_ddc_port_ctor(struct nouveau_object *parent,
228 struct nouveau_object *engine,
229 struct nouveau_oclass *oclass, void *data, u32 index,
230 struct nouveau_object **pobject)
232 struct nouveau_i2c_port *mast = (void *)parent;
233 struct anx9805_i2c_port *port;
236 ret = nouveau_i2c_port_create(parent, engine, oclass, index,
237 &anx9805_i2c_algo, &port);
238 *pobject = nv_object(port);
242 switch ((oclass->handle & 0xff00) >> 8) {
255 if (mast->adapter.algo == &i2c_bit_algo) {
256 struct i2c_algo_bit_data *algo = mast->adapter.algo_data;
257 algo->udelay = max(algo->udelay, 40);
260 port->base.func = &anx9805_i2c_func;
264 static struct nouveau_ofuncs
265 anx9805_ddc_ofuncs = {
266 .ctor = anx9805_ddc_port_ctor,
267 .dtor = _nouveau_i2c_port_dtor,
268 .init = _nouveau_i2c_port_init,
269 .fini = _nouveau_i2c_port_fini,
272 struct nouveau_oclass
273 nouveau_anx9805_sclass[] = {
274 { .handle = NV_I2C_TYPE_EXTDDC(0x0d), .ofuncs = &anx9805_ddc_ofuncs },
275 { .handle = NV_I2C_TYPE_EXTAUX(0x0d), .ofuncs = &anx9805_aux_ofuncs },
276 { .handle = NV_I2C_TYPE_EXTDDC(0x0e), .ofuncs = &anx9805_ddc_ofuncs },
277 { .handle = NV_I2C_TYPE_EXTAUX(0x0e), .ofuncs = &anx9805_aux_ofuncs },