2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include <subdev/vga.h>
26 #include <subdev/bios.h>
27 #include <subdev/bios/bit.h>
28 #include <subdev/bios/bmp.h>
29 #include <subdev/bios/pll.h>
36 static struct pll_mapping
37 nv04_pll_mapping[] = {
38 { PLL_CORE , 0x680500 },
39 { PLL_MEMORY, 0x680504 },
40 { PLL_VPLL0 , 0x680508 },
41 { PLL_VPLL1 , 0x680520 },
45 static struct pll_mapping
46 nv40_pll_mapping[] = {
47 { PLL_CORE , 0x004000 },
48 { PLL_MEMORY, 0x004020 },
49 { PLL_VPLL0 , 0x680508 },
50 { PLL_VPLL1 , 0x680520 },
54 static struct pll_mapping
55 nv50_pll_mapping[] = {
56 { PLL_CORE , 0x004028 },
57 { PLL_SHADER, 0x004020 },
58 { PLL_UNK03 , 0x004000 },
59 { PLL_MEMORY, 0x004008 },
60 { PLL_UNK40 , 0x00e810 },
61 { PLL_UNK41 , 0x00e818 },
62 { PLL_UNK42 , 0x00e824 },
63 { PLL_VPLL0 , 0x614100 },
64 { PLL_VPLL1 , 0x614900 },
68 static struct pll_mapping
69 nv84_pll_mapping[] = {
70 { PLL_CORE , 0x004028 },
71 { PLL_SHADER, 0x004020 },
72 { PLL_MEMORY, 0x004008 },
73 { PLL_VDEC , 0x004030 },
74 { PLL_UNK41 , 0x00e818 },
75 { PLL_VPLL0 , 0x614100 },
76 { PLL_VPLL1 , 0x614900 },
81 pll_limits_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
83 struct bit_entry bit_C;
85 if (!bit_entry(bios, 'C', &bit_C) && bit_C.length >= 10) {
86 u16 data = nv_ro16(bios, bit_C.offset + 8);
88 *ver = nv_ro08(bios, data + 0);
89 *hdr = nv_ro08(bios, data + 1);
90 *len = nv_ro08(bios, data + 2);
91 *cnt = nv_ro08(bios, data + 3);
96 if (bmp_version(bios) >= 0x0524) {
97 u16 data = nv_ro16(bios, bios->bmp_offset + 142);
99 *ver = nv_ro08(bios, data + 0);
111 static struct pll_mapping *
112 pll_map(struct nouveau_bios *bios)
114 switch (nv_device(bios)->card_type) {
119 return nv04_pll_mapping;
122 return nv40_pll_mapping;
124 if (nv_device(bios)->chipset == 0x50)
125 return nv50_pll_mapping;
127 if (nv_device(bios)->chipset < 0xa3 ||
128 nv_device(bios)->chipset == 0xaa ||
129 nv_device(bios)->chipset == 0xac)
130 return nv84_pll_mapping;
137 pll_map_reg(struct nouveau_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
139 struct pll_mapping *map;
143 data = pll_limits_table(bios, ver, &hdr, &cnt, len);
144 if (data && *ver >= 0x30) {
147 if (nv_ro32(bios, data + 3) == reg) {
148 *type = nv_ro08(bios, data + 0);
158 if (map->reg == reg && *ver >= 0x20) {
159 u16 addr = (data += hdr);
162 if (nv_ro32(bios, data) == map->reg)
168 if (map->reg == reg) {
179 pll_map_type(struct nouveau_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
181 struct pll_mapping *map;
185 data = pll_limits_table(bios, ver, &hdr, &cnt, len);
186 if (data && *ver >= 0x30) {
189 if (nv_ro08(bios, data + 0) == type) {
190 *reg = nv_ro32(bios, data + 3);
200 if (map->type == type && *ver >= 0x20) {
201 u16 addr = (data += hdr);
204 if (nv_ro32(bios, data) == map->reg)
210 if (map->type == type) {
221 nvbios_pll_parse(struct nouveau_bios *bios, u32 type, struct nvbios_pll *info)
227 if (type > PLL_MAX) {
229 data = pll_map_reg(bios, reg, &type, &ver, &len);
231 data = pll_map_type(bios, type, ®, &ver, &len);
237 memset(info, 0, sizeof(*info));
246 info->vco1.min_freq = nv_ro32(bios, data + 0);
247 info->vco1.max_freq = nv_ro32(bios, data + 4);
248 info->vco2.min_freq = nv_ro32(bios, data + 8);
249 info->vco2.max_freq = nv_ro32(bios, data + 12);
250 info->vco1.min_inputfreq = nv_ro32(bios, data + 16);
251 info->vco2.min_inputfreq = nv_ro32(bios, data + 20);
252 info->vco1.max_inputfreq = INT_MAX;
253 info->vco2.max_inputfreq = INT_MAX;
256 info->max_p_usable = 0x6;
258 /* these values taken from nv30/31/36 */
259 switch (bios->version.chip) {
261 info->vco1.min_n = 0x5;
264 info->vco1.min_n = 0x1;
267 info->vco1.max_n = 0xff;
268 info->vco1.min_m = 0x1;
269 info->vco1.max_m = 0xd;
272 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
273 * table version (apart from nv35)), N2 is compared to
274 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
277 info->vco2.min_n = 0x4;
278 switch (bios->version.chip) {
281 info->vco2.max_n = 0x1f;
284 info->vco2.max_n = 0x28;
287 info->vco2.min_m = 0x1;
288 info->vco2.max_m = 0x4;
292 info->vco1.min_freq = nv_ro16(bios, data + 4) * 1000;
293 info->vco1.max_freq = nv_ro16(bios, data + 6) * 1000;
294 info->vco2.min_freq = nv_ro16(bios, data + 8) * 1000;
295 info->vco2.max_freq = nv_ro16(bios, data + 10) * 1000;
296 info->vco1.min_inputfreq = nv_ro16(bios, data + 12) * 1000;
297 info->vco2.min_inputfreq = nv_ro16(bios, data + 14) * 1000;
298 info->vco1.max_inputfreq = nv_ro16(bios, data + 16) * 1000;
299 info->vco2.max_inputfreq = nv_ro16(bios, data + 18) * 1000;
300 info->vco1.min_n = nv_ro08(bios, data + 20);
301 info->vco1.max_n = nv_ro08(bios, data + 21);
302 info->vco1.min_m = nv_ro08(bios, data + 22);
303 info->vco1.max_m = nv_ro08(bios, data + 23);
304 info->vco2.min_n = nv_ro08(bios, data + 24);
305 info->vco2.max_n = nv_ro08(bios, data + 25);
306 info->vco2.min_m = nv_ro08(bios, data + 26);
307 info->vco2.max_m = nv_ro08(bios, data + 27);
309 info->max_p = nv_ro08(bios, data + 29);
310 info->max_p_usable = info->max_p;
311 if (bios->version.chip < 0x60)
312 info->max_p_usable = 0x6;
313 info->bias_p = nv_ro08(bios, data + 30);
316 info->refclk = nv_ro32(bios, data + 31);
319 data = nv_ro16(bios, data + 1);
321 info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000;
322 info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000;
323 info->vco2.min_freq = nv_ro16(bios, data + 4) * 1000;
324 info->vco2.max_freq = nv_ro16(bios, data + 6) * 1000;
325 info->vco1.min_inputfreq = nv_ro16(bios, data + 8) * 1000;
326 info->vco2.min_inputfreq = nv_ro16(bios, data + 10) * 1000;
327 info->vco1.max_inputfreq = nv_ro16(bios, data + 12) * 1000;
328 info->vco2.max_inputfreq = nv_ro16(bios, data + 14) * 1000;
329 info->vco1.min_n = nv_ro08(bios, data + 16);
330 info->vco1.max_n = nv_ro08(bios, data + 17);
331 info->vco1.min_m = nv_ro08(bios, data + 18);
332 info->vco1.max_m = nv_ro08(bios, data + 19);
333 info->vco2.min_n = nv_ro08(bios, data + 20);
334 info->vco2.max_n = nv_ro08(bios, data + 21);
335 info->vco2.min_m = nv_ro08(bios, data + 22);
336 info->vco2.max_m = nv_ro08(bios, data + 23);
337 info->max_p_usable = info->max_p = nv_ro08(bios, data + 25);
338 info->bias_p = nv_ro08(bios, data + 27);
339 info->refclk = nv_ro32(bios, data + 28);
342 info->refclk = nv_ro16(bios, data + 9) * 1000;
343 data = nv_ro16(bios, data + 1);
345 info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000;
346 info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000;
347 info->vco1.min_inputfreq = nv_ro16(bios, data + 4) * 1000;
348 info->vco1.max_inputfreq = nv_ro16(bios, data + 6) * 1000;
349 info->vco1.min_m = nv_ro08(bios, data + 8);
350 info->vco1.max_m = nv_ro08(bios, data + 9);
351 info->vco1.min_n = nv_ro08(bios, data + 10);
352 info->vco1.max_n = nv_ro08(bios, data + 11);
353 info->min_p = nv_ro08(bios, data + 12);
354 info->max_p = nv_ro08(bios, data + 13);
357 nv_error(bios, "unknown pll limits version 0x%02x\n", ver);
362 info->refclk = nv_device(bios)->crystal;
363 if (bios->version.chip == 0x51) {
364 u32 sel_clk = nv_rd32(bios, 0x680524);
365 if ((info->reg == 0x680508 && sel_clk & 0x20) ||
366 (info->reg == 0x680520 && sel_clk & 0x80)) {
367 if (nv_rdvgac(bios, 0, 0x27) < 0xa3)
368 info->refclk = 200000;
370 info->refclk = 25000;
376 * By now any valid limit table ought to have set a max frequency for
377 * vco1, so if it's zero it's either a pre limit table bios, or one
378 * with an empty limit table (seen on nv18)
380 if (!info->vco1.max_freq) {
381 info->vco1.max_freq = nv_ro32(bios, bios->bmp_offset + 67);
382 info->vco1.min_freq = nv_ro32(bios, bios->bmp_offset + 71);
383 if (bmp_version(bios) < 0x0506) {
384 info->vco1.max_freq = 256000;
385 info->vco1.min_freq = 128000;
388 info->vco1.min_inputfreq = 0;
389 info->vco1.max_inputfreq = INT_MAX;
390 info->vco1.min_n = 0x1;
391 info->vco1.max_n = 0xff;
392 info->vco1.min_m = 0x1;
394 if (nv_device(bios)->crystal == 13500) {
395 /* nv05 does this, nv11 doesn't, nv10 unknown */
396 if (bios->version.chip < 0x11)
397 info->vco1.min_m = 0x7;
398 info->vco1.max_m = 0xd;
400 if (bios->version.chip < 0x11)
401 info->vco1.min_m = 0x8;
402 info->vco1.max_m = 0xe;
405 if (bios->version.chip < 0x17 ||
406 bios->version.chip == 0x1a ||
407 bios->version.chip == 0x20)
411 info->max_p_usable = info->max_p;