drivers/gpu/drm/nouveau/core/engine/graph/nv50.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include <engine/fifo.h>
  31 #include <core/ramht.h>
  32 #include "nouveau_dma.h"
  33 #include "nv50_evo.h"
  34
  35 struct nv50_graph_engine {
  36         struct nouveau_exec_engine base;
  37         u32 ctxprog[512];
  38         u32 ctxprog_size;
  39         u32 grctx_size;
  40 };
  41
  42 static int
  43 nv50_graph_init(struct drm_device *dev, int engine)
  44 {
  45         struct drm_nouveau_private *dev_priv = dev->dev_private;
  46         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
  47         u32 units = nv_rd32(dev, 0x001540);
  48         int i;
  49
  50         NV_DEBUG(dev, "\n");
  51
  52         /* master reset */
  53         nv_mask(dev, 0x000200, 0x00201000, 0x00000000);
  54         nv_mask(dev, 0x000200, 0x00201000, 0x00201000);
  55         nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
  56
  57         /* reset/enable traps and interrupts */
  58         nv_wr32(dev, 0x400804, 0xc0000000);
  59         nv_wr32(dev, 0x406800, 0xc0000000);
  60         nv_wr32(dev, 0x400c04, 0xc0000000);
  61         nv_wr32(dev, 0x401800, 0xc0000000);
  62         nv_wr32(dev, 0x405018, 0xc0000000);
  63         nv_wr32(dev, 0x402000, 0xc0000000);
  64         for (i = 0; i < 16; i++) {
  65                 if (!(units & (1 << i)))
  66                         continue;
  67
  68                 if (dev_priv->chipset < 0xa0) {
  69                         nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
  70                         nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
  71                         nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
  72                 } else {
  73                         nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
  74                         nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
  75                         nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
  76                 }
  77         }
  78
  79         nv_wr32(dev, 0x400108, 0xffffffff);
  80         nv_wr32(dev, 0x400138, 0xffffffff);
  81         nv_wr32(dev, 0x400100, 0xffffffff);
  82         nv_wr32(dev, 0x40013c, 0xffffffff);
  83         nv_wr32(dev, 0x400500, 0x00010001);
  84
  85         /* upload context program, initialise ctxctl defaults */
  86         nv_wr32(dev, 0x400324, 0x00000000);
  87         for (i = 0; i < pgraph->ctxprog_size; i++)
  88                 nv_wr32(dev, 0x400328, pgraph->ctxprog[i]);
  89         nv_wr32(dev, 0x400824, 0x00000000);
  90         nv_wr32(dev, 0x400828, 0x00000000);
  91         nv_wr32(dev, 0x40082c, 0x00000000);
  92         nv_wr32(dev, 0x400830, 0x00000000);
  93         nv_wr32(dev, 0x400724, 0x00000000);
  94         nv_wr32(dev, 0x40032c, 0x00000000);
  95         nv_wr32(dev, 0x400320, 4);      /* CTXCTL_CMD = NEWCTXDMA */
  96
  97         /* some unknown zcull magic */
  98         switch (dev_priv->chipset & 0xf0) {
  99         case 0x50:
 100         case 0x80:
 101         case 0x90:
 102                 nv_wr32(dev, 0x402ca8, 0x00000800);
 103                 break;
 104         case 0xa0:
 105         default:
 106                 nv_wr32(dev, 0x402cc0, 0x00000000);
 107                 if (dev_priv->chipset == 0xa0 ||
 108                     dev_priv->chipset == 0xaa ||
 109                     dev_priv->chipset == 0xac) {
 110                         nv_wr32(dev, 0x402ca8, 0x00000802);
 111                 } else {
 112                         nv_wr32(dev, 0x402cc0, 0x00000000);
 113                         nv_wr32(dev, 0x402ca8, 0x00000002);
 114                 }
 115
 116                 break;
 117         }
 118
 119         /* zero out zcull regions */
 120         for (i = 0; i < 8; i++) {
 121                 nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000);
 122                 nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000);
 123                 nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000);
 124                 nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000);
 125         }
 126
 127         return 0;
 128 }
 129
 130 static int
 131 nv50_graph_fini(struct drm_device *dev, int engine, bool suspend)
 132 {
 133         nv_wr32(dev, 0x40013c, 0x00000000);
 134         return 0;
 135 }
 136
 137 static int
 138 nv50_graph_context_new(struct nouveau_channel *chan, int engine)
 139 {
 140         struct drm_device *dev = chan->dev;
 141         struct drm_nouveau_private *dev_priv = dev->dev_private;
 142         struct nouveau_gpuobj *ramin = chan->ramin;
 143         struct nouveau_gpuobj *grctx = NULL;
 144         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
 145         int hdr, ret;
 146
 147         NV_DEBUG(dev, "ch%d\n", chan->id);
 148
 149         ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 0,
 150                                  NVOBJ_FLAG_ZERO_ALLOC |
 151                                  NVOBJ_FLAG_ZERO_FREE, &grctx);
 152         if (ret)
 153                 return ret;
 154
 155         hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 156         nv_wo32(ramin, hdr + 0x00, 0x00190002);
 157         nv_wo32(ramin, hdr + 0x04, grctx->addr + grctx->size - 1);
 158         nv_wo32(ramin, hdr + 0x08, grctx->addr);
 159         nv_wo32(ramin, hdr + 0x0c, 0);
 160         nv_wo32(ramin, hdr + 0x10, 0);
 161         nv_wo32(ramin, hdr + 0x14, 0x00010000);
 162
 163         nv50_grctx_fill(dev, grctx);
 164         nv_wo32(grctx, 0x00000, chan->ramin->addr >> 12);
 165
 166         nvimem_flush(dev);
 167
 168         nvvm_engref(chan->vm, engine, 1);
 169         chan->engctx[NVOBJ_ENGINE_GR] = grctx;
 170         return 0;
 171 }
 172
 173 static void
 174 nv50_graph_context_del(struct nouveau_channel *chan, int engine)
 175 {
 176         struct nouveau_gpuobj *grctx = chan->engctx[engine];
 177         struct drm_device *dev = chan->dev;
 178         struct drm_nouveau_private *dev_priv = dev->dev_private;
 179         int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 180
 181         for (i = hdr; i < hdr + 24; i += 4)
 182                 nv_wo32(chan->ramin, i, 0);
 183         nvimem_flush(dev);
 184
 185         nvvm_engref(chan->vm, engine, -1);
 186         nouveau_gpuobj_ref(NULL, &grctx);
 187         chan->engctx[engine] = NULL;
 188 }
 189
 190 static int
 191 nv50_graph_object_new(struct nouveau_channel *chan, int engine,
 192                       u32 handle, u16 class)
 193 {
 194         struct drm_device *dev = chan->dev;
 195         struct nouveau_gpuobj *obj = NULL;
 196         int ret;
 197
 198         ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
 199         if (ret)
 200                 return ret;
 201         obj->engine = 1;
 202         obj->class  = class;
 203
 204         nv_wo32(obj, 0x00, class);
 205         nv_wo32(obj, 0x04, 0x00000000);
 206         nv_wo32(obj, 0x08, 0x00000000);
 207         nv_wo32(obj, 0x0c, 0x00000000);
 208         nvimem_flush(dev);
 209
 210         ret = nouveau_ramht_insert(chan, handle, obj);
 211         nouveau_gpuobj_ref(NULL, &obj);
 212         return ret;
 213 }
 214
 215 static void
 216 nv50_graph_tlb_flush(struct drm_device *dev, int engine)
 217 {
 218         nv50_vm_flush_engine(dev, 0);
 219 }
 220
 221 static void
 222 nv84_graph_tlb_flush(struct drm_device *dev, int engine)
 223 {
 224         struct drm_nouveau_private *dev_priv = dev->dev_private;
 225         bool idle, timeout = false;
 226         unsigned long flags;
 227         u64 start;
 228         u32 tmp;
 229
 230         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 231         nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
 232
 233         start = nv_timer_read(dev);
 234         do {
 235                 idle = true;
 236
 237                 for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
 238                         if ((tmp & 7) == 1)
 239                                 idle = false;
 240                 }
 241
 242                 for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
 243                         if ((tmp & 7) == 1)
 244                                 idle = false;
 245                 }
 246
 247                 for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
 248                         if ((tmp & 7) == 1)
 249                                 idle = false;
 250                 }
 251         } while (!idle && !(timeout = nv_timer_read(dev) - start > 2000000000));
 252
 253         if (timeout) {
 254                 NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
 255                               "0x%08x 0x%08x 0x%08x 0x%08x\n",
 256                          nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
 257                          nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
 258         }
 259
 260         nv50_vm_flush_engine(dev, 0);
 261
 262         nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
 263         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 264 }
 265
 266 static struct nouveau_enum nv50_mp_exec_error_names[] = {
 267         { 3, "STACK_UNDERFLOW", NULL },
 268         { 4, "QUADON_ACTIVE", NULL },
 269         { 8, "TIMEOUT", NULL },
 270         { 0x10, "INVALID_OPCODE", NULL },
 271         { 0x40, "BREAKPOINT", NULL },
 272         {}
 273 };
 274
 275 static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
 276         { 0x00000001, "NOTIFY" },
 277         { 0x00000002, "IN" },
 278         { 0x00000004, "OUT" },
 279         {}
 280 };
 281
 282 static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
 283         { 0x00000001, "FAULT" },
 284         {}
 285 };
 286
 287 static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
 288         { 0x00000001, "FAULT" },
 289         {}
 290 };
 291
 292 static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
 293         { 0x00000001, "FAULT" },
 294         {}
 295 };
 296
 297 /* There must be a *lot* of these. Will take some time to gather them up. */
 298 struct nouveau_enum nv50_data_error_names[] = {
 299         { 0x00000003, "INVALID_OPERATION", NULL },
 300         { 0x00000004, "INVALID_VALUE", NULL },
 301         { 0x00000005, "INVALID_ENUM", NULL },
 302         { 0x00000008, "INVALID_OBJECT", NULL },
 303         { 0x00000009, "READ_ONLY_OBJECT", NULL },
 304         { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
 305         { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
 306         { 0x0000000c, "INVALID_BITFIELD", NULL },
 307         { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
 308         { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
 309         { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
 310         { 0x00000010, "RT_DOUBLE_BIND", NULL },
 311         { 0x00000011, "RT_TYPES_MISMATCH", NULL },
 312         { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
 313         { 0x00000015, "FP_TOO_FEW_REGS", NULL },
 314         { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
 315         { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
 316         { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
 317         { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
 318         { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
 319         { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
 320         { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
 321         { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
 322         { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
 323         { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
 324         { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
 325         { 0x00000024, "VP_ZERO_INPUTS", NULL },
 326         { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
 327         { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
 328         { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
 329         { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
 330         { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
 331         { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
 332         { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
 333         { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
 334         { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
 335         { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
 336         { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
 337         { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
 338         { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
 339         { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
 340         { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
 341         {}
 342 };
 343
 344 static struct nouveau_bitfield nv50_graph_intr[] = {
 345         { 0x00000001, "NOTIFY" },
 346         { 0x00000002, "COMPUTE_QUERY" },
 347         { 0x00000010, "ILLEGAL_MTHD" },
 348         { 0x00000020, "ILLEGAL_CLASS" },
 349         { 0x00000040, "DOUBLE_NOTIFY" },
 350         { 0x00001000, "CONTEXT_SWITCH" },
 351         { 0x00010000, "BUFFER_NOTIFY" },
 352         { 0x00100000, "DATA_ERROR" },
 353         { 0x00200000, "TRAP" },
 354         { 0x01000000, "SINGLE_STEP" },
 355         {}
 356 };
 357
 358 static void
 359 nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
 360 {
 361         struct drm_nouveau_private *dev_priv = dev->dev_private;
 362         uint32_t units = nv_rd32(dev, 0x1540);
 363         uint32_t addr, mp10, status, pc, oplow, ophigh;
 364         int i;
 365         int mps = 0;
 366         for (i = 0; i < 4; i++) {
 367                 if (!(units & 1 << (i+24)))
 368                         continue;
 369                 if (dev_priv->chipset < 0xa0)
 370                         addr = 0x408200 + (tpid << 12) + (i << 7);
 371                 else
 372                         addr = 0x408100 + (tpid << 11) + (i << 7);
 373                 mp10 = nv_rd32(dev, addr + 0x10);
 374                 status = nv_rd32(dev, addr + 0x14);
 375                 if (!status)
 376                         continue;
 377                 if (display) {
 378                         nv_rd32(dev, addr + 0x20);
 379                         pc = nv_rd32(dev, addr + 0x24);
 380                         oplow = nv_rd32(dev, addr + 0x70);
 381                         ophigh = nv_rd32(dev, addr + 0x74);
 382                         NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
 383                                         "TP %d MP %d: ", tpid, i);
 384                         nouveau_enum_print(nv50_mp_exec_error_names, status);
 385                         printk(" at %06x warp %d, opcode %08x %08x\n",
 386                                         pc&0xffffff, pc >> 24,
 387                                         oplow, ophigh);
 388                 }
 389                 nv_wr32(dev, addr + 0x10, mp10);
 390                 nv_wr32(dev, addr + 0x14, 0);
 391                 mps++;
 392         }
 393         if (!mps && display)
 394                 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
 395                                 "No MPs claiming errors?\n", tpid);
 396 }
 397
 398 static void
 399 nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
 400                 uint32_t ustatus_new, int display, const char *name)
 401 {
 402         struct drm_nouveau_private *dev_priv = dev->dev_private;
 403         int tps = 0;
 404         uint32_t units = nv_rd32(dev, 0x1540);
 405         int i, r;
 406         uint32_t ustatus_addr, ustatus;
 407         for (i = 0; i < 16; i++) {
 408                 if (!(units & (1 << i)))
 409                         continue;
 410                 if (dev_priv->chipset < 0xa0)
 411                         ustatus_addr = ustatus_old + (i << 12);
 412                 else
 413                         ustatus_addr = ustatus_new + (i << 11);
 414                 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
 415                 if (!ustatus)
 416                         continue;
 417                 tps++;
 418                 switch (type) {
 419                 case 6: /* texture error... unknown for now */
 420                         if (display) {
 421                                 NV_ERROR(dev, "magic set %d:\n", i);
 422                                 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
 423                                         NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
 424                                                 nv_rd32(dev, r));
 425                         }
 426                         break;
 427                 case 7: /* MP error */
 428                         if (ustatus & 0x04030000) {
 429                                 nv50_pgraph_mp_trap(dev, i, display);
 430                                 ustatus &= ~0x04030000;
 431                         }
 432                         break;
 433                 case 8: /* TPDMA error */
 434                         {
 435                         uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
 436                         uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
 437                         uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
 438                         uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
 439                         uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
 440                         uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
 441                         uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
 442                         /* 2d engine destination */
 443                         if (ustatus & 0x00000010) {
 444                                 if (display) {
 445                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
 446                                                         i, e14, e10);
 447                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 448                                                         i, e0c, e18, e1c, e20, e24);
 449                                 }
 450                                 ustatus &= ~0x00000010;
 451                         }
 452                         /* Render target */
 453                         if (ustatus & 0x00000040) {
 454                                 if (display) {
 455                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
 456                                                         i, e14, e10);
 457                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 458                                                         i, e0c, e18, e1c, e20, e24);
 459                                 }
 460                                 ustatus &= ~0x00000040;
 461                         }
 462                         /* CUDA memory: l[], g[] or stack. */
 463                         if (ustatus & 0x00000080) {
 464                                 if (display) {
 465                                         if (e18 & 0x80000000) {
 466                                                 /* g[] read fault? */
 467                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
 468                                                                 i, e14, e10 | ((e18 >> 24) & 0x1f));
 469                                                 e18 &= ~0x1f000000;
 470                                         } else if (e18 & 0xc) {
 471                                                 /* g[] write fault? */
 472                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
 473                                                                 i, e14, e10 | ((e18 >> 7) & 0x1f));
 474                                                 e18 &= ~0x00000f80;
 475                                         } else {
 476                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
 477                                                                 i, e14, e10);
 478                                         }
 479                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 480                                                         i, e0c, e18, e1c, e20, e24);
 481                                 }
 482                                 ustatus &= ~0x00000080;
 483                         }
 484                         }
 485                         break;
 486                 }
 487                 if (ustatus) {
 488                         if (display)
 489                                 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
 490                 }
 491                 nv_wr32(dev, ustatus_addr, 0xc0000000);
 492         }
 493
 494         if (!tps && display)
 495                 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
 496 }
 497
 498 static int
 499 nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
 500 {
 501         u32 status = nv_rd32(dev, 0x400108);
 502         u32 ustatus;
 503
 504         if (!status && display) {
 505                 NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
 506                 return 1;
 507         }
 508
 509         /* DISPATCH: Relays commands to other units and handles NOTIFY,
 510          * COND, QUERY. If you get a trap from it, the command is still stuck
 511          * in DISPATCH and you need to do something about it. */
 512         if (status & 0x001) {
 513                 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
 514                 if (!ustatus && display) {
 515                         NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
 516                 }
 517
 518                 nv_wr32(dev, 0x400500, 0x00000000);
 519
 520                 /* Known to be triggered by screwed up NOTIFY and COND... */
 521                 if (ustatus & 0x00000001) {
 522                         u32 addr = nv_rd32(dev, 0x400808);
 523                         u32 subc = (addr & 0x00070000) >> 16;
 524                         u32 mthd = (addr & 0x00001ffc);
 525                         u32 datal = nv_rd32(dev, 0x40080c);
 526                         u32 datah = nv_rd32(dev, 0x400810);
 527                         u32 class = nv_rd32(dev, 0x400814);
 528                         u32 r848 = nv_rd32(dev, 0x400848);
 529
 530                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
 531                         if (display && (addr & 0x80000000)) {
 532                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 533                                              "subc %d class 0x%04x mthd 0x%04x "
 534                                              "data 0x%08x%08x "
 535                                              "400808 0x%08x 400848 0x%08x\n",
 536                                         chid, inst, subc, class, mthd, datah,
 537                                         datal, addr, r848);
 538                         } else
 539                         if (display) {
 540                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 541                         }
 542
 543                         nv_wr32(dev, 0x400808, 0);
 544                         nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
 545                         nv_wr32(dev, 0x400848, 0);
 546                         ustatus &= ~0x00000001;
 547                 }
 548
 549                 if (ustatus & 0x00000002) {
 550                         u32 addr = nv_rd32(dev, 0x40084c);
 551                         u32 subc = (addr & 0x00070000) >> 16;
 552                         u32 mthd = (addr & 0x00001ffc);
 553                         u32 data = nv_rd32(dev, 0x40085c);
 554                         u32 class = nv_rd32(dev, 0x400814);
 555
 556                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
 557                         if (display && (addr & 0x80000000)) {
 558                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 559                                              "subc %d class 0x%04x mthd 0x%04x "
 560                                              "data 0x%08x 40084c 0x%08x\n",
 561                                         chid, inst, subc, class, mthd,
 562                                         data, addr);
 563                         } else
 564                         if (display) {
 565                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 566                         }
 567
 568                         nv_wr32(dev, 0x40084c, 0);
 569                         ustatus &= ~0x00000002;
 570                 }
 571
 572                 if (ustatus && display) {
 573                         NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
 574                                       "0x%08x)\n", ustatus);
 575                 }
 576
 577                 nv_wr32(dev, 0x400804, 0xc0000000);
 578                 nv_wr32(dev, 0x400108, 0x001);
 579                 status &= ~0x001;
 580                 if (!status)
 581                         return 0;
 582         }
 583
 584         /* M2MF: Memory to memory copy engine. */
 585         if (status & 0x002) {
 586                 u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
 587                 if (display) {
 588                         NV_INFO(dev, "PGRAPH - TRAP_M2MF");
 589                         nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
 590                         printk("\n");
 591                         NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
 592                                 nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
 593                                 nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
 594
 595                 }
 596
 597                 /* No sane way found yet -- just reset the bugger. */
 598                 nv_wr32(dev, 0x400040, 2);
 599                 nv_wr32(dev, 0x400040, 0);
 600                 nv_wr32(dev, 0x406800, 0xc0000000);
 601                 nv_wr32(dev, 0x400108, 0x002);
 602                 status &= ~0x002;
 603         }
 604
 605         /* VFETCH: Fetches data from vertex buffers. */
 606         if (status & 0x004) {
 607                 u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
 608                 if (display) {
 609                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
 610                         nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
 611                         printk("\n");
 612                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
 613                                 nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
 614                                 nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
 615                 }
 616
 617                 nv_wr32(dev, 0x400c04, 0xc0000000);
 618                 nv_wr32(dev, 0x400108, 0x004);
 619                 status &= ~0x004;
 620         }
 621
 622         /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
 623         if (status & 0x008) {
 624                 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
 625                 if (display) {
 626                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
 627                         nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
 628                         printk("\n");
 629                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
 630                                 nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
 631                                 nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
 632
 633                 }
 634
 635                 /* No sane way found yet -- just reset the bugger. */
 636                 nv_wr32(dev, 0x400040, 0x80);
 637                 nv_wr32(dev, 0x400040, 0);
 638                 nv_wr32(dev, 0x401800, 0xc0000000);
 639                 nv_wr32(dev, 0x400108, 0x008);
 640                 status &= ~0x008;
 641         }
 642
 643         /* CCACHE: Handles code and c[] caches and fills them. */
 644         if (status & 0x010) {
 645                 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
 646                 if (display) {
 647                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
 648                         nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
 649                         printk("\n");
 650                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
 651                                      " %08x %08x %08x\n",
 652                                 nv_rd32(dev, 0x405000), nv_rd32(dev, 0x405004),
 653                                 nv_rd32(dev, 0x405008), nv_rd32(dev, 0x40500c),
 654                                 nv_rd32(dev, 0x405010), nv_rd32(dev, 0x405014),
 655                                 nv_rd32(dev, 0x40501c));
 656
 657                 }
 658
 659                 nv_wr32(dev, 0x405018, 0xc0000000);
 660                 nv_wr32(dev, 0x400108, 0x010);
 661                 status &= ~0x010;
 662         }
 663
 664         /* Unknown, not seen yet... 0x402000 is the only trap status reg
 665          * remaining, so try to handle it anyway. Perhaps related to that
 666          * unknown DMA slot on tesla? */
 667         if (status & 0x20) {
 668                 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
 669                 if (display)
 670                         NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
 671                 nv_wr32(dev, 0x402000, 0xc0000000);
 672                 /* no status modifiction on purpose */
 673         }
 674
 675         /* TEXTURE: CUDA texturing units */
 676         if (status & 0x040) {
 677                 nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
 678                                     "PGRAPH - TRAP_TEXTURE");
 679                 nv_wr32(dev, 0x400108, 0x040);
 680                 status &= ~0x040;
 681         }
 682
 683         /* MP: CUDA execution engines. */
 684         if (status & 0x080) {
 685                 nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
 686                                     "PGRAPH - TRAP_MP");
 687                 nv_wr32(dev, 0x400108, 0x080);
 688                 status &= ~0x080;
 689         }
 690
 691         /* TPDMA:  Handles TP-initiated uncached memory accesses:
 692          * l[], g[], stack, 2d surfaces, render targets. */
 693         if (status & 0x100) {
 694                 nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
 695                                     "PGRAPH - TRAP_TPDMA");
 696                 nv_wr32(dev, 0x400108, 0x100);
 697                 status &= ~0x100;
 698         }
 699
 700         if (status) {
 701                 if (display)
 702                         NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
 703                 nv_wr32(dev, 0x400108, status);
 704         }
 705
 706         return 1;
 707 }
 708
 709 int
 710 nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
 711 {
 712         struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 713         struct drm_nouveau_private *dev_priv = dev->dev_private;
 714         struct nouveau_channel *chan;
 715         unsigned long flags;
 716         int i;
 717
 718         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 719         for (i = 0; i < pfifo->channels; i++) {
 720                 chan = dev_priv->channels.ptr[i];
 721                 if (!chan || !chan->ramin)
 722                         continue;
 723
 724                 if (inst == chan->ramin->addr)
 725                         break;
 726         }
 727         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 728         return i;
 729 }
 730
 731 static void
 732 nv50_graph_isr(struct drm_device *dev)
 733 {
 734         u32 stat;
 735
 736         while ((stat = nv_rd32(dev, 0x400100))) {
 737                 u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
 738                 u32 chid = nv50_graph_isr_chid(dev, inst);
 739                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
 740                 u32 subc = (addr & 0x00070000) >> 16;
 741                 u32 mthd = (addr & 0x00001ffc);
 742                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
 743                 u32 class = nv_rd32(dev, 0x400814);
 744                 u32 show = stat;
 745
 746                 if (stat & 0x00000010) {
 747                         if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
 748                                                        mthd, data))
 749                                 show &= ~0x00000010;
 750                 }
 751
 752                 show = (show && nouveau_ratelimit()) ? show : 0;
 753
 754                 if (show & 0x00100000) {
 755                         u32 ecode = nv_rd32(dev, 0x400110);
 756                         NV_INFO(dev, "PGRAPH - DATA_ERROR ");
 757                         nouveau_enum_print(nv50_data_error_names, ecode);
 758                         printk("\n");
 759                 }
 760
 761                 if (stat & 0x00200000) {
 762                         if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
 763                                 show &= ~0x00200000;
 764                 }
 765
 766                 nv_wr32(dev, 0x400100, stat);
 767                 nv_wr32(dev, 0x400500, 0x00010001);
 768
 769                 if (show) {
 770                         NV_INFO(dev, "PGRAPH -");
 771                         nouveau_bitfield_print(nv50_graph_intr, show);
 772                         printk("\n");
 773                         NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
 774                                      "class 0x%04x mthd 0x%04x data 0x%08x\n",
 775                                 chid, inst, subc, class, mthd, data);
 776                         nv50_fb_vm_trap(dev, 1);
 777                 }
 778         }
 779
 780         if (nv_rd32(dev, 0x400824) & (1 << 31))
 781                 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
 782 }
 783
 784 static void
 785 nv50_graph_destroy(struct drm_device *dev, int engine)
 786 {
 787         struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
 788
 789         NVOBJ_ENGINE_DEL(dev, GR);
 790
 791         nouveau_irq_unregister(dev, 12);
 792         kfree(pgraph);
 793 }
 794
 795 int
 796 nv50_graph_create(struct drm_device *dev)
 797 {
 798         struct drm_nouveau_private *dev_priv = dev->dev_private;
 799         struct nv50_graph_engine *pgraph;
 800         int ret;
 801
 802         pgraph = kzalloc(sizeof(*pgraph),GFP_KERNEL);
 803         if (!pgraph)
 804                 return -ENOMEM;
 805
 806         ret = nv50_grctx_init(dev, pgraph->ctxprog, ARRAY_SIZE(pgraph->ctxprog),
 807                                   &pgraph->ctxprog_size,
 808                                   &pgraph->grctx_size);
 809         if (ret) {
 810                 NV_ERROR(dev, "PGRAPH: ctxprog build failed\n");
 811                 kfree(pgraph);
 812                 return 0;
 813         }
 814
 815         pgraph->base.destroy = nv50_graph_destroy;
 816         pgraph->base.init = nv50_graph_init;
 817         pgraph->base.fini = nv50_graph_fini;
 818         pgraph->base.context_new = nv50_graph_context_new;
 819         pgraph->base.context_del = nv50_graph_context_del;
 820         pgraph->base.object_new = nv50_graph_object_new;
 821         if (dev_priv->chipset == 0x50 || dev_priv->chipset == 0xac)
 822                 pgraph->base.tlb_flush = nv50_graph_tlb_flush;
 823         else
 824                 pgraph->base.tlb_flush = nv84_graph_tlb_flush;
 825
 826         nouveau_irq_register(dev, 12, nv50_graph_isr);
 827
 828         NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
 829         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
 830         NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
 831         NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
 832
 833         /* tesla */
 834         if (dev_priv->chipset == 0x50)
 835                 NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
 836         else
 837         if (dev_priv->chipset < 0xa0)
 838                 NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
 839         else {
 840                 switch (dev_priv->chipset) {
 841                 case 0xa0:
 842                 case 0xaa:
 843                 case 0xac:
 844                         NVOBJ_CLASS(dev, 0x8397, GR);
 845                         break;
 846                 case 0xa3:
 847                 case 0xa5:
 848                 case 0xa8:
 849                         NVOBJ_CLASS(dev, 0x8597, GR);
 850                         break;
 851                 case 0xaf:
 852                         NVOBJ_CLASS(dev, 0x8697, GR);
 853                         break;
 854                 }
 855         }
 856
 857         /* compute */
 858         NVOBJ_CLASS(dev, 0x50c0, GR);
 859         if (dev_priv->chipset  > 0xa0 &&
 860             dev_priv->chipset != 0xaa &&
 861             dev_priv->chipset != 0xac)
 862                 NVOBJ_CLASS(dev, 0x85c0, GR);
 863
 864         return 0;
 865 }