1 /* fuc microcode for nvc0 PGRAPH/GPC
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27 * - bracket certain functions with scratch writes, useful for debugging
28 * - watchdog timer around ctx operations
32 gpc_mmio_list_head: .b32 #mmio_list_base
34 tpc_mmio_list_head: .b32 #mmio_list_base
36 unk_mmio_list_head: .b32 #mmio_list_base
37 unk_mmio_list_tail: .b32 #mmio_list_base
55 // reports an exception to the host
57 // In: $r15 error code (see nvc0.fuc)
61 mov $r14 -0x67ec // 0x9814
63 call #nv_wr32 // HUB_CTXCTL_CC_SCRATCH[5] = error code
66 call #nv_wr32 // HUB_CTXCTL_INTR_UP_SET
70 // GPC fuc initialisation, executed by triggering ucode start, will
71 // fall through to main loop after completion.
74 // CC_SCRATCH[1]: context base
78 // 31:31: set to signal completion
80 // 31:0: GPC context size
89 iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
91 // setup i0 handler, and route all interrupts to it
95 iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
97 // enable fifo interrupt
99 iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
104 // figure out which GPC we are, and how many TPCs we have
107 iord $r2 I[$r1 + 0x000] // UNITS
112 st b32 D[$r0 + #tpc_count] $r2
113 st b32 D[$r0 + #tpc_mask] $r3
115 iord $r2 I[$r1 + 0x000] // MYINDEX
116 st b32 D[$r0 + #gpc_id] $r2
118 // initialise context base, and size tracking
121 iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
122 clear b32 $r3 // track GPC context size here
124 // set mmctx base addresses now so we don't have to do it later,
125 // they don't currently ever change
129 iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE
130 iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE
132 // calculate GPC mmio context size
133 ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
134 ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
139 // calculate per-TPC mmio context size
140 ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
141 ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
143 ld b32 $r14 D[$r0 + #tpc_count]
149 // calculate per-UNK mmio context size
150 ld b32 $r14 D[$r0 + #unk_mmio_list_head]
151 ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
153 ld b32 $r14 D[$r0 + #unk_count]
159 // round up base/size to 256 byte boundary (for strand SWBASE)
162 iowr I[$r4 + 0x000] $r3 // MMCTX_LOAD_COUNT, wtf for?!?
170 // calculate size of strand context data
172 call #strand_ctx_init
175 // save context size, and tell HUB we're done
178 iowr I[$r1 + 0x100] $r3 // CC_SCRATCH[1] = context size
182 iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000
184 // Main program loop, very simple, sleeps until woken up by the interrupt
185 // handler, pulls a command from the queue and executes its handler
194 // 0x0000-0x0003 are all context transfers
196 bra nc #main_not_ctx_xfer
197 // fetch $flags and mask off $p1/$p2
202 // set $p1/$p2 according to transfer type
206 // transfer context data
212 or $r15 E_BAD_COMMAND
228 // incoming fifo command?
229 iord $r10 I[$r0 + 0x200] // INTR
230 and $r11 $r10 0x00000004
232 // queue incoming fifo command for later processing
235 iord $r14 I[$r11 + 0x100] // FIFO_CMD
236 iord $r15 I[$r11 + 0x000] // FIFO_DATA
240 iowr I[$r11 + 0x000] $r14 // FIFO_ACK
242 // ack, and wake up main()
244 iowr I[$r0 + 0x100] $r10 // INTR_ACK
258 // Set this GPC's bit in HUB_BAR, used to signal completion of various
259 // activities to the HUB fuc
263 ld b32 $r14 D[$r0 + #gpc_id]
265 mov $r14 -0x6be8 // 0x409418 - HUB_BAR_SET
270 // Disables various things, waits a bit, and re-enables them..
272 // Not sure how exactly this helps, perhaps "ENABLE" is not such a
273 // good description for the bits we turn off? Anyways, without this,
274 // funny things happen.
280 iowr I[$r14] $r15 // GPC_RED_SWITCH = POWER
284 bra ne #ctx_redswitch_delay
286 iowr I[$r14] $r15 // GPC_RED_SWITCH = UNK11, ENABLE, POWER
289 // Transfer GPC context data between GPU and storage area
291 // In: $r15 context base address
292 // $p1 clear on save, set on load
293 // $p2 set if opposite direction done/will be done, so:
294 // on save it means: "a load will follow this save"
295 // on load it means: "a save preceeded this load"
298 // set context base address
301 iowr I[$r1 + 0x000] $r15// MEM_BASE
302 bra not $p1 #ctx_xfer_not_load
310 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
314 iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
317 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
320 xbit $r10 $flags $p1 // direction
324 ld b32 $r12 D[$r0 + #gpc_id]
326 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn
327 ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
328 ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
329 mov $r14 0 // not multi
332 // per-TPC mmio context
333 xbit $r10 $flags $p1 // direction
335 sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0
336 ld b32 $r12 D[$r0 + #gpc_id]
338 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0
339 ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
340 ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
341 ld b32 $r15 D[$r0 + #tpc_mask]
342 mov $r14 0x800 // stride = 0x800
346 // per-UNK mmio context
347 xbit $r10 $flags $p1 // direction
350 sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_UNK0
351 ld b32 $r12 D[$r0 + #gpc_id]
353 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0
354 ld b32 $r12 D[$r0 + #unk_mmio_list_head]
355 ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
356 ld b32 $r15 D[$r0 + #unk_mask]
357 mov $r14 0x200 // stride = 0x200
361 // wait for strands to finish
364 // if load, or a save without a load following, do some
365 // unknown stuff that's done after finishing a block of
367 bra $p1 #ctx_xfer_post
368 bra not $p2 #ctx_xfer_done
373 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0d
376 // mark completion in HUB's barrier
378 call #hub_barrier_done