drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/os.h>
  26 #include <core/client.h>
  27 #include <core/engctx.h>
  28 #include <core/ramht.h>
  29 #include <core/class.h>
  30 #include <core/math.h>
  31
  32 #include <subdev/timer.h>
  33 #include <subdev/bar.h>
  34
  35 #include <engine/dmaobj.h>
  36 #include <engine/fifo.h>
  37
  38 #include "nv50.h"
  39
  40 /*******************************************************************************
  41  * FIFO channel objects
  42  ******************************************************************************/
  43
  44 static int
  45 nv84_fifo_context_attach(struct nouveau_object *parent,
  46                          struct nouveau_object *object)
  47 {
  48         struct nouveau_bar *bar = nouveau_bar(parent);
  49         struct nv50_fifo_base *base = (void *)parent->parent;
  50         struct nouveau_gpuobj *ectx = (void *)object;
  51         u64 limit = ectx->addr + ectx->size - 1;
  52         u64 start = ectx->addr;
  53         u32 addr;
  54
  55         switch (nv_engidx(object->engine)) {
  56         case NVDEV_ENGINE_SW   : return 0;
  57         case NVDEV_ENGINE_GR   : addr = 0x0020; break;
  58         case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
  59         case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
  60         case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
  61         default:
  62                 return -EINVAL;
  63         }
  64
  65         nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
  66         nv_wo32(base->eng, addr + 0x00, 0x00190000);
  67         nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
  68         nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
  69         nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
  70                                         upper_32_bits(start));
  71         nv_wo32(base->eng, addr + 0x10, 0x00000000);
  72         nv_wo32(base->eng, addr + 0x14, 0x00000000);
  73         bar->flush(bar);
  74         return 0;
  75 }
  76
  77 static int
  78 nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
  79                          struct nouveau_object *object)
  80 {
  81         struct nouveau_bar *bar = nouveau_bar(parent);
  82         struct nv50_fifo_priv *priv = (void *)parent->engine;
  83         struct nv50_fifo_base *base = (void *)parent->parent;
  84         struct nv50_fifo_chan *chan = (void *)parent;
  85         u32 addr, save, engn;
  86         bool done;
  87
  88         switch (nv_engidx(object->engine)) {
  89         case NVDEV_ENGINE_SW   : return 0;
  90         case NVDEV_ENGINE_GR   : engn = 0; addr = 0x0020; break;
  91         case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
  92         case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
  93         case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
  94         default:
  95                 return -EINVAL;
  96         }
  97
  98         nv_wo32(base->eng, addr + 0x00, 0x00000000);
  99         nv_wo32(base->eng, addr + 0x04, 0x00000000);
 100         nv_wo32(base->eng, addr + 0x08, 0x00000000);
 101         nv_wo32(base->eng, addr + 0x0c, 0x00000000);
 102         nv_wo32(base->eng, addr + 0x10, 0x00000000);
 103         nv_wo32(base->eng, addr + 0x14, 0x00000000);
 104         bar->flush(bar);
 105
 106         save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn);
 107         nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
 108         done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff);
 109         nv_wr32(priv, 0x002520, save);
 110         if (!done) {
 111                 nv_error(priv, "channel %d unload timeout\n", chan->base.chid);
 112                 if (suspend)
 113                         return -EBUSY;
 114         }
 115         return 0;
 116 }
 117
 118 static int
 119 nv84_fifo_object_attach(struct nouveau_object *parent,
 120                         struct nouveau_object *object, u32 handle)
 121 {
 122         struct nv50_fifo_chan *chan = (void *)parent;
 123         u32 context;
 124
 125         if (nv_iclass(object, NV_GPUOBJ_CLASS))
 126                 context = nv_gpuobj(object)->node->offset >> 4;
 127         else
 128                 context = 0x00000004; /* just non-zero */
 129
 130         switch (nv_engidx(object->engine)) {
 131         case NVDEV_ENGINE_DMAOBJ:
 132         case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
 133         case NVDEV_ENGINE_GR    : context |= 0x00100000; break;
 134         case NVDEV_ENGINE_MPEG  :
 135         case NVDEV_ENGINE_PPP   : context |= 0x00200000; break;
 136         case NVDEV_ENGINE_ME    :
 137         case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
 138         case NVDEV_ENGINE_VP    : context |= 0x00400000; break;
 139         case NVDEV_ENGINE_CRYPT :
 140         case NVDEV_ENGINE_UNK1C1: context |= 0x00500000; break;
 141         case NVDEV_ENGINE_BSP   : context |= 0x00600000; break;
 142         default:
 143                 return -EINVAL;
 144         }
 145
 146         return nouveau_ramht_insert(chan->ramht, 0, handle, context);
 147 }
 148
 149 static int
 150 nv84_fifo_chan_ctor(struct nouveau_object *parent,
 151                     struct nouveau_object *engine,
 152                     struct nouveau_oclass *oclass, void *data, u32 size,
 153                     struct nouveau_object **pobject)
 154 {
 155         struct nouveau_bar *bar = nouveau_bar(parent);
 156         struct nv50_fifo_base *base = (void *)parent;
 157         struct nv50_fifo_chan *chan;
 158         struct nv50_channel_ind_class *args = data;
 159         u64 ioffset, ilength;
 160         int ret;
 161
 162         if (size < sizeof(*args))
 163                 return -EINVAL;
 164
 165         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 166                                           0x2000, args->pushbuf,
 167                                           (1 << NVDEV_ENGINE_DMAOBJ) |
 168                                           (1 << NVDEV_ENGINE_SW) |
 169                                           (1 << NVDEV_ENGINE_GR) |
 170                                           (1 << NVDEV_ENGINE_MPEG) |
 171                                           (1 << NVDEV_ENGINE_ME) |
 172                                           (1 << NVDEV_ENGINE_VP) |
 173                                           (1 << NVDEV_ENGINE_CRYPT) |
 174                                           (1 << NVDEV_ENGINE_BSP) |
 175                                           (1 << NVDEV_ENGINE_PPP) |
 176                                           (1 << NVDEV_ENGINE_COPY0) |
 177                                           (1 << NVDEV_ENGINE_UNK1C1), &chan);
 178         *pobject = nv_object(chan);
 179         if (ret)
 180                 return ret;
 181
 182         ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht);
 183         if (ret)
 184                 return ret;
 185
 186         nv_parent(chan)->context_attach = nv84_fifo_context_attach;
 187         nv_parent(chan)->context_detach = nv84_fifo_context_detach;
 188         nv_parent(chan)->object_attach = nv84_fifo_object_attach;
 189         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 190
 191         ioffset = args->ioffset;
 192         ilength = log2i(args->ilength / 8);
 193
 194         nv_wo32(base->ramfc, 0x3c, 0x403f6078);
 195         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 196         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 197         nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
 198         nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
 199         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 200         nv_wo32(base->ramfc, 0x78, 0x00000000);
 201         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 202         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 203                                    (4 << 24) /* SEARCH_FULL */ |
 204                                    (chan->ramht->base.node->offset >> 4));
 205         nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
 206         nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
 207         bar->flush(bar);
 208         return 0;
 209 }
 210
 211 static int
 212 nv84_fifo_chan_init(struct nouveau_object *object)
 213 {
 214         struct nv50_fifo_priv *priv = (void *)object->engine;
 215         struct nv50_fifo_base *base = (void *)object->parent;
 216         struct nv50_fifo_chan *chan = (void *)object;
 217         struct nouveau_gpuobj *ramfc = base->ramfc;
 218         u32 chid = chan->base.chid;
 219         int ret;
 220
 221         ret = nouveau_fifo_channel_init(&chan->base);
 222         if (ret)
 223                 return ret;
 224
 225         nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);
 226         nv50_fifo_playlist_update(priv);
 227         return 0;
 228 }
 229
 230 static struct nouveau_ofuncs
 231 nv84_fifo_ofuncs = {
 232         .ctor = nv84_fifo_chan_ctor,
 233         .dtor = nv50_fifo_chan_dtor,
 234         .init = nv84_fifo_chan_init,
 235         .fini = nv50_fifo_chan_fini,
 236         .rd32 = _nouveau_fifo_channel_rd32,
 237         .wr32 = _nouveau_fifo_channel_wr32,
 238 };
 239
 240 static struct nouveau_oclass
 241 nv84_fifo_sclass[] = {
 242         { 0x826f, &nv84_fifo_ofuncs },
 243         {}
 244 };
 245
 246 /*******************************************************************************
 247  * FIFO context - basically just the instmem reserved for the channel
 248  ******************************************************************************/
 249
 250 int
 251 nv84_fifo_context_ctor(struct nouveau_object *parent,
 252                        struct nouveau_object *engine,
 253                        struct nouveau_oclass *oclass, void *data, u32 size,
 254                        struct nouveau_object **pobject)
 255 {
 256         struct nv50_fifo_base *base;
 257         int ret;
 258
 259         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
 260                                           0x1000, NVOBJ_FLAG_HEAP, &base);
 261         *pobject = nv_object(base);
 262         if (ret)
 263                 return ret;
 264
 265         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x0200, 0,
 266                                  NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
 267         if (ret)
 268                 return ret;
 269
 270         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x4000, 0,
 271                                  0, &base->pgd);
 272         if (ret)
 273                 return ret;
 274
 275         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 276         if (ret)
 277                 return ret;
 278
 279         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x1000, 0x400,
 280                                  NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
 281         if (ret)
 282                 return ret;
 283
 284         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x0100, 0x100,
 285                                  NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
 286         if (ret)
 287                 return ret;
 288
 289         return 0;
 290 }
 291
 292 static struct nouveau_oclass
 293 nv84_fifo_cclass = {
 294         .handle = NV_ENGCTX(FIFO, 0x84),
 295         .ofuncs = &(struct nouveau_ofuncs) {
 296                 .ctor = nv84_fifo_context_ctor,
 297                 .dtor = nv50_fifo_context_dtor,
 298                 .init = _nouveau_fifo_context_init,
 299                 .fini = _nouveau_fifo_context_fini,
 300                 .rd32 = _nouveau_fifo_context_rd32,
 301                 .wr32 = _nouveau_fifo_context_wr32,
 302         },
 303 };
 304
 305 /*******************************************************************************
 306  * PFIFO engine
 307  ******************************************************************************/
 308
 309 static int
 310 nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 311                struct nouveau_oclass *oclass, void *data, u32 size,
 312                struct nouveau_object **pobject)
 313 {
 314         struct nv50_fifo_priv *priv;
 315         int ret;
 316
 317         ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
 318         *pobject = nv_object(priv);
 319         if (ret)
 320                 return ret;
 321
 322         ret = nouveau_gpuobj_new(parent, NULL, 128 * 4, 0x1000, 0,
 323                                 &priv->playlist[0]);
 324         if (ret)
 325                 return ret;
 326
 327         ret = nouveau_gpuobj_new(parent, NULL, 128 * 4, 0x1000, 0,
 328                                 &priv->playlist[1]);
 329         if (ret)
 330                 return ret;
 331
 332         nv_subdev(priv)->unit = 0x00000100;
 333         nv_subdev(priv)->intr = nv04_fifo_intr;
 334         nv_engine(priv)->cclass = &nv84_fifo_cclass;
 335         nv_engine(priv)->sclass = nv84_fifo_sclass;
 336         return 0;
 337 }
 338
 339 struct nouveau_oclass
 340 nv84_fifo_oclass = {
 341         .handle = NV_ENGINE(FIFO, 0x84),
 342         .ofuncs = &(struct nouveau_ofuncs) {
 343                 .ctor = nv84_fifo_ctor,
 344                 .dtor = nv50_fifo_dtor,
 345                 .init = nv50_fifo_init,
 346                 .fini = _nouveau_fifo_fini,
 347         },
 348 };