drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/engctx.h>
  27 #include <core/ramht.h>
  28 #include <core/class.h>
  29 #include <core/math.h>
  30
  31 #include <subdev/timer.h>
  32 #include <subdev/bar.h>
  33
  34 #include <engine/dmaobj.h>
  35 #include <engine/fifo.h>
  36
  37 #include "nv50.h"
  38
  39 /*******************************************************************************
  40  * FIFO channel objects
  41  ******************************************************************************/
  42
  43 void
  44 nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
  45 {
  46         struct nouveau_bar *bar = nouveau_bar(priv);
  47         struct nouveau_gpuobj *cur;
  48         int i, p;
  49
  50         cur = priv->playlist[priv->cur_playlist];
  51         priv->cur_playlist = !priv->cur_playlist;
  52
  53         for (i = priv->base.min, p = 0; i < priv->base.max; i++) {
  54                 if (nv_rd32(priv, 0x002600 + (i * 4)) & 0x80000000)
  55                         nv_wo32(cur, p++ * 4, i);
  56         }
  57
  58         bar->flush(bar);
  59
  60         nv_wr32(priv, 0x0032f4, cur->addr >> 12);
  61         nv_wr32(priv, 0x0032ec, p);
  62         nv_wr32(priv, 0x002500, 0x00000101);
  63 }
  64
  65 static int
  66 nv50_fifo_context_attach(struct nouveau_object *parent,
  67                          struct nouveau_object *object)
  68 {
  69         struct nouveau_bar *bar = nouveau_bar(parent);
  70         struct nv50_fifo_base *base = (void *)parent->parent;
  71         struct nouveau_gpuobj *ectx = (void *)object;
  72         u64 limit = ectx->addr + ectx->size - 1;
  73         u64 start = ectx->addr;
  74         u32 addr;
  75
  76         switch (nv_engidx(object->engine)) {
  77         case NVDEV_ENGINE_SW   : return 0;
  78         case NVDEV_ENGINE_GR   : addr = 0x0000; break;
  79         case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
  80         default:
  81                 return -EINVAL;
  82         }
  83
  84         nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
  85         nv_wo32(base->eng, addr + 0x00, 0x00190000);
  86         nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
  87         nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
  88         nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
  89                                         upper_32_bits(start));
  90         nv_wo32(base->eng, addr + 0x10, 0x00000000);
  91         nv_wo32(base->eng, addr + 0x14, 0x00000000);
  92         bar->flush(bar);
  93         return 0;
  94 }
  95
  96 static int
  97 nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend,
  98                          struct nouveau_object *object)
  99 {
 100         struct nouveau_bar *bar = nouveau_bar(parent);
 101         struct nv50_fifo_priv *priv = (void *)parent->engine;
 102         struct nv50_fifo_base *base = (void *)parent->parent;
 103         struct nv50_fifo_chan *chan = (void *)parent;
 104         u32 addr, me;
 105         int ret = 0;
 106
 107         switch (nv_engidx(object->engine)) {
 108         case NVDEV_ENGINE_SW   : return 0;
 109         case NVDEV_ENGINE_GR   : addr = 0x0000; break;
 110         case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
 111         default:
 112                 return -EINVAL;
 113         }
 114
 115         /* HW bug workaround:
 116          *
 117          * PFIFO will hang forever if the connected engines don't report
 118          * that they've processed the context switch request.
 119          *
 120          * In order for the kickoff to work, we need to ensure all the
 121          * connected engines are in a state where they can answer.
 122          *
 123          * Newer chipsets don't seem to suffer from this issue, and well,
 124          * there's also a "ignore these engines" bitmask reg we can use
 125          * if we hit the issue there..
 126          */
 127         me = nv_mask(priv, 0x00b860, 0x00000001, 0x00000001);
 128
 129         /* do the kickoff... */
 130         nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
 131         if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) {
 132                 nv_error(priv, "channel %d unload timeout\n", chan->base.chid);
 133                 if (suspend)
 134                         ret = -EBUSY;
 135         }
 136         nv_wr32(priv, 0x00b860, me);
 137
 138         if (ret == 0) {
 139                 nv_wo32(base->eng, addr + 0x00, 0x00000000);
 140                 nv_wo32(base->eng, addr + 0x04, 0x00000000);
 141                 nv_wo32(base->eng, addr + 0x08, 0x00000000);
 142                 nv_wo32(base->eng, addr + 0x0c, 0x00000000);
 143                 nv_wo32(base->eng, addr + 0x10, 0x00000000);
 144                 nv_wo32(base->eng, addr + 0x14, 0x00000000);
 145                 bar->flush(bar);
 146         }
 147
 148         return ret;
 149 }
 150
 151 static int
 152 nv50_fifo_object_attach(struct nouveau_object *parent,
 153                         struct nouveau_object *object, u32 handle)
 154 {
 155         struct nv50_fifo_chan *chan = (void *)parent;
 156         u32 context;
 157
 158         if (nv_iclass(object, NV_GPUOBJ_CLASS))
 159                 context = nv_gpuobj(object)->node->offset >> 4;
 160         else
 161                 context = 0x00000004; /* just non-zero */
 162
 163         switch (nv_engidx(object->engine)) {
 164         case NVDEV_ENGINE_DMAOBJ:
 165         case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
 166         case NVDEV_ENGINE_GR    : context |= 0x00100000; break;
 167         case NVDEV_ENGINE_MPEG  : context |= 0x00200000; break;
 168         default:
 169                 return -EINVAL;
 170         }
 171
 172         return nouveau_ramht_insert(chan->ramht, 0, handle, context);
 173 }
 174
 175 void
 176 nv50_fifo_object_detach(struct nouveau_object *parent, int cookie)
 177 {
 178         struct nv50_fifo_chan *chan = (void *)parent;
 179         nouveau_ramht_remove(chan->ramht, cookie);
 180 }
 181
 182 static int
 183 nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
 184                         struct nouveau_object *engine,
 185                         struct nouveau_oclass *oclass, void *data, u32 size,
 186                         struct nouveau_object **pobject)
 187 {
 188         struct nouveau_bar *bar = nouveau_bar(parent);
 189         struct nv50_fifo_base *base = (void *)parent;
 190         struct nv50_fifo_chan *chan;
 191         struct nv03_channel_dma_class *args = data;
 192         int ret;
 193
 194         if (size < sizeof(*args))
 195                 return -EINVAL;
 196
 197         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 198                                           0x2000, args->pushbuf,
 199                                           (1ULL << NVDEV_ENGINE_DMAOBJ) |
 200                                           (1ULL << NVDEV_ENGINE_SW) |
 201                                           (1ULL << NVDEV_ENGINE_GR) |
 202                                           (1ULL << NVDEV_ENGINE_MPEG), &chan);
 203         *pobject = nv_object(chan);
 204         if (ret)
 205                 return ret;
 206
 207         nv_parent(chan)->context_attach = nv50_fifo_context_attach;
 208         nv_parent(chan)->context_detach = nv50_fifo_context_detach;
 209         nv_parent(chan)->object_attach = nv50_fifo_object_attach;
 210         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 211
 212         ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht);
 213         if (ret)
 214                 return ret;
 215
 216         nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset));
 217         nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset));
 218         nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset));
 219         nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset));
 220         nv_wo32(base->ramfc, 0x3c, 0x003f6078);
 221         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 222         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 223         nv_wo32(base->ramfc, 0x4c, 0xffffffff);
 224         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 225         nv_wo32(base->ramfc, 0x78, 0x00000000);
 226         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 227         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 228                                    (4 << 24) /* SEARCH_FULL */ |
 229                                    (chan->ramht->base.node->offset >> 4));
 230         bar->flush(bar);
 231         return 0;
 232 }
 233
 234 static int
 235 nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
 236                         struct nouveau_object *engine,
 237                         struct nouveau_oclass *oclass, void *data, u32 size,
 238                         struct nouveau_object **pobject)
 239 {
 240         struct nv50_channel_ind_class *args = data;
 241         struct nouveau_bar *bar = nouveau_bar(parent);
 242         struct nv50_fifo_base *base = (void *)parent;
 243         struct nv50_fifo_chan *chan;
 244         u64 ioffset, ilength;
 245         int ret;
 246
 247         if (size < sizeof(*args))
 248                 return -EINVAL;
 249
 250         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 251                                           0x2000, args->pushbuf,
 252                                           (1ULL << NVDEV_ENGINE_DMAOBJ) |
 253                                           (1ULL << NVDEV_ENGINE_SW) |
 254                                           (1ULL << NVDEV_ENGINE_GR) |
 255                                           (1ULL << NVDEV_ENGINE_MPEG), &chan);
 256         *pobject = nv_object(chan);
 257         if (ret)
 258                 return ret;
 259
 260         nv_parent(chan)->context_attach = nv50_fifo_context_attach;
 261         nv_parent(chan)->context_detach = nv50_fifo_context_detach;
 262         nv_parent(chan)->object_attach = nv50_fifo_object_attach;
 263         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 264
 265         ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht);
 266         if (ret)
 267                 return ret;
 268
 269         ioffset = args->ioffset;
 270         ilength = log2i(args->ilength / 8);
 271
 272         nv_wo32(base->ramfc, 0x3c, 0x403f6078);
 273         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 274         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 275         nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
 276         nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
 277         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 278         nv_wo32(base->ramfc, 0x78, 0x00000000);
 279         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 280         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 281                                    (4 << 24) /* SEARCH_FULL */ |
 282                                    (chan->ramht->base.node->offset >> 4));
 283         bar->flush(bar);
 284         return 0;
 285 }
 286
 287 void
 288 nv50_fifo_chan_dtor(struct nouveau_object *object)
 289 {
 290         struct nv50_fifo_chan *chan = (void *)object;
 291         nouveau_ramht_ref(NULL, &chan->ramht);
 292         nouveau_fifo_channel_destroy(&chan->base);
 293 }
 294
 295 static int
 296 nv50_fifo_chan_init(struct nouveau_object *object)
 297 {
 298         struct nv50_fifo_priv *priv = (void *)object->engine;
 299         struct nv50_fifo_base *base = (void *)object->parent;
 300         struct nv50_fifo_chan *chan = (void *)object;
 301         struct nouveau_gpuobj *ramfc = base->ramfc;
 302         u32 chid = chan->base.chid;
 303         int ret;
 304
 305         ret = nouveau_fifo_channel_init(&chan->base);
 306         if (ret)
 307                 return ret;
 308
 309         nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12);
 310         nv50_fifo_playlist_update(priv);
 311         return 0;
 312 }
 313
 314 int
 315 nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 316 {
 317         struct nv50_fifo_priv *priv = (void *)object->engine;
 318         struct nv50_fifo_chan *chan = (void *)object;
 319         u32 chid = chan->base.chid;
 320
 321         /* remove channel from playlist, fifo will unload context */
 322         nv_mask(priv, 0x002600 + (chid * 4), 0x80000000, 0x00000000);
 323         nv50_fifo_playlist_update(priv);
 324         nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000);
 325
 326         return nouveau_fifo_channel_fini(&chan->base, suspend);
 327 }
 328
 329 static struct nouveau_ofuncs
 330 nv50_fifo_ofuncs_dma = {
 331         .ctor = nv50_fifo_chan_ctor_dma,
 332         .dtor = nv50_fifo_chan_dtor,
 333         .init = nv50_fifo_chan_init,
 334         .fini = nv50_fifo_chan_fini,
 335         .rd32 = _nouveau_fifo_channel_rd32,
 336         .wr32 = _nouveau_fifo_channel_wr32,
 337 };
 338
 339 static struct nouveau_ofuncs
 340 nv50_fifo_ofuncs_ind = {
 341         .ctor = nv50_fifo_chan_ctor_ind,
 342         .dtor = nv50_fifo_chan_dtor,
 343         .init = nv50_fifo_chan_init,
 344         .fini = nv50_fifo_chan_fini,
 345         .rd32 = _nouveau_fifo_channel_rd32,
 346         .wr32 = _nouveau_fifo_channel_wr32,
 347 };
 348
 349 static struct nouveau_oclass
 350 nv50_fifo_sclass[] = {
 351         { NV50_CHANNEL_DMA_CLASS, &nv50_fifo_ofuncs_dma },
 352         { NV50_CHANNEL_IND_CLASS, &nv50_fifo_ofuncs_ind },
 353         {}
 354 };
 355
 356 /*******************************************************************************
 357  * FIFO context - basically just the instmem reserved for the channel
 358  ******************************************************************************/
 359
 360 static int
 361 nv50_fifo_context_ctor(struct nouveau_object *parent,
 362                        struct nouveau_object *engine,
 363                        struct nouveau_oclass *oclass, void *data, u32 size,
 364                        struct nouveau_object **pobject)
 365 {
 366         struct nv50_fifo_base *base;
 367         int ret;
 368
 369         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
 370                                           0x1000, NVOBJ_FLAG_HEAP, &base);
 371         *pobject = nv_object(base);
 372         if (ret)
 373                 return ret;
 374
 375         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x0200, 0x1000,
 376                                  NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
 377         if (ret)
 378                 return ret;
 379
 380         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x1200, 0,
 381                                  NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
 382         if (ret)
 383                 return ret;
 384
 385         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x4000, 0, 0,
 386                                 &base->pgd);
 387         if (ret)
 388                 return ret;
 389
 390         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 391         if (ret)
 392                 return ret;
 393
 394         return 0;
 395 }
 396
 397 void
 398 nv50_fifo_context_dtor(struct nouveau_object *object)
 399 {
 400         struct nv50_fifo_base *base = (void *)object;
 401         nouveau_vm_ref(NULL, &base->vm, base->pgd);
 402         nouveau_gpuobj_ref(NULL, &base->pgd);
 403         nouveau_gpuobj_ref(NULL, &base->eng);
 404         nouveau_gpuobj_ref(NULL, &base->ramfc);
 405         nouveau_gpuobj_ref(NULL, &base->cache);
 406         nouveau_fifo_context_destroy(&base->base);
 407 }
 408
 409 static struct nouveau_oclass
 410 nv50_fifo_cclass = {
 411         .handle = NV_ENGCTX(FIFO, 0x50),
 412         .ofuncs = &(struct nouveau_ofuncs) {
 413                 .ctor = nv50_fifo_context_ctor,
 414                 .dtor = nv50_fifo_context_dtor,
 415                 .init = _nouveau_fifo_context_init,
 416                 .fini = _nouveau_fifo_context_fini,
 417                 .rd32 = _nouveau_fifo_context_rd32,
 418                 .wr32 = _nouveau_fifo_context_wr32,
 419         },
 420 };
 421
 422 /*******************************************************************************
 423  * PFIFO engine
 424  ******************************************************************************/
 425
 426 static int
 427 nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 428                struct nouveau_oclass *oclass, void *data, u32 size,
 429                struct nouveau_object **pobject)
 430 {
 431         struct nv50_fifo_priv *priv;
 432         int ret;
 433
 434         ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
 435         *pobject = nv_object(priv);
 436         if (ret)
 437                 return ret;
 438
 439         ret = nouveau_gpuobj_new(parent, NULL, 128 * 4, 0x1000, 0,
 440                                 &priv->playlist[0]);
 441         if (ret)
 442                 return ret;
 443
 444         ret = nouveau_gpuobj_new(parent, NULL, 128 * 4, 0x1000, 0,
 445                                 &priv->playlist[1]);
 446         if (ret)
 447                 return ret;
 448
 449         nv_subdev(priv)->unit = 0x00000100;
 450         nv_subdev(priv)->intr = nv04_fifo_intr;
 451         nv_engine(priv)->cclass = &nv50_fifo_cclass;
 452         nv_engine(priv)->sclass = nv50_fifo_sclass;
 453         return 0;
 454 }
 455
 456 void
 457 nv50_fifo_dtor(struct nouveau_object *object)
 458 {
 459         struct nv50_fifo_priv *priv = (void *)object;
 460
 461         nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
 462         nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
 463
 464         nouveau_fifo_destroy(&priv->base);
 465 }
 466
 467 int
 468 nv50_fifo_init(struct nouveau_object *object)
 469 {
 470         struct nv50_fifo_priv *priv = (void *)object;
 471         int ret, i;
 472
 473         ret = nouveau_fifo_init(&priv->base);
 474         if (ret)
 475                 return ret;
 476
 477         nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
 478         nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
 479         nv_wr32(priv, 0x00250c, 0x6f3cfc34);
 480         nv_wr32(priv, 0x002044, 0x01003fff);
 481
 482         nv_wr32(priv, 0x002100, 0xffffffff);
 483         nv_wr32(priv, 0x002140, 0xffffffff);
 484
 485         for (i = 0; i < 128; i++)
 486                 nv_wr32(priv, 0x002600 + (i * 4), 0x00000000);
 487         nv50_fifo_playlist_update(priv);
 488
 489         nv_wr32(priv, 0x003200, 0x00000001);
 490         nv_wr32(priv, 0x003250, 0x00000001);
 491         nv_wr32(priv, 0x002500, 0x00000001);
 492         return 0;
 493 }
 494
 495 struct nouveau_oclass
 496 nv50_fifo_oclass = {
 497         .handle = NV_ENGINE(FIFO, 0x50),
 498         .ofuncs = &(struct nouveau_ofuncs) {
 499                 .ctor = nv50_fifo_ctor,
 500                 .dtor = nv50_fifo_dtor,
 501                 .init = nv50_fifo_init,
 502                 .fini = _nouveau_fifo_fini,
 503         },
 504 };