drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/os.h>
  26 #include <core/class.h>
  27 #include <core/engctx.h>
  28 #include <core/ramht.h>
  29
  30 #include <subdev/instmem.h>
  31 #include <subdev/instmem/nv04.h>
  32 #include <subdev/fb.h>
  33
  34 #include <engine/fifo.h>
  35
  36 #include "nv04.h"
  37
  38 static struct ramfc_desc
  39 nv40_ramfc[] = {
  40         { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
  41         { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
  42         { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
  43         { 32,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
  44         { 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
  45         { 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_STATE },
  46         { 28,  0, 0x18,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
  47         {  2, 28, 0x18, 28, 0x002058 },
  48         { 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_ENGINE },
  49         { 32,  0, 0x20,  0, NV04_PFIFO_CACHE1_PULL1 },
  50         { 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
  51         { 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
  52         { 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
  53         { 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
  54         { 32,  0, 0x34,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
  55         { 32,  0, 0x38,  0, NV40_PFIFO_GRCTX_INSTANCE },
  56         { 17,  0, 0x3c,  0, NV04_PFIFO_DMA_TIMESLICE },
  57         { 32,  0, 0x40,  0, 0x0032e4 },
  58         { 32,  0, 0x44,  0, 0x0032e8 },
  59         { 32,  0, 0x4c,  0, 0x002088 },
  60         { 32,  0, 0x50,  0, 0x003300 },
  61         { 32,  0, 0x54,  0, 0x00330c },
  62         {}
  63 };
  64
  65 /*******************************************************************************
  66  * FIFO channel objects
  67  ******************************************************************************/
  68
  69 static int
  70 nv40_fifo_object_attach(struct nouveau_object *parent,
  71                         struct nouveau_object *object, u32 handle)
  72 {
  73         struct nv04_fifo_priv *priv = (void *)parent->engine;
  74         struct nv04_fifo_chan *chan = (void *)parent;
  75         u32 context, chid = chan->base.chid;
  76         int ret;
  77
  78         if (nv_iclass(object, NV_GPUOBJ_CLASS))
  79                 context = nv_gpuobj(object)->addr >> 4;
  80         else
  81                 context = 0x00000004; /* just non-zero */
  82
  83         switch (nv_engidx(object->engine)) {
  84         case NVDEV_ENGINE_DMAOBJ:
  85         case NVDEV_ENGINE_SW:
  86                 context |= 0x00000000;
  87                 break;
  88         case NVDEV_ENGINE_GR:
  89                 context |= 0x00100000;
  90                 break;
  91         case NVDEV_ENGINE_MPEG:
  92                 context |= 0x00200000;
  93                 break;
  94         default:
  95                 return -EINVAL;
  96         }
  97
  98         context |= chid << 23;
  99
 100         mutex_lock(&nv_subdev(priv)->mutex);
 101         ret = nouveau_ramht_insert(priv->ramht, chid, handle, context);
 102         mutex_unlock(&nv_subdev(priv)->mutex);
 103         return ret;
 104 }
 105
 106 static int
 107 nv40_fifo_context_attach(struct nouveau_object *parent,
 108                          struct nouveau_object *engctx)
 109 {
 110         struct nv04_fifo_priv *priv = (void *)parent->engine;
 111         struct nv04_fifo_chan *chan = (void *)parent;
 112         unsigned long flags;
 113         u32 reg, ctx;
 114
 115         switch (nv_engidx(engctx->engine)) {
 116         case NVDEV_ENGINE_SW:
 117                 return 0;
 118         case NVDEV_ENGINE_GR:
 119                 reg = 0x32e0;
 120                 ctx = 0x38;
 121                 break;
 122         case NVDEV_ENGINE_MPEG:
 123                 reg = 0x330c;
 124                 ctx = 0x54;
 125                 break;
 126         default:
 127                 return -EINVAL;
 128         }
 129
 130         spin_lock_irqsave(&priv->base.lock, flags);
 131         nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4;
 132         nv_mask(priv, 0x002500, 0x00000001, 0x00000000);
 133
 134         if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid)
 135                 nv_wr32(priv, reg, nv_engctx(engctx)->addr);
 136         nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr);
 137
 138         nv_mask(priv, 0x002500, 0x00000001, 0x00000001);
 139         spin_unlock_irqrestore(&priv->base.lock, flags);
 140         return 0;
 141 }
 142
 143 static int
 144 nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 145                          struct nouveau_object *engctx)
 146 {
 147         struct nv04_fifo_priv *priv = (void *)parent->engine;
 148         struct nv04_fifo_chan *chan = (void *)parent;
 149         unsigned long flags;
 150         u32 reg, ctx;
 151
 152         switch (nv_engidx(engctx->engine)) {
 153         case NVDEV_ENGINE_SW:
 154                 return 0;
 155         case NVDEV_ENGINE_GR:
 156                 reg = 0x32e0;
 157                 ctx = 0x38;
 158                 break;
 159         case NVDEV_ENGINE_MPEG:
 160                 reg = 0x330c;
 161                 ctx = 0x54;
 162                 break;
 163         default:
 164                 return -EINVAL;
 165         }
 166
 167         spin_lock_irqsave(&priv->base.lock, flags);
 168         nv_mask(priv, 0x002500, 0x00000001, 0x00000000);
 169
 170         if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid)
 171                 nv_wr32(priv, reg, 0x00000000);
 172         nv_wo32(priv->ramfc, chan->ramfc + ctx, 0x00000000);
 173
 174         nv_mask(priv, 0x002500, 0x00000001, 0x00000001);
 175         spin_unlock_irqrestore(&priv->base.lock, flags);
 176         return 0;
 177 }
 178
 179 static int
 180 nv40_fifo_chan_ctor(struct nouveau_object *parent,
 181                     struct nouveau_object *engine,
 182                     struct nouveau_oclass *oclass, void *data, u32 size,
 183                     struct nouveau_object **pobject)
 184 {
 185         struct nv04_fifo_priv *priv = (void *)engine;
 186         struct nv04_fifo_chan *chan;
 187         struct nv03_channel_dma_class *args = data;
 188         int ret;
 189
 190         if (size < sizeof(*args))
 191                 return -EINVAL;
 192
 193         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 194                                           0x1000, args->pushbuf,
 195                                           (1ULL << NVDEV_ENGINE_DMAOBJ) |
 196                                           (1ULL << NVDEV_ENGINE_SW) |
 197                                           (1ULL << NVDEV_ENGINE_GR) |
 198                                           (1ULL << NVDEV_ENGINE_MPEG), &chan);
 199         *pobject = nv_object(chan);
 200         if (ret)
 201                 return ret;
 202
 203         nv_parent(chan)->context_attach = nv40_fifo_context_attach;
 204         nv_parent(chan)->context_detach = nv40_fifo_context_detach;
 205         nv_parent(chan)->object_attach = nv40_fifo_object_attach;
 206         nv_parent(chan)->object_detach = nv04_fifo_object_detach;
 207         chan->ramfc = chan->base.chid * 128;
 208
 209         nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);
 210         nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset);
 211         nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
 212         nv_wo32(priv->ramfc, chan->ramfc + 0x18, 0x30000000 |
 213                              NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 214                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 215 #ifdef __BIG_ENDIAN
 216                              NV_PFIFO_CACHE1_BIG_ENDIAN |
 217 #endif
 218                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
 219         nv_wo32(priv->ramfc, chan->ramfc + 0x3c, 0x0001ffff);
 220         return 0;
 221 }
 222
 223 static struct nouveau_ofuncs
 224 nv40_fifo_ofuncs = {
 225         .ctor = nv40_fifo_chan_ctor,
 226         .dtor = nv04_fifo_chan_dtor,
 227         .init = nv04_fifo_chan_init,
 228         .fini = nv04_fifo_chan_fini,
 229         .rd32 = _nouveau_fifo_channel_rd32,
 230         .wr32 = _nouveau_fifo_channel_wr32,
 231 };
 232
 233 static struct nouveau_oclass
 234 nv40_fifo_sclass[] = {
 235         { NV40_CHANNEL_DMA_CLASS, &nv40_fifo_ofuncs },
 236         {}
 237 };
 238
 239 /*******************************************************************************
 240  * FIFO context - basically just the instmem reserved for the channel
 241  ******************************************************************************/
 242
 243 static struct nouveau_oclass
 244 nv40_fifo_cclass = {
 245         .handle = NV_ENGCTX(FIFO, 0x40),
 246         .ofuncs = &(struct nouveau_ofuncs) {
 247                 .ctor = nv04_fifo_context_ctor,
 248                 .dtor = _nouveau_fifo_context_dtor,
 249                 .init = _nouveau_fifo_context_init,
 250                 .fini = _nouveau_fifo_context_fini,
 251                 .rd32 = _nouveau_fifo_context_rd32,
 252                 .wr32 = _nouveau_fifo_context_wr32,
 253         },
 254 };
 255
 256 /*******************************************************************************
 257  * PFIFO engine
 258  ******************************************************************************/
 259
 260 static int
 261 nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 262                struct nouveau_oclass *oclass, void *data, u32 size,
 263                struct nouveau_object **pobject)
 264 {
 265         struct nv04_instmem_priv *imem = nv04_instmem(parent);
 266         struct nv04_fifo_priv *priv;
 267         int ret;
 268
 269         ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
 270         *pobject = nv_object(priv);
 271         if (ret)
 272                 return ret;
 273
 274         nouveau_ramht_ref(imem->ramht, &priv->ramht);
 275         nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
 276         nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
 277
 278         nv_subdev(priv)->unit = 0x00000100;
 279         nv_subdev(priv)->intr = nv04_fifo_intr;
 280         nv_engine(priv)->cclass = &nv40_fifo_cclass;
 281         nv_engine(priv)->sclass = nv40_fifo_sclass;
 282         priv->base.pause = nv04_fifo_pause;
 283         priv->base.start = nv04_fifo_start;
 284         priv->ramfc_desc = nv40_ramfc;
 285         return 0;
 286 }
 287
 288 static int
 289 nv40_fifo_init(struct nouveau_object *object)
 290 {
 291         struct nv04_fifo_priv *priv = (void *)object;
 292         struct nouveau_fb *pfb = nouveau_fb(object);
 293         int ret;
 294
 295         ret = nouveau_fifo_init(&priv->base);
 296         if (ret)
 297                 return ret;
 298
 299         nv_wr32(priv, 0x002040, 0x000000ff);
 300         nv_wr32(priv, 0x002044, 0x2101ffff);
 301         nv_wr32(priv, 0x002058, 0x00000001);
 302
 303         nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 304                                        ((priv->ramht->bits - 9) << 16) |
 305                                         (priv->ramht->base.addr >> 8));
 306         nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
 307
 308         switch (nv_device(priv)->chipset) {
 309         case 0x47:
 310         case 0x49:
 311         case 0x4b:
 312                 nv_wr32(priv, 0x002230, 0x00000001);
 313         case 0x40:
 314         case 0x41:
 315         case 0x42:
 316         case 0x43:
 317         case 0x45:
 318         case 0x48:
 319                 nv_wr32(priv, 0x002220, 0x00030002);
 320                 break;
 321         default:
 322                 nv_wr32(priv, 0x002230, 0x00000000);
 323                 nv_wr32(priv, 0x002220, ((pfb->ram.size - 512 * 1024 +
 324                                          priv->ramfc->addr) >> 16) |
 325                                         0x00030000);
 326                 break;
 327         }
 328
 329         nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
 330
 331         nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
 332         nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff);
 333
 334         nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
 335         nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
 336         nv_wr32(priv, NV03_PFIFO_CACHES, 1);
 337         return 0;
 338 }
 339
 340 struct nouveau_oclass
 341 nv40_fifo_oclass = {
 342         .handle = NV_ENGINE(FIFO, 0x40),
 343         .ofuncs = &(struct nouveau_ofuncs) {
 344                 .ctor = nv40_fifo_ctor,
 345                 .dtor = nv04_fifo_dtor,
 346                 .init = nv40_fifo_init,
 347                 .fini = _nouveau_fifo_fini,
 348         },
 349 };