drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/device.h>
  26 #include <core/gpuobj.h>
  27 #include <core/class.h>
  28
  29 #include <subdev/fb.h>
  30 #include <engine/dmaobj.h>
  31
  32 struct nvd0_dmaeng_priv {
  33         struct nouveau_dmaeng base;
  34 };
  35
  36 static int
  37 nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
  38                  struct nouveau_object *parent,
  39                  struct nouveau_dmaobj *dmaobj,
  40                  struct nouveau_gpuobj **pgpuobj)
  41 {
  42         u32 flags0 = 0x00000000;
  43         int ret;
  44
  45         if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
  46                 switch (nv_mclass(parent->parent)) {
  47                 case NVD0_DISP_MAST_CLASS:
  48                 case NVD0_DISP_SYNC_CLASS:
  49                 case NVD0_DISP_OVLY_CLASS:
  50                 case NVE0_DISP_MAST_CLASS:
  51                 case NVE0_DISP_SYNC_CLASS:
  52                 case NVE0_DISP_OVLY_CLASS:
  53                 case NVF0_DISP_MAST_CLASS:
  54                 case NVF0_DISP_SYNC_CLASS:
  55                 case NVF0_DISP_OVLY_CLASS:
  56                         break;
  57                 default:
  58                         return -EINVAL;
  59                 }
  60         } else
  61                 return 0;
  62
  63         if (!(dmaobj->conf0 & NVD0_DMA_CONF0_ENABLE)) {
  64                 if (dmaobj->target == NV_MEM_TARGET_VM) {
  65                         dmaobj->conf0 |= NVD0_DMA_CONF0_TYPE_VM;
  66                         dmaobj->conf0 |= NVD0_DMA_CONF0_PAGE_LP;
  67                 } else {
  68                         dmaobj->conf0 |= NVD0_DMA_CONF0_TYPE_LINEAR;
  69                         dmaobj->conf0 |= NVD0_DMA_CONF0_PAGE_SP;
  70                 }
  71         }
  72
  73         flags0 |= (dmaobj->conf0 & NVD0_DMA_CONF0_TYPE) << 20;
  74         flags0 |= (dmaobj->conf0 & NVD0_DMA_CONF0_PAGE) >> 4;
  75
  76         switch (dmaobj->target) {
  77         case NV_MEM_TARGET_VRAM:
  78                 flags0 |= 0x00000009;
  79                 break;
  80         default:
  81                 return -EINVAL;
  82                 break;
  83         }
  84
  85         ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
  86         if (ret == 0) {
  87                 nv_wo32(*pgpuobj, 0x00, flags0);
  88                 nv_wo32(*pgpuobj, 0x04, dmaobj->start >> 8);
  89                 nv_wo32(*pgpuobj, 0x08, dmaobj->limit >> 8);
  90                 nv_wo32(*pgpuobj, 0x0c, 0x00000000);
  91                 nv_wo32(*pgpuobj, 0x10, 0x00000000);
  92                 nv_wo32(*pgpuobj, 0x14, 0x00000000);
  93         }
  94
  95         return ret;
  96 }
  97
  98 static int
  99 nvd0_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 100                  struct nouveau_oclass *oclass, void *data, u32 size,
 101                  struct nouveau_object **pobject)
 102 {
 103         struct nvd0_dmaeng_priv *priv;
 104         int ret;
 105
 106         ret = nouveau_dmaeng_create(parent, engine, oclass, &priv);
 107         *pobject = nv_object(priv);
 108         if (ret)
 109                 return ret;
 110
 111         nv_engine(priv)->sclass = nouveau_dmaobj_sclass;
 112         priv->base.bind = nvd0_dmaobj_bind;
 113         return 0;
 114 }
 115
 116 struct nouveau_oclass
 117 nvd0_dmaeng_oclass = {
 118         .handle = NV_ENGINE(DMAOBJ, 0xd0),
 119         .ofuncs = &(struct nouveau_ofuncs) {
 120                 .ctor = nvd0_dmaeng_ctor,
 121                 .dtor = _nouveau_dmaeng_dtor,
 122                 .init = _nouveau_dmaeng_init,
 123                 .fini = _nouveau_dmaeng_fini,
 124         },
 125 };