drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/gpuobj.h>
  26 #include <core/class.h>
  27
  28 #include <subdev/fb.h>
  29
  30 #include "priv.h"
  31
  32 struct nv50_dmaobj_priv {
  33         struct nouveau_dmaobj base;
  34         u32 flags0;
  35         u32 flags5;
  36 };
  37
  38 static int
  39 nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
  40                  struct nouveau_object *parent,
  41                  struct nouveau_gpuobj **pgpuobj)
  42 {
  43         struct nv50_dmaobj_priv *priv = (void *)dmaobj;
  44         int ret;
  45
  46         if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
  47                 switch (nv_mclass(parent->parent)) {
  48                 case NV50_CHANNEL_DMA_CLASS:
  49                 case NV84_CHANNEL_DMA_CLASS:
  50                 case NV50_CHANNEL_IND_CLASS:
  51                 case NV84_CHANNEL_IND_CLASS:
  52                 case NV50_DISP_MAST_CLASS:
  53                 case NV84_DISP_MAST_CLASS:
  54                 case NV94_DISP_MAST_CLASS:
  55                 case NVA0_DISP_MAST_CLASS:
  56                 case NVA3_DISP_MAST_CLASS:
  57                 case NV50_DISP_SYNC_CLASS:
  58                 case NV84_DISP_SYNC_CLASS:
  59                 case NV94_DISP_SYNC_CLASS:
  60                 case NVA0_DISP_SYNC_CLASS:
  61                 case NVA3_DISP_SYNC_CLASS:
  62                 case NV50_DISP_OVLY_CLASS:
  63                 case NV84_DISP_OVLY_CLASS:
  64                 case NV94_DISP_OVLY_CLASS:
  65                 case NVA0_DISP_OVLY_CLASS:
  66                 case NVA3_DISP_OVLY_CLASS:
  67                         break;
  68                 default:
  69                         return -EINVAL;
  70                 }
  71         }
  72
  73         ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
  74         if (ret == 0) {
  75                 nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
  76                 nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
  77                 nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start));
  78                 nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 |
  79                                         upper_32_bits(priv->base.start));
  80                 nv_wo32(*pgpuobj, 0x10, 0x00000000);
  81                 nv_wo32(*pgpuobj, 0x14, priv->flags5);
  82         }
  83
  84         return ret;
  85 }
  86
  87 static int
  88 nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
  89                  struct nouveau_oclass *oclass, void *data, u32 size,
  90                  struct nouveau_object **pobject)
  91 {
  92         struct nouveau_dmaeng *dmaeng = (void *)engine;
  93         struct nv50_dmaobj_priv *priv;
  94         union {
  95                 u32 conf0;
  96         } *args;
  97         int ret;
  98
  99         ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
 100         *pobject = nv_object(priv);
 101         if (ret)
 102                 return ret;
 103         args = data;
 104
 105         if (!(args->conf0 & NV50_DMA_CONF0_ENABLE)) {
 106                 if (priv->base.target == NV_MEM_TARGET_VM) {
 107                         args->conf0  = NV50_DMA_CONF0_PRIV_VM;
 108                         args->conf0 |= NV50_DMA_CONF0_PART_VM;
 109                         args->conf0 |= NV50_DMA_CONF0_COMP_VM;
 110                         args->conf0 |= NV50_DMA_CONF0_TYPE_VM;
 111                 } else {
 112                         args->conf0  = NV50_DMA_CONF0_PRIV_US;
 113                         args->conf0 |= NV50_DMA_CONF0_PART_256;
 114                         args->conf0 |= NV50_DMA_CONF0_COMP_NONE;
 115                         args->conf0 |= NV50_DMA_CONF0_TYPE_LINEAR;
 116                 }
 117         }
 118
 119         priv->flags0 |= (args->conf0 & NV50_DMA_CONF0_COMP) << 22;
 120         priv->flags0 |= (args->conf0 & NV50_DMA_CONF0_TYPE) << 22;
 121         priv->flags0 |= (args->conf0 & NV50_DMA_CONF0_PRIV);
 122         priv->flags5 |= (args->conf0 & NV50_DMA_CONF0_PART);
 123
 124         switch (priv->base.target) {
 125         case NV_MEM_TARGET_VM:
 126                 priv->flags0 |= 0x00000000;
 127                 break;
 128         case NV_MEM_TARGET_VRAM:
 129                 priv->flags0 |= 0x00010000;
 130                 break;
 131         case NV_MEM_TARGET_PCI:
 132                 priv->flags0 |= 0x00020000;
 133                 break;
 134         case NV_MEM_TARGET_PCI_NOSNOOP:
 135                 priv->flags0 |= 0x00030000;
 136                 break;
 137         default:
 138                 return -EINVAL;
 139         }
 140
 141         switch (priv->base.access) {
 142         case NV_MEM_ACCESS_VM:
 143                 break;
 144         case NV_MEM_ACCESS_RO:
 145                 priv->flags0 |= 0x00040000;
 146                 break;
 147         case NV_MEM_ACCESS_WO:
 148         case NV_MEM_ACCESS_RW:
 149                 priv->flags0 |= 0x00080000;
 150                 break;
 151         default:
 152                 return -EINVAL;
 153         }
 154
 155         return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
 156 }
 157
 158 static struct nouveau_ofuncs
 159 nv50_dmaobj_ofuncs = {
 160         .ctor =  nv50_dmaobj_ctor,
 161         .dtor = _nvkm_dmaobj_dtor,
 162         .init = _nvkm_dmaobj_init,
 163         .fini = _nvkm_dmaobj_fini,
 164 };
 165
 166 static struct nouveau_oclass
 167 nv50_dmaeng_sclass[] = {
 168         { NV_DMA_FROM_MEMORY_CLASS, &nv50_dmaobj_ofuncs },
 169         { NV_DMA_TO_MEMORY_CLASS, &nv50_dmaobj_ofuncs },
 170         { NV_DMA_IN_MEMORY_CLASS, &nv50_dmaobj_ofuncs },
 171         {}
 172 };
 173
 174 struct nouveau_oclass *
 175 nv50_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
 176         .base.handle = NV_ENGINE(DMAOBJ, 0x50),
 177         .base.ofuncs = &(struct nouveau_ofuncs) {
 178                 .ctor = _nvkm_dmaeng_ctor,
 179                 .dtor = _nvkm_dmaeng_dtor,
 180                 .init = _nvkm_dmaeng_init,
 181                 .fini = _nvkm_dmaeng_fini,
 182         },
 183         .sclass = nv50_dmaeng_sclass,
 184         .bind = nv50_dmaobj_bind,
 185 }.base;