drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <engine/software.h>
  26 #include <engine/disp.h>
  27
  28 struct nv50_disp_priv {
  29         struct nouveau_disp base;
  30 };
  31
  32 static struct nouveau_oclass
  33 nv50_disp_sclass[] = {
  34         {},
  35 };
  36
  37 static void
  38 nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
  39 {
  40         struct nouveau_disp *disp = &priv->base;
  41         struct nouveau_software_chan *chan, *temp;
  42         unsigned long flags;
  43
  44         spin_lock_irqsave(&disp->vblank.lock, flags);
  45         list_for_each_entry_safe(chan, temp, &disp->vblank.list, vblank.head) {
  46                 if (chan->vblank.crtc != crtc)
  47                         continue;
  48
  49                 nv_wr32(priv, 0x001704, chan->vblank.channel);
  50                 nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
  51
  52                 if (nv_device(priv)->chipset == 0x50) {
  53                         nv_wr32(priv, 0x001570, chan->vblank.offset);
  54                         nv_wr32(priv, 0x001574, chan->vblank.value);
  55                 } else {
  56                         if (nv_device(priv)->chipset >= 0xc0) {
  57                                 nv_wr32(priv, 0x06000c,
  58                                         upper_32_bits(chan->vblank.offset));
  59                         }
  60                         nv_wr32(priv, 0x060010, chan->vblank.offset);
  61                         nv_wr32(priv, 0x060014, chan->vblank.value);
  62                 }
  63
  64                 list_del(&chan->vblank.head);
  65                 if (disp->vblank.put)
  66                         disp->vblank.put(disp->vblank.data, crtc);
  67         }
  68         spin_unlock_irqrestore(&disp->vblank.lock, flags);
  69
  70         if (disp->vblank.notify)
  71                 disp->vblank.notify(disp->vblank.data, crtc);
  72 }
  73
  74 static void
  75 nv50_disp_intr(struct nouveau_subdev *subdev)
  76 {
  77         struct nv50_disp_priv *priv = (void *)subdev;
  78         u32 stat1 = nv_rd32(priv, 0x610024);
  79
  80         if (stat1 & 0x00000004) {
  81                 nv50_disp_intr_vblank(priv, 0);
  82                 nv_wr32(priv, 0x610024, 0x00000004);
  83                 stat1 &= ~0x00000004;
  84         }
  85
  86         if (stat1 & 0x00000008) {
  87                 nv50_disp_intr_vblank(priv, 1);
  88                 nv_wr32(priv, 0x610024, 0x00000008);
  89                 stat1 &= ~0x00000008;
  90         }
  91
  92 }
  93
  94 static int
  95 nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
  96                   struct nouveau_oclass *oclass, void *data, u32 size,
  97                   struct nouveau_object **pobject)
  98 {
  99         struct nv50_disp_priv *priv;
 100         int ret;
 101
 102         ret = nouveau_disp_create(parent, engine, oclass, "PDISP",
 103                                   "display", &priv);
 104         *pobject = nv_object(priv);
 105         if (ret)
 106                 return ret;
 107
 108         nv_engine(priv)->sclass = nv50_disp_sclass;
 109         nv_subdev(priv)->intr = nv50_disp_intr;
 110
 111         INIT_LIST_HEAD(&priv->base.vblank.list);
 112         spin_lock_init(&priv->base.vblank.lock);
 113         return 0;
 114 }
 115
 116 struct nouveau_oclass
 117 nv50_disp_oclass = {
 118         .handle = NV_ENGINE(DISP, 0x50),
 119         .ofuncs = &(struct nouveau_ofuncs) {
 120                 .ctor = nv50_disp_ctor,
 121                 .dtor = _nouveau_disp_dtor,
 122                 .init = _nouveau_disp_init,
 123                 .fini = _nouveau_disp_fini,
 124         },
 125 };