drivers/gpu/drm/nouveau/core/engine/device/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/bios.h>
  26 #include <subdev/bus.h>
  27 #include <subdev/gpio.h>
  28 #include <subdev/i2c.h>
  29 #include <subdev/clock.h>
  30 #include <subdev/therm.h>
  31 #include <subdev/mxm.h>
  32 #include <subdev/devinit.h>
  33 #include <subdev/mc.h>
  34 #include <subdev/timer.h>
  35 #include <subdev/fb.h>
  36 #include <subdev/instmem.h>
  37 #include <subdev/vm.h>
  38 #include <subdev/bar.h>
  39 #include <subdev/pwr.h>
  40
  41 #include <engine/device.h>
  42 #include <engine/dmaobj.h>
  43 #include <engine/fifo.h>
  44 #include <engine/software.h>
  45 #include <engine/graph.h>
  46 #include <engine/mpeg.h>
  47 #include <engine/vp.h>
  48 #include <engine/crypt.h>
  49 #include <engine/bsp.h>
  50 #include <engine/ppp.h>
  51 #include <engine/copy.h>
  52 #include <engine/disp.h>
  53
  54 int
  55 nv50_identify(struct nouveau_device *device)
  56 {
  57         switch (device->chipset) {
  58         case 0x50:
  59                 device->cname = "G80";
  60                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  61                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  62                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv50_i2c_oclass;
  63                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
  64                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv50_therm_oclass;
  65                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
  66                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  67                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
  68                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
  69                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  70                 device->oclass[NVDEV_SUBDEV_FB     ] =  nv50_fb_oclass;
  71                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
  72                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
  73                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
  74                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
  75                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv50_fifo_oclass;
  76                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
  77                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
  78                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv50_mpeg_oclass;
  79                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
  80                 break;
  81         case 0x84:
  82                 device->cname = "G84";
  83                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  84                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  85                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv50_i2c_oclass;
  86                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
  87                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
  88                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
  89                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  90                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
  91                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
  92                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  93                 device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
  94                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
  95                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
  96                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
  97                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
  98                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
  99                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 100                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 101                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 102                 device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 103                 device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
 104                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
 105                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv84_disp_oclass;
 106                 break;
 107         case 0x86:
 108                 device->cname = "G86";
 109                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 110                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 111                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv50_i2c_oclass;
 112                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
 113                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
 114                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 115                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 116                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
 117                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
 118                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 119                 device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 120                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 121                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
 122                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 123                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
 124                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 125                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 126                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 127                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 128                 device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 129                 device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
 130                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
 131                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv84_disp_oclass;
 132                 break;
 133         case 0x92:
 134                 device->cname = "G92";
 135                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 136                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 137                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv50_i2c_oclass;
 138                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
 139                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
 140                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 141                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 142                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
 143                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
 144                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 145                 device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 146                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 147                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
 148                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 149                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
 150                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 151                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 152                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 153                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 154                 device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 155                 device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
 156                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
 157                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv84_disp_oclass;
 158                 break;
 159         case 0x94:
 160                 device->cname = "G94";
 161                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 162                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 163                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 164                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
 165                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
 166                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 167                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 168                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv94_mc_oclass;
 169                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
 170                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 171                 device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 172                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 173                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
 174                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 175                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
 176                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 177                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 178                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 179                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 180                 device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 181                 device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
 182                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
 183                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
 184                 break;
 185         case 0x96:
 186                 device->cname = "G96";
 187                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 188                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 189                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 190                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
 191                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
 192                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 193                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 194                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv94_mc_oclass;
 195                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
 196                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 197                 device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 198                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 199                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
 200                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 201                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
 202                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 203                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 204                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 205                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 206                 device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 207                 device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
 208                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
 209                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
 210                 break;
 211         case 0x98:
 212                 device->cname = "G98";
 213                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 214                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 215                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 216                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
 217                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
 218                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 219                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 220                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
 221                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
 222                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 223                 device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 224                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 225                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
 226                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 227                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
 228                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 229                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 230                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 231                 device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 232                 device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
 233                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
 234                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
 235                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
 236                 break;
 237         case 0xa0:
 238                 device->cname = "G200";
 239                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 240                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 241                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv50_i2c_oclass;
 242                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
 243                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
 244                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 245                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 246                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
 247                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
 248                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 249                 device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
 250                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 251                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
 252                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 253                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
 254                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 255                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 256                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 257                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 258                 device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 259                 device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
 260                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
 261                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva0_disp_oclass;
 262                 break;
 263         case 0xaa:
 264                 device->cname = "MCP77/MCP78";
 265                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 266                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 267                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 268                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
 269                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
 270                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 271                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 272                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
 273                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
 274                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 275                 device->oclass[NVDEV_SUBDEV_FB     ] =  nvaa_fb_oclass;
 276                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 277                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
 278                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 279                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
 280                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 281                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 282                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 283                 device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 284                 device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
 285                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
 286                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
 287                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
 288                 break;
 289         case 0xac:
 290                 device->cname = "MCP79/MCP7A";
 291                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 292                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 293                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 294                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv50_clock_oclass;
 295                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
 296                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 297                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 298                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
 299                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
 300                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 301                 device->oclass[NVDEV_SUBDEV_FB     ] =  nvaa_fb_oclass;
 302                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 303                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
 304                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 305                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
 306                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 307                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 308                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 309                 device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 310                 device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
 311                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
 312                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
 313                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
 314                 break;
 315         case 0xa3:
 316                 device->cname = "GT215";
 317                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 318                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 319                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 320                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
 321                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
 322                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 323                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
 324                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
 325                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
 326                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 327                 device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
 328                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 329                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
 330                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 331                 device->oclass[NVDEV_SUBDEV_PWR    ] = &nva3_pwr_oclass;
 332                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
 333                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 334                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 335                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 336                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 337                 device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 338                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
 339                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
 340                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
 341                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
 342                 break;
 343         case 0xa5:
 344                 device->cname = "GT216";
 345                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 346                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 347                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 348                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
 349                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
 350                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 351                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
 352                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
 353                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
 354                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 355                 device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
 356                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 357                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
 358                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 359                 device->oclass[NVDEV_SUBDEV_PWR    ] = &nva3_pwr_oclass;
 360                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
 361                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 362                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 363                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 364                 device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 365                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
 366                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
 367                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
 368                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
 369                 break;
 370         case 0xa8:
 371                 device->cname = "GT218";
 372                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 373                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 374                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 375                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
 376                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
 377                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 378                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
 379                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
 380                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
 381                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 382                 device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
 383                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 384                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
 385                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 386                 device->oclass[NVDEV_SUBDEV_PWR    ] = &nva3_pwr_oclass;
 387                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
 388                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 389                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 390                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 391                 device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 392                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
 393                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
 394                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
 395                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
 396                 break;
 397         case 0xaf:
 398                 device->cname = "MCP89";
 399                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 400                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 401                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 402                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
 403                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
 404                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 405                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
 406                 device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
 407                 device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
 408                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 409                 device->oclass[NVDEV_SUBDEV_FB     ] =  nvaf_fb_oclass;
 410                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 411                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
 412                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
 413                 device->oclass[NVDEV_SUBDEV_PWR    ] = &nva3_pwr_oclass;
 414                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
 415                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 416                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
 417                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
 418                 device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 419                 device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
 420                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
 421                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
 422                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
 423                 break;
 424         default:
 425                 nv_fatal(device, "unknown Tesla chipset\n");
 426                 return -EINVAL;
 427         }
 428
 429         return 0;
 430 }