2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/clk.h>
22 #include <linux/regulator/consumer.h>
25 #include "msm_fence.h"
26 #include "msm_ringbuffer.h"
28 struct msm_gem_submit;
29 struct msm_gpu_perfcntr;
31 /* So far, with hardware that I've seen to date, we can have:
32 * + zero, one, or two z180 2d cores
33 * + a3xx or a2xx 3d core, which share a common CP (the firmware
34 * for the CP seems to implement some different PM4 packet types
35 * but the basics of cmdstream submission are the same)
37 * Which means that the eventual complete "class" hierarchy, once
38 * support for all past and present hw is in place, becomes:
45 struct msm_gpu_funcs {
46 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
47 int (*hw_init)(struct msm_gpu *gpu);
48 int (*pm_suspend)(struct msm_gpu *gpu);
49 int (*pm_resume)(struct msm_gpu *gpu);
50 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
51 struct msm_file_private *ctx);
52 void (*flush)(struct msm_gpu *gpu);
53 bool (*idle)(struct msm_gpu *gpu);
54 irqreturn_t (*irq)(struct msm_gpu *irq);
55 uint32_t (*last_fence)(struct msm_gpu *gpu);
56 void (*recover)(struct msm_gpu *gpu);
57 void (*destroy)(struct msm_gpu *gpu);
58 #ifdef CONFIG_DEBUG_FS
59 /* show GPU status in debugfs: */
60 void (*show)(struct msm_gpu *gpu, struct seq_file *m);
66 struct drm_device *dev;
67 struct platform_device *pdev;
68 const struct msm_gpu_funcs *funcs;
70 /* performance counters (hw & sw): */
77 uint32_t totaltime, activetime; /* sw counters */
78 uint32_t last_cntrs[5]; /* hw counters */
79 const struct msm_gpu_perfcntr *perfcntrs;
80 uint32_t num_perfcntrs;
83 struct msm_ringbuffer *rb;
86 /* list of GEM active objects: */
87 struct list_head active_list;
90 struct msm_fence_context *fctx;
92 /* does gpu need hw_init? */
95 /* worker for handling active-list retiring: */
96 struct work_struct retire_work;
101 struct msm_gem_address_space *aspace;
105 struct regulator *gpu_reg, *gpu_cx;
106 struct clk **grp_clks;
108 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
109 uint32_t fast_rate, bus_freq;
111 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
112 struct msm_bus_scale_pdata *bus_scale_table;
116 /* Hang and Inactivity Detection:
118 #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
120 #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
121 #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
122 struct timer_list hangcheck_timer;
123 uint32_t hangcheck_fence;
124 struct work_struct recover_work;
126 struct list_head submit_list;
129 static inline bool msm_gpu_active(struct msm_gpu *gpu)
131 return gpu->fctx->last_fence > gpu->funcs->last_fence(gpu);
135 * The select_reg and select_val are just there for the benefit of the child
136 * class that actually enables the perf counter.. but msm_gpu base class
137 * will handle sampling/displaying the counters.
140 struct msm_gpu_perfcntr {
147 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
149 msm_writel(data, gpu->mmio + (reg << 2));
152 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
154 return msm_readl(gpu->mmio + (reg << 2));
157 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
159 uint32_t val = gpu_read(gpu, reg);
162 gpu_write(gpu, reg, val | or);
165 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
170 * Why not a readq here? Two reasons: 1) many of the LO registers are
171 * not quad word aligned and 2) the GPU hardware designers have a bit
172 * of a history of putting registers where they fit, especially in
173 * spins. The longer a GPU family goes the higher the chance that
174 * we'll get burned. We could do a series of validity checks if we
175 * wanted to, but really is a readq() that much better? Nah.
179 * For some lo/hi registers (like perfcounters), the hi value is latched
180 * when the lo is read, so make sure to read the lo first to trigger
183 val = (u64) msm_readl(gpu->mmio + (lo << 2));
184 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
189 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
191 /* Why not a writeq here? Read the screed above */
192 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
193 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
196 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
197 int msm_gpu_pm_resume(struct msm_gpu *gpu);
199 int msm_gpu_hw_init(struct msm_gpu *gpu);
201 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
202 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
203 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
204 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
206 void msm_gpu_retire(struct msm_gpu *gpu);
207 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
208 struct msm_file_private *ctx);
210 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
211 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
212 const char *name, const char *ioname, const char *irqname, int ringsz);
213 void msm_gpu_cleanup(struct msm_gpu *gpu);
215 struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
216 void __init adreno_register(void);
217 void __exit adreno_unregister(void);
219 #endif /* __MSM_GPU_H__ */