1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
10 #include <linux/adreno-smmu-priv.h>
11 #include <linux/clk.h>
12 #include <linux/devfreq.h>
13 #include <linux/interconnect.h>
14 #include <linux/pm_opp.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/reset.h>
19 #include "msm_fence.h"
20 #include "msm_ringbuffer.h"
23 struct msm_gem_submit;
24 struct msm_gpu_perfcntr;
26 struct msm_file_private;
28 struct msm_gpu_config {
30 unsigned int nr_rings;
33 /* So far, with hardware that I've seen to date, we can have:
34 * + zero, one, or two z180 2d cores
35 * + a3xx or a2xx 3d core, which share a common CP (the firmware
36 * for the CP seems to implement some different PM4 packet types
37 * but the basics of cmdstream submission are the same)
39 * Which means that the eventual complete "class" hierarchy, once
40 * support for all past and present hw is in place, becomes:
47 struct msm_gpu_funcs {
48 int (*get_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
49 uint32_t param, uint64_t *value, uint32_t *len);
50 int (*set_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
51 uint32_t param, uint64_t value, uint32_t len);
52 int (*hw_init)(struct msm_gpu *gpu);
53 int (*pm_suspend)(struct msm_gpu *gpu);
54 int (*pm_resume)(struct msm_gpu *gpu);
55 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
56 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
57 irqreturn_t (*irq)(struct msm_gpu *irq);
58 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
59 void (*recover)(struct msm_gpu *gpu);
60 void (*destroy)(struct msm_gpu *gpu);
61 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
62 /* show GPU status in debugfs: */
63 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
64 struct drm_printer *p);
65 /* for generation specific debugfs: */
66 void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
68 /* note: gpu_busy() can assume that we have been pm_resumed */
69 u64 (*gpu_busy)(struct msm_gpu *gpu, unsigned long *out_sample_rate);
70 struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
71 int (*gpu_state_put)(struct msm_gpu_state *state);
72 unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
73 /* note: gpu_set_freq() can assume that we have been pm_resumed */
74 void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
76 struct msm_gem_address_space *(*create_address_space)
77 (struct msm_gpu *gpu, struct platform_device *pdev);
78 struct msm_gem_address_space *(*create_private_address_space)
79 (struct msm_gpu *gpu);
80 uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
83 /* Additional state for iommu faults: */
84 struct msm_gpu_fault_info {
93 * struct msm_gpu_devfreq - devfreq related state
95 struct msm_gpu_devfreq {
96 /** devfreq: devfreq instance */
97 struct devfreq *devfreq;
99 /** lock: lock for "suspended", "busy_cycles", and "time" */
105 * A PM QoS constraint to limit max freq while the GPU is idle.
107 struct dev_pm_qos_request idle_freq;
112 * A PM QoS constraint to boost min freq for a period of time
113 * until the boost expires.
115 struct dev_pm_qos_request boost_freq;
118 * busy_cycles: Last busy counter value, for calculating elapsed busy
119 * cycles since last sampling period.
123 /** time: Time of last sampling period. */
126 /** idle_time: Time of last transition to idle: */
129 struct devfreq_dev_status average_status;
134 * Used to delay clamping to idle freq on active->idle transition.
136 struct msm_hrtimer_work idle_work;
141 * Used to reset the boost_constraint after the boost period has
144 struct msm_hrtimer_work boost_work;
146 /** suspended: tracks if we're suspended */
152 struct drm_device *dev;
153 struct platform_device *pdev;
154 const struct msm_gpu_funcs *funcs;
156 struct adreno_smmu_priv adreno_smmu;
158 /* performance counters (hw & sw): */
159 spinlock_t perf_lock;
160 bool perfcntr_active;
165 uint32_t totaltime, activetime; /* sw counters */
166 uint32_t last_cntrs[5]; /* hw counters */
167 const struct msm_gpu_perfcntr *perfcntrs;
168 uint32_t num_perfcntrs;
170 struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
176 * The count of contexts that have enabled system profiling.
178 refcount_t sysprof_active;
183 * The ctx->seqno value of the last context to submit rendering,
184 * and the one with current pgtables installed (for generations
185 * that support per-context pgtables). Tracked by seqno rather
186 * than pointer value to avoid dangling pointers, and cases where
187 * a ctx can be freed and a new one created with the same address.
194 * General lock for serializing all the gpu things.
196 * TODO move to per-ring locking where feasible (ie. submit/retire
204 * The number of submitted but not yet retired submits, used to
205 * determine transitions between active and idle.
207 * Protected by active_lock
211 /** lock: protects active_submits and idle/active transitions */
212 struct mutex active_lock;
214 /* does gpu need hw_init? */
218 * global_faults: number of GPU hangs not attributed to a particular
226 struct msm_gem_address_space *aspace;
229 struct regulator *gpu_reg, *gpu_cx;
230 struct clk_bulk_data *grp_clks;
232 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
235 /* Hang and Inactivity Detection:
237 #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
239 #define DRM_MSM_HANGCHECK_DEFAULT_PERIOD 500 /* in ms */
240 struct timer_list hangcheck_timer;
242 /* Fault info for most recent iova fault: */
243 struct msm_gpu_fault_info fault_info;
245 /* work for handling GPU ioval faults: */
246 struct kthread_work fault_work;
248 /* work for handling GPU recovery: */
249 struct kthread_work recover_work;
251 /** retire_event: notified when submits are retired: */
252 wait_queue_head_t retire_event;
254 /* work for handling active-list retiring: */
255 struct kthread_work retire_work;
257 /* worker for retire/recover: */
258 struct kthread_worker *worker;
260 struct drm_gem_object *memptrs_bo;
262 struct msm_gpu_devfreq devfreq;
264 uint32_t suspend_count;
266 struct msm_gpu_state *crashstate;
268 /* Enable clamping to idle freq when inactive: */
271 /* True if the hardware supports expanded apriv (a650 and newer) */
274 struct thermal_cooling_device *cooling;
276 /* To poll for cx gdsc collapse during gpu recovery */
277 struct reset_control *cx_collapse;
280 static inline struct msm_gpu *dev_to_gpu(struct device *dev)
282 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
283 return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);
286 /* It turns out that all targets use the same ringbuffer size */
287 #define MSM_GPU_RINGBUFFER_SZ SZ_32K
288 #define MSM_GPU_RINGBUFFER_BLKSIZE 32
290 #define MSM_GPU_RB_CNTL_DEFAULT \
291 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
292 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
294 static inline bool msm_gpu_active(struct msm_gpu *gpu)
298 for (i = 0; i < gpu->nr_rings; i++) {
299 struct msm_ringbuffer *ring = gpu->rb[i];
301 if (fence_after(ring->fctx->last_fence, ring->memptrs->fence))
309 * The select_reg and select_val are just there for the benefit of the child
310 * class that actually enables the perf counter.. but msm_gpu base class
311 * will handle sampling/displaying the counters.
314 struct msm_gpu_perfcntr {
322 * The number of priority levels provided by drm gpu scheduler. The
323 * DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some
324 * cases, so we don't use it (no need for kernel generated jobs).
326 #define NR_SCHED_PRIORITIES (1 + DRM_SCHED_PRIORITY_HIGH - DRM_SCHED_PRIORITY_MIN)
329 * struct msm_file_private - per-drm_file context
331 * @queuelock: synchronizes access to submitqueues list
332 * @submitqueues: list of &msm_gpu_submitqueue created by userspace
333 * @queueid: counter incremented each time a submitqueue is created,
334 * used to assign &msm_gpu_submitqueue.id
335 * @aspace: the per-process GPU address-space
336 * @ref: reference count
337 * @seqno: unique per process seqno
339 struct msm_file_private {
341 struct list_head submitqueues;
343 struct msm_gem_address_space *aspace;
350 * The value of MSM_PARAM_SYSPROF set by userspace. This is
351 * intended to be used by system profiling tools like Mesa's
352 * pps-producer (perfetto), and restricted to CAP_SYS_ADMIN.
354 * Setting a value of 1 will preserve performance counters across
355 * context switches. Setting a value of 2 will in addition
356 * suppress suspend. (Performance counters lose state across
357 * power collapse, which is undesirable for profiling in some
360 * The value automatically reverts to zero when the drm device
365 /** comm: Overridden task comm, see MSM_PARAM_COMM */
368 /** cmdline: Overridden task cmdline, see MSM_PARAM_CMDLINE */
374 * The total (cumulative) elapsed time GPU was busy with rendering
375 * from this context in ns.
382 * The total (cumulative) GPU cycles elapsed attributed to this
390 * Table of per-priority-level sched entities used by submitqueues
391 * associated with this &drm_file. Because some userspace apps
392 * make assumptions about rendering from multiple gl contexts
393 * (of the same priority) within the process happening in FIFO
394 * order without requiring any fencing beyond MakeCurrent(), we
395 * create at most one &drm_sched_entity per-process per-priority-
398 struct drm_sched_entity *entities[NR_SCHED_PRIORITIES * MSM_GPU_MAX_RINGS];
402 * msm_gpu_convert_priority - Map userspace priority to ring # and sched priority
404 * @gpu: the gpu instance
405 * @prio: the userspace priority level
406 * @ring_nr: [out] the ringbuffer the userspace priority maps to
407 * @sched_prio: [out] the gpu scheduler priority level which the userspace
410 * With drm/scheduler providing it's own level of prioritization, our total
411 * number of available priority levels is (nr_rings * NR_SCHED_PRIORITIES).
412 * Each ring is associated with it's own scheduler instance. However, our
413 * UABI is that lower numerical values are higher priority. So mapping the
414 * single userspace priority level into ring_nr and sched_prio takes some
415 * care. The userspace provided priority (when a submitqueue is created)
416 * is mapped to ring nr and scheduler priority as such:
418 * ring_nr = userspace_prio / NR_SCHED_PRIORITIES
419 * sched_prio = NR_SCHED_PRIORITIES -
420 * (userspace_prio % NR_SCHED_PRIORITIES) - 1
422 * This allows generations without preemption (nr_rings==1) to have some
423 * amount of prioritization, and provides more priority levels for gens
424 * that do have preemption.
426 static inline int msm_gpu_convert_priority(struct msm_gpu *gpu, int prio,
427 unsigned *ring_nr, enum drm_sched_priority *sched_prio)
431 rn = div_u64_rem(prio, NR_SCHED_PRIORITIES, &sp);
433 /* invert sched priority to map to higher-numeric-is-higher-
434 * priority convention
436 sp = NR_SCHED_PRIORITIES - sp - 1;
438 if (rn >= gpu->nr_rings)
448 * struct msm_gpu_submitqueues - Userspace created context.
450 * A submitqueue is associated with a gl context or vk queue (or equiv)
453 * @id: userspace id for the submitqueue, unique within the drm_file
454 * @flags: userspace flags for the submitqueue, specified at creation
455 * (currently unusued)
456 * @ring_nr: the ringbuffer used by this submitqueue, which is determined
457 * by the submitqueue's priority
458 * @faults: the number of GPU hangs associated with this submitqueue
459 * @last_fence: the sequence number of the last allocated fence (for error
461 * @ctx: the per-drm_file context associated with the submitqueue (ie.
462 * which set of pgtables do submits jobs associated with the
464 * @node: node in the context's list of submitqueues
465 * @fence_idr: maps fence-id to dma_fence for userspace visible fence
466 * seqno, protected by submitqueue lock
467 * @idr_lock: for serializing access to fence_idr
468 * @lock: submitqueue lock for serializing submits on a queue
469 * @ref: reference count
470 * @entity: the submit job-queue
472 struct msm_gpu_submitqueue {
478 struct msm_file_private *ctx;
479 struct list_head node;
480 struct idr fence_idr;
481 struct mutex idr_lock;
484 struct drm_sched_entity *entity;
487 struct msm_gpu_state_bo {
495 struct msm_gpu_state {
497 struct timespec64 time;
508 } ring[MSM_GPU_MAX_RINGS];
518 struct msm_gpu_fault_info fault_info;
521 struct msm_gpu_state_bo *bos;
524 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
526 msm_writel(data, gpu->mmio + (reg << 2));
529 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
531 return msm_readl(gpu->mmio + (reg << 2));
534 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
536 msm_rmw(gpu->mmio + (reg << 2), mask, or);
539 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
544 * Why not a readq here? Two reasons: 1) many of the LO registers are
545 * not quad word aligned and 2) the GPU hardware designers have a bit
546 * of a history of putting registers where they fit, especially in
547 * spins. The longer a GPU family goes the higher the chance that
548 * we'll get burned. We could do a series of validity checks if we
549 * wanted to, but really is a readq() that much better? Nah.
553 * For some lo/hi registers (like perfcounters), the hi value is latched
554 * when the lo is read, so make sure to read the lo first to trigger
557 val = (u64) msm_readl(gpu->mmio + (lo << 2));
558 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
563 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
565 /* Why not a writeq here? Read the screed above */
566 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
567 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
570 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
571 int msm_gpu_pm_resume(struct msm_gpu *gpu);
573 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
574 struct drm_printer *p);
576 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
577 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
579 int msm_submitqueue_create(struct drm_device *drm,
580 struct msm_file_private *ctx,
581 u32 prio, u32 flags, u32 *id);
582 int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
583 struct drm_msm_submitqueue_query *args);
584 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
585 void msm_submitqueue_close(struct msm_file_private *ctx);
587 void msm_submitqueue_destroy(struct kref *kref);
589 int msm_file_private_set_sysprof(struct msm_file_private *ctx,
590 struct msm_gpu *gpu, int sysprof);
591 void __msm_file_private_destroy(struct kref *kref);
593 static inline void msm_file_private_put(struct msm_file_private *ctx)
595 kref_put(&ctx->ref, __msm_file_private_destroy);
598 static inline struct msm_file_private *msm_file_private_get(
599 struct msm_file_private *ctx)
605 void msm_devfreq_init(struct msm_gpu *gpu);
606 void msm_devfreq_cleanup(struct msm_gpu *gpu);
607 void msm_devfreq_resume(struct msm_gpu *gpu);
608 void msm_devfreq_suspend(struct msm_gpu *gpu);
609 void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor);
610 void msm_devfreq_active(struct msm_gpu *gpu);
611 void msm_devfreq_idle(struct msm_gpu *gpu);
613 int msm_gpu_hw_init(struct msm_gpu *gpu);
615 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
616 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
617 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
618 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
620 void msm_gpu_retire(struct msm_gpu *gpu);
621 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
623 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
624 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
625 const char *name, struct msm_gpu_config *config);
627 struct msm_gem_address_space *
628 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
630 void msm_gpu_cleanup(struct msm_gpu *gpu);
632 struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
633 void __init adreno_register(void);
634 void __exit adreno_unregister(void);
636 static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
639 kref_put(&queue->ref, msm_submitqueue_destroy);
642 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
644 struct msm_gpu_state *state = NULL;
646 mutex_lock(&gpu->lock);
648 if (gpu->crashstate) {
649 kref_get(&gpu->crashstate->ref);
650 state = gpu->crashstate;
653 mutex_unlock(&gpu->lock);
658 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
660 mutex_lock(&gpu->lock);
662 if (gpu->crashstate) {
663 if (gpu->funcs->gpu_state_put(gpu->crashstate))
664 gpu->crashstate = NULL;
667 mutex_unlock(&gpu->lock);
671 * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
672 * support expanded privileges
674 #define check_apriv(gpu, flags) \
675 (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))
678 #endif /* __MSM_GPU_H__ */