1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/dma-mapping.h>
9 #include <linux/fault-inject.h>
10 #include <linux/kthread.h>
11 #include <linux/sched/mm.h>
12 #include <linux/uaccess.h>
13 #include <uapi/linux/sched/types.h>
15 #include <drm/drm_bridge.h>
16 #include <drm/drm_drv.h>
17 #include <drm/drm_file.h>
18 #include <drm/drm_ioctl.h>
19 #include <drm/drm_prime.h>
20 #include <drm/drm_of.h>
21 #include <drm/drm_vblank.h>
23 #include "disp/msm_disp_snapshot.h"
25 #include "msm_debugfs.h"
26 #include "msm_fence.h"
31 #include "adreno/adreno_gpu.h"
35 * - 1.0.0 - initial interface
36 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
37 * - 1.2.0 - adds explicit fence support for submit ioctl
38 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
39 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
41 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
42 * GEM object's debug name
43 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
44 * - 1.6.0 - Syncobj support
45 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
46 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
47 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
49 #define MSM_VERSION_MAJOR 1
50 #define MSM_VERSION_MINOR 9
51 #define MSM_VERSION_PATCHLEVEL 0
53 static const struct drm_mode_config_funcs mode_config_funcs = {
54 .fb_create = msm_framebuffer_create,
55 .output_poll_changed = drm_fb_helper_output_poll_changed,
56 .atomic_check = drm_atomic_helper_check,
57 .atomic_commit = drm_atomic_helper_commit,
60 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
61 .atomic_commit_tail = msm_atomic_commit_tail,
64 #ifdef CONFIG_DRM_FBDEV_EMULATION
65 static bool fbdev = true;
66 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
67 module_param(fbdev, bool, 0600);
70 static char *vram = "16m";
71 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
72 module_param(vram, charp, 0);
75 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
76 module_param(dumpstate, bool, 0600);
78 static bool modeset = true;
79 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
80 module_param(modeset, bool, 0600);
82 #ifdef CONFIG_FAULT_INJECTION
83 DECLARE_FAULT_ATTR(fail_gem_alloc);
84 DECLARE_FAULT_ATTR(fail_gem_iova);
87 static irqreturn_t msm_irq(int irq, void *arg)
89 struct drm_device *dev = arg;
90 struct msm_drm_private *priv = dev->dev_private;
91 struct msm_kms *kms = priv->kms;
95 return kms->funcs->irq(kms);
98 static void msm_irq_preinstall(struct drm_device *dev)
100 struct msm_drm_private *priv = dev->dev_private;
101 struct msm_kms *kms = priv->kms;
105 kms->funcs->irq_preinstall(kms);
108 static int msm_irq_postinstall(struct drm_device *dev)
110 struct msm_drm_private *priv = dev->dev_private;
111 struct msm_kms *kms = priv->kms;
115 if (kms->funcs->irq_postinstall)
116 return kms->funcs->irq_postinstall(kms);
121 static int msm_irq_install(struct drm_device *dev, unsigned int irq)
123 struct msm_drm_private *priv = dev->dev_private;
124 struct msm_kms *kms = priv->kms;
127 if (irq == IRQ_NOTCONNECTED)
130 msm_irq_preinstall(dev);
132 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
136 kms->irq_requested = true;
138 ret = msm_irq_postinstall(dev);
147 static void msm_irq_uninstall(struct drm_device *dev)
149 struct msm_drm_private *priv = dev->dev_private;
150 struct msm_kms *kms = priv->kms;
152 kms->funcs->irq_uninstall(kms);
153 if (kms->irq_requested)
154 free_irq(kms->irq, dev);
157 struct msm_vblank_work {
158 struct work_struct work;
161 struct msm_drm_private *priv;
164 static void vblank_ctrl_worker(struct work_struct *work)
166 struct msm_vblank_work *vbl_work = container_of(work,
167 struct msm_vblank_work, work);
168 struct msm_drm_private *priv = vbl_work->priv;
169 struct msm_kms *kms = priv->kms;
171 if (vbl_work->enable)
172 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
174 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
179 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
180 int crtc_id, bool enable)
182 struct msm_vblank_work *vbl_work;
184 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
188 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
190 vbl_work->crtc_id = crtc_id;
191 vbl_work->enable = enable;
192 vbl_work->priv = priv;
194 queue_work(priv->wq, &vbl_work->work);
199 static int msm_drm_uninit(struct device *dev)
201 struct platform_device *pdev = to_platform_device(dev);
202 struct msm_drm_private *priv = platform_get_drvdata(pdev);
203 struct drm_device *ddev = priv->dev;
204 struct msm_kms *kms = priv->kms;
208 * Shutdown the hw if we're far enough along where things might be on.
209 * If we run this too early, we'll end up panicking in any variety of
210 * places. Since we don't register the drm device until late in
211 * msm_drm_init, drm_dev->registered is used as an indicator that the
212 * shutdown will be successful.
214 if (ddev->registered) {
215 drm_dev_unregister(ddev);
216 drm_atomic_helper_shutdown(ddev);
219 /* We must cancel and cleanup any pending vblank enable/disable
220 * work before msm_irq_uninstall() to avoid work re-enabling an
221 * irq after uninstall has disabled it.
224 flush_workqueue(priv->wq);
226 /* clean up event worker threads */
227 for (i = 0; i < priv->num_crtcs; i++) {
228 if (priv->event_thread[i].worker)
229 kthread_destroy_worker(priv->event_thread[i].worker);
232 msm_gem_shrinker_cleanup(ddev);
234 drm_kms_helper_poll_fini(ddev);
236 msm_perf_debugfs_cleanup(priv);
237 msm_rd_debugfs_cleanup(priv);
239 #ifdef CONFIG_DRM_FBDEV_EMULATION
240 if (fbdev && priv->fbdev)
241 msm_fbdev_free(ddev);
244 msm_disp_snapshot_destroy(ddev);
246 drm_mode_config_cleanup(ddev);
248 for (i = 0; i < priv->num_bridges; i++)
249 drm_bridge_remove(priv->bridges[i]);
250 priv->num_bridges = 0;
252 pm_runtime_get_sync(dev);
253 msm_irq_uninstall(ddev);
254 pm_runtime_put_sync(dev);
256 if (kms && kms->funcs)
257 kms->funcs->destroy(kms);
259 if (priv->vram.paddr) {
260 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
261 drm_mm_takedown(&priv->vram.mm);
262 dma_free_attrs(dev, priv->vram.size, NULL,
263 priv->vram.paddr, attrs);
266 component_unbind_all(dev, ddev);
268 ddev->dev_private = NULL;
271 destroy_workqueue(priv->wq);
276 #include <linux/of_address.h>
278 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
280 struct iommu_domain *domain;
281 struct msm_gem_address_space *aspace;
283 struct device *mdp_dev = dev->dev;
284 struct device *mdss_dev = mdp_dev->parent;
285 struct device *iommu_dev;
288 * IOMMUs can be a part of MDSS device tree binding, or the
291 if (device_iommu_mapped(mdp_dev))
294 iommu_dev = mdss_dev;
296 domain = iommu_domain_alloc(iommu_dev->bus);
298 drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n");
302 mmu = msm_iommu_new(iommu_dev, domain);
304 iommu_domain_free(domain);
305 return ERR_CAST(mmu);
308 aspace = msm_gem_address_space_create(mmu, "mdp_kms",
309 0x1000, 0x100000000 - 0x1000);
311 mmu->funcs->destroy(mmu);
316 bool msm_use_mmu(struct drm_device *dev)
318 struct msm_drm_private *priv = dev->dev_private;
321 * a2xx comes with its own MMU
322 * On other platforms IOMMU can be declared specified either for the
323 * MDP/DPU device or for its parent, MDSS device.
325 return priv->is_a2xx ||
326 device_iommu_mapped(dev->dev) ||
327 device_iommu_mapped(dev->dev->parent);
330 static int msm_init_vram(struct drm_device *dev)
332 struct msm_drm_private *priv = dev->dev_private;
333 struct device_node *node;
334 unsigned long size = 0;
337 /* In the device-tree world, we could have a 'memory-region'
338 * phandle, which gives us a link to our "vram". Allocating
339 * is all nicely abstracted behind the dma api, but we need
340 * to know the entire size to allocate it all in one go. There
342 * 1) device with no IOMMU, in which case we need exclusive
343 * access to a VRAM carveout big enough for all gpu
345 * 2) device with IOMMU, but where the bootloader puts up
346 * a splash screen. In this case, the VRAM carveout
347 * need only be large enough for fbdev fb. But we need
348 * exclusive access to the buffer to avoid the kernel
349 * using those pages for other purposes (which appears
350 * as corruption on screen before we have a chance to
351 * load and do initial modeset)
354 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
357 ret = of_address_to_resource(node, 0, &r);
361 size = r.end - r.start + 1;
362 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
364 /* if we have no IOMMU, then we need to use carveout allocator.
365 * Grab the entire CMA chunk carved out in early startup in
368 } else if (!msm_use_mmu(dev)) {
369 DRM_INFO("using %s VRAM carveout\n", vram);
370 size = memparse(vram, NULL);
374 unsigned long attrs = 0;
377 priv->vram.size = size;
379 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
380 spin_lock_init(&priv->vram.lock);
382 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
383 attrs |= DMA_ATTR_WRITE_COMBINE;
385 /* note that for no-kernel-mapping, the vaddr returned
386 * is bogus, but non-null if allocation succeeded:
388 p = dma_alloc_attrs(dev->dev, size,
389 &priv->vram.paddr, GFP_KERNEL, attrs);
391 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
392 priv->vram.paddr = 0;
396 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
397 (uint32_t)priv->vram.paddr,
398 (uint32_t)(priv->vram.paddr + size));
404 static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
406 struct msm_drm_private *priv = dev_get_drvdata(dev);
407 struct drm_device *ddev;
411 if (drm_firmware_drivers_only())
414 ddev = drm_dev_alloc(drv, dev);
416 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
417 return PTR_ERR(ddev);
419 ddev->dev_private = priv;
422 priv->wq = alloc_ordered_workqueue("msm", 0);
423 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
425 INIT_LIST_HEAD(&priv->objects);
426 mutex_init(&priv->obj_lock);
429 * Initialize the LRUs:
431 mutex_init(&priv->lru.lock);
432 drm_gem_lru_init(&priv->lru.unbacked, &priv->lru.lock);
433 drm_gem_lru_init(&priv->lru.pinned, &priv->lru.lock);
434 drm_gem_lru_init(&priv->lru.willneed, &priv->lru.lock);
435 drm_gem_lru_init(&priv->lru.dontneed, &priv->lru.lock);
437 /* Teach lockdep about lock ordering wrt. shrinker: */
438 fs_reclaim_acquire(GFP_KERNEL);
439 might_lock(&priv->lru.lock);
440 fs_reclaim_release(GFP_KERNEL);
442 drm_mode_config_init(ddev);
444 ret = msm_init_vram(ddev);
448 /* Bind all our sub-components: */
449 ret = component_bind_all(dev, ddev);
453 dma_set_max_seg_size(dev, UINT_MAX);
455 msm_gem_shrinker_init(ddev);
457 if (priv->kms_init) {
458 ret = priv->kms_init(ddev);
460 DRM_DEV_ERROR(dev, "failed to load kms\n");
466 /* valid only for the dummy headless case, where of_node=NULL */
467 WARN_ON(dev->of_node);
471 /* Enable normalization of plane zpos */
472 ddev->mode_config.normalize_zpos = true;
476 ret = kms->funcs->hw_init(kms);
478 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
483 drm_helper_move_panel_connectors_to_head(ddev);
485 ddev->mode_config.funcs = &mode_config_funcs;
486 ddev->mode_config.helper_private = &mode_config_helper_funcs;
488 for (i = 0; i < priv->num_crtcs; i++) {
489 /* initialize event thread */
490 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
491 priv->event_thread[i].dev = ddev;
492 priv->event_thread[i].worker = kthread_create_worker(0,
493 "crtc_event:%d", priv->event_thread[i].crtc_id);
494 if (IS_ERR(priv->event_thread[i].worker)) {
495 ret = PTR_ERR(priv->event_thread[i].worker);
496 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
497 ret = PTR_ERR(priv->event_thread[i].worker);
501 sched_set_fifo(priv->event_thread[i].worker->task);
504 ret = drm_vblank_init(ddev, priv->num_crtcs);
506 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
511 pm_runtime_get_sync(dev);
512 ret = msm_irq_install(ddev, kms->irq);
513 pm_runtime_put_sync(dev);
515 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
520 ret = drm_dev_register(ddev, 0);
525 ret = msm_disp_snapshot_init(ddev);
527 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
529 drm_mode_config_reset(ddev);
531 #ifdef CONFIG_DRM_FBDEV_EMULATION
533 priv->fbdev = msm_fbdev_init(ddev);
536 ret = msm_debugfs_late_init(ddev);
540 drm_kms_helper_poll_init(ddev);
553 static void load_gpu(struct drm_device *dev)
555 static DEFINE_MUTEX(init_lock);
556 struct msm_drm_private *priv = dev->dev_private;
558 mutex_lock(&init_lock);
561 priv->gpu = adreno_load_gpu(dev);
563 mutex_unlock(&init_lock);
566 static int context_init(struct drm_device *dev, struct drm_file *file)
568 static atomic_t ident = ATOMIC_INIT(0);
569 struct msm_drm_private *priv = dev->dev_private;
570 struct msm_file_private *ctx;
572 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
576 INIT_LIST_HEAD(&ctx->submitqueues);
577 rwlock_init(&ctx->queuelock);
579 kref_init(&ctx->ref);
580 msm_submitqueue_init(dev, ctx);
582 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
583 file->driver_priv = ctx;
585 ctx->seqno = atomic_inc_return(&ident);
590 static int msm_open(struct drm_device *dev, struct drm_file *file)
592 /* For now, load gpu on open.. to avoid the requirement of having
593 * firmware in the initrd.
597 return context_init(dev, file);
600 static void context_close(struct msm_file_private *ctx)
602 msm_submitqueue_close(ctx);
603 msm_file_private_put(ctx);
606 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
608 struct msm_drm_private *priv = dev->dev_private;
609 struct msm_file_private *ctx = file->driver_priv;
612 * It is not possible to set sysprof param to non-zero if gpu
613 * is not initialized:
616 msm_file_private_set_sysprof(ctx, priv->gpu, 0);
621 int msm_crtc_enable_vblank(struct drm_crtc *crtc)
623 struct drm_device *dev = crtc->dev;
624 unsigned int pipe = crtc->index;
625 struct msm_drm_private *priv = dev->dev_private;
626 struct msm_kms *kms = priv->kms;
629 drm_dbg_vbl(dev, "crtc=%u", pipe);
630 return vblank_ctrl_queue_work(priv, pipe, true);
633 void msm_crtc_disable_vblank(struct drm_crtc *crtc)
635 struct drm_device *dev = crtc->dev;
636 unsigned int pipe = crtc->index;
637 struct msm_drm_private *priv = dev->dev_private;
638 struct msm_kms *kms = priv->kms;
641 drm_dbg_vbl(dev, "crtc=%u", pipe);
642 vblank_ctrl_queue_work(priv, pipe, false);
649 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
650 struct drm_file *file)
652 struct msm_drm_private *priv = dev->dev_private;
653 struct drm_msm_param *args = data;
656 /* for now, we just have 3d pipe.. eventually this would need to
657 * be more clever to dispatch to appropriate gpu module:
659 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
667 return gpu->funcs->get_param(gpu, file->driver_priv,
668 args->param, &args->value, &args->len);
671 static int msm_ioctl_set_param(struct drm_device *dev, void *data,
672 struct drm_file *file)
674 struct msm_drm_private *priv = dev->dev_private;
675 struct drm_msm_param *args = data;
678 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
686 return gpu->funcs->set_param(gpu, file->driver_priv,
687 args->param, args->value, args->len);
690 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
691 struct drm_file *file)
693 struct drm_msm_gem_new *args = data;
694 uint32_t flags = args->flags;
696 if (args->flags & ~MSM_BO_FLAGS) {
697 DRM_ERROR("invalid flags: %08x\n", args->flags);
702 * Uncached CPU mappings are deprecated, as of:
704 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)")
706 * So promote them to WC.
708 if (flags & MSM_BO_UNCACHED) {
709 flags &= ~MSM_BO_CACHED;
713 if (should_fail(&fail_gem_alloc, args->size))
716 return msm_gem_new_handle(dev, file, args->size,
717 args->flags, &args->handle, NULL);
720 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
722 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
725 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
726 struct drm_file *file)
728 struct drm_msm_gem_cpu_prep *args = data;
729 struct drm_gem_object *obj;
730 ktime_t timeout = to_ktime(args->timeout);
733 if (args->op & ~MSM_PREP_FLAGS) {
734 DRM_ERROR("invalid op: %08x\n", args->op);
738 obj = drm_gem_object_lookup(file, args->handle);
742 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
744 drm_gem_object_put(obj);
749 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
750 struct drm_file *file)
752 struct drm_msm_gem_cpu_fini *args = data;
753 struct drm_gem_object *obj;
756 obj = drm_gem_object_lookup(file, args->handle);
760 ret = msm_gem_cpu_fini(obj);
762 drm_gem_object_put(obj);
767 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
768 struct drm_file *file, struct drm_gem_object *obj,
771 struct msm_drm_private *priv = dev->dev_private;
772 struct msm_file_private *ctx = file->driver_priv;
777 if (should_fail(&fail_gem_iova, obj->size))
781 * Don't pin the memory here - just get an address so that userspace can
784 return msm_gem_get_iova(obj, ctx->aspace, iova);
787 static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,
788 struct drm_file *file, struct drm_gem_object *obj,
791 struct msm_drm_private *priv = dev->dev_private;
792 struct msm_file_private *ctx = file->driver_priv;
797 /* Only supported if per-process address space is supported: */
798 if (priv->gpu->aspace == ctx->aspace)
801 if (should_fail(&fail_gem_iova, obj->size))
804 return msm_gem_set_iova(obj, ctx->aspace, iova);
807 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
808 struct drm_file *file)
810 struct drm_msm_gem_info *args = data;
811 struct drm_gem_object *obj;
812 struct msm_gem_object *msm_obj;
818 switch (args->info) {
819 case MSM_INFO_GET_OFFSET:
820 case MSM_INFO_GET_IOVA:
821 case MSM_INFO_SET_IOVA:
822 /* value returned as immediate, not pointer, so len==0: */
826 case MSM_INFO_SET_NAME:
827 case MSM_INFO_GET_NAME:
833 obj = drm_gem_object_lookup(file, args->handle);
837 msm_obj = to_msm_bo(obj);
839 switch (args->info) {
840 case MSM_INFO_GET_OFFSET:
841 args->value = msm_gem_mmap_offset(obj);
843 case MSM_INFO_GET_IOVA:
844 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
846 case MSM_INFO_SET_IOVA:
847 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
849 case MSM_INFO_SET_NAME:
850 /* length check should leave room for terminating null: */
851 if (args->len >= sizeof(msm_obj->name)) {
855 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
857 msm_obj->name[0] = '\0';
861 msm_obj->name[args->len] = '\0';
862 for (i = 0; i < args->len; i++) {
863 if (!isprint(msm_obj->name[i])) {
864 msm_obj->name[i] = '\0';
869 case MSM_INFO_GET_NAME:
870 if (args->value && (args->len < strlen(msm_obj->name))) {
874 args->len = strlen(msm_obj->name);
876 if (copy_to_user(u64_to_user_ptr(args->value),
877 msm_obj->name, args->len))
883 drm_gem_object_put(obj);
888 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
891 struct dma_fence *fence;
894 if (fence_after(fence_id, queue->last_fence)) {
895 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
896 fence_id, queue->last_fence);
901 * Map submitqueue scoped "seqno" (which is actually an idr key)
902 * back to underlying dma-fence
904 * The fence is removed from the fence_idr when the submit is
905 * retired, so if the fence is not found it means there is nothing
908 ret = mutex_lock_interruptible(&queue->idr_lock);
911 fence = idr_find(&queue->fence_idr, fence_id);
913 fence = dma_fence_get_rcu(fence);
914 mutex_unlock(&queue->idr_lock);
919 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
922 } else if (ret != -ERESTARTSYS) {
926 dma_fence_put(fence);
931 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
932 struct drm_file *file)
934 struct msm_drm_private *priv = dev->dev_private;
935 struct drm_msm_wait_fence *args = data;
936 struct msm_gpu_submitqueue *queue;
940 DRM_ERROR("invalid pad: %08x\n", args->pad);
947 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
951 ret = wait_fence(queue, args->fence, to_ktime(args->timeout));
953 msm_submitqueue_put(queue);
958 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
959 struct drm_file *file)
961 struct drm_msm_gem_madvise *args = data;
962 struct drm_gem_object *obj;
965 switch (args->madv) {
966 case MSM_MADV_DONTNEED:
967 case MSM_MADV_WILLNEED:
973 obj = drm_gem_object_lookup(file, args->handle);
978 ret = msm_gem_madvise(obj, args->madv);
980 args->retained = ret;
984 drm_gem_object_put(obj);
990 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
991 struct drm_file *file)
993 struct drm_msm_submitqueue *args = data;
995 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
998 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
999 args->flags, &args->id);
1002 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
1003 struct drm_file *file)
1005 return msm_submitqueue_query(dev, file->driver_priv, data);
1008 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
1009 struct drm_file *file)
1011 u32 id = *(u32 *) data;
1013 return msm_submitqueue_remove(file->driver_priv, id);
1016 static const struct drm_ioctl_desc msm_ioctls[] = {
1017 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
1018 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW),
1019 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
1020 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
1021 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
1022 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
1023 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
1024 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
1025 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
1026 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
1027 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
1028 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
1031 static void msm_fop_show_fdinfo(struct seq_file *m, struct file *f)
1033 struct drm_file *file = f->private_data;
1034 struct drm_device *dev = file->minor->dev;
1035 struct msm_drm_private *priv = dev->dev_private;
1036 struct drm_printer p = drm_seq_file_printer(m);
1041 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, &p);
1044 static const struct file_operations fops = {
1045 .owner = THIS_MODULE,
1047 .show_fdinfo = msm_fop_show_fdinfo,
1050 static const struct drm_driver msm_driver = {
1051 .driver_features = DRIVER_GEM |
1057 .postclose = msm_postclose,
1058 .lastclose = drm_fb_helper_lastclose,
1059 .dumb_create = msm_gem_dumb_create,
1060 .dumb_map_offset = msm_gem_dumb_map_offset,
1061 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1062 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1063 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1064 .gem_prime_mmap = msm_gem_prime_mmap,
1065 #ifdef CONFIG_DEBUG_FS
1066 .debugfs_init = msm_debugfs_init,
1068 .ioctls = msm_ioctls,
1069 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1072 .desc = "MSM Snapdragon DRM",
1074 .major = MSM_VERSION_MAJOR,
1075 .minor = MSM_VERSION_MINOR,
1076 .patchlevel = MSM_VERSION_PATCHLEVEL,
1079 int msm_pm_prepare(struct device *dev)
1081 struct msm_drm_private *priv = dev_get_drvdata(dev);
1082 struct drm_device *ddev = priv ? priv->dev : NULL;
1084 if (!priv || !priv->kms)
1087 return drm_mode_config_helper_suspend(ddev);
1090 void msm_pm_complete(struct device *dev)
1092 struct msm_drm_private *priv = dev_get_drvdata(dev);
1093 struct drm_device *ddev = priv ? priv->dev : NULL;
1095 if (!priv || !priv->kms)
1098 drm_mode_config_helper_resume(ddev);
1101 static const struct dev_pm_ops msm_pm_ops = {
1102 .prepare = msm_pm_prepare,
1103 .complete = msm_pm_complete,
1107 * Componentized driver support:
1111 * Identify what components need to be added by parsing what remote-endpoints
1112 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1113 * is no external component that we need to add since LVDS is within MDP4
1116 static int add_components_mdp(struct device *master_dev,
1117 struct component_match **matchptr)
1119 struct device_node *np = master_dev->of_node;
1120 struct device_node *ep_node;
1122 for_each_endpoint_of_node(np, ep_node) {
1123 struct device_node *intf;
1124 struct of_endpoint ep;
1127 ret = of_graph_parse_endpoint(ep_node, &ep);
1129 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n");
1130 of_node_put(ep_node);
1135 * The LCDC/LVDS port on MDP4 is a speacial case where the
1136 * remote-endpoint isn't a component that we need to add
1138 if (of_device_is_compatible(np, "qcom,mdp4") &&
1143 * It's okay if some of the ports don't have a remote endpoint
1144 * specified. It just means that the port isn't connected to
1145 * any external interface.
1147 intf = of_graph_get_remote_port_parent(ep_node);
1151 if (of_device_is_available(intf))
1152 drm_of_component_match_add(master_dev, matchptr,
1153 component_compare_of, intf);
1162 * We don't know what's the best binding to link the gpu with the drm device.
1163 * Fow now, we just hunt for all the possible gpus that we support, and add them
1166 static const struct of_device_id msm_gpu_match[] = {
1167 { .compatible = "qcom,adreno" },
1168 { .compatible = "qcom,adreno-3xx" },
1169 { .compatible = "amd,imageon" },
1170 { .compatible = "qcom,kgsl-3d0" },
1174 static int add_gpu_components(struct device *dev,
1175 struct component_match **matchptr)
1177 struct device_node *np;
1179 np = of_find_matching_node(NULL, msm_gpu_match);
1183 if (of_device_is_available(np))
1184 drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1191 static int msm_drm_bind(struct device *dev)
1193 return msm_drm_init(dev, &msm_driver);
1196 static void msm_drm_unbind(struct device *dev)
1198 msm_drm_uninit(dev);
1201 const struct component_master_ops msm_drm_ops = {
1202 .bind = msm_drm_bind,
1203 .unbind = msm_drm_unbind,
1206 int msm_drv_probe(struct device *master_dev,
1207 int (*kms_init)(struct drm_device *dev))
1209 struct msm_drm_private *priv;
1210 struct component_match *match = NULL;
1213 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL);
1217 priv->kms_init = kms_init;
1218 dev_set_drvdata(master_dev, priv);
1220 /* Add mdp components if we have KMS. */
1222 ret = add_components_mdp(master_dev, &match);
1227 ret = add_gpu_components(master_dev, &match);
1231 /* on all devices that I am aware of, iommu's which can map
1232 * any address the cpu can see are used:
1234 ret = dma_set_mask_and_coherent(master_dev, ~0);
1238 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match);
1247 * Used only for headlesss GPU instances
1250 static int msm_pdev_probe(struct platform_device *pdev)
1252 return msm_drv_probe(&pdev->dev, NULL);
1255 static int msm_pdev_remove(struct platform_device *pdev)
1257 component_master_del(&pdev->dev, &msm_drm_ops);
1262 void msm_drv_shutdown(struct platform_device *pdev)
1264 struct msm_drm_private *priv = platform_get_drvdata(pdev);
1265 struct drm_device *drm = priv ? priv->dev : NULL;
1268 * Shutdown the hw if we're far enough along where things might be on.
1269 * If we run this too early, we'll end up panicking in any variety of
1270 * places. Since we don't register the drm device until late in
1271 * msm_drm_init, drm_dev->registered is used as an indicator that the
1272 * shutdown will be successful.
1274 if (drm && drm->registered)
1275 drm_atomic_helper_shutdown(drm);
1278 static struct platform_driver msm_platform_driver = {
1279 .probe = msm_pdev_probe,
1280 .remove = msm_pdev_remove,
1281 .shutdown = msm_drv_shutdown,
1288 static int __init msm_drm_register(void)
1297 msm_hdmi_register();
1300 msm_mdp4_register();
1301 msm_mdss_register();
1302 return platform_driver_register(&msm_platform_driver);
1305 static void __exit msm_drm_unregister(void)
1308 platform_driver_unregister(&msm_platform_driver);
1309 msm_mdss_unregister();
1310 msm_mdp4_unregister();
1311 msm_dp_unregister();
1312 msm_hdmi_unregister();
1313 adreno_unregister();
1314 msm_dsi_unregister();
1315 msm_mdp_unregister();
1316 msm_dpu_unregister();
1319 module_init(msm_drm_register);
1320 module_exit(msm_drm_unregister);
1322 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1323 MODULE_DESCRIPTION("MSM DRM Driver");
1324 MODULE_LICENSE("GPL");