1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/dma-mapping.h>
9 #include <linux/kthread.h>
10 #include <linux/sched/mm.h>
11 #include <linux/uaccess.h>
12 #include <uapi/linux/sched/types.h>
14 #include <drm/drm_bridge.h>
15 #include <drm/drm_drv.h>
16 #include <drm/drm_file.h>
17 #include <drm/drm_ioctl.h>
18 #include <drm/drm_prime.h>
19 #include <drm/drm_of.h>
20 #include <drm/drm_vblank.h>
22 #include "disp/msm_disp_snapshot.h"
24 #include "msm_debugfs.h"
25 #include "msm_fence.h"
29 #include "adreno/adreno_gpu.h"
33 * - 1.0.0 - initial interface
34 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
35 * - 1.2.0 - adds explicit fence support for submit ioctl
36 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
37 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
39 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
40 * GEM object's debug name
41 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
42 * - 1.6.0 - Syncobj support
43 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
44 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
46 #define MSM_VERSION_MAJOR 1
47 #define MSM_VERSION_MINOR 8
48 #define MSM_VERSION_PATCHLEVEL 0
50 static const struct drm_mode_config_funcs mode_config_funcs = {
51 .fb_create = msm_framebuffer_create,
52 .output_poll_changed = drm_fb_helper_output_poll_changed,
53 .atomic_check = drm_atomic_helper_check,
54 .atomic_commit = drm_atomic_helper_commit,
57 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
58 .atomic_commit_tail = msm_atomic_commit_tail,
61 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
62 static bool reglog = false;
63 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
64 module_param(reglog, bool, 0600);
69 #ifdef CONFIG_DRM_FBDEV_EMULATION
70 static bool fbdev = true;
71 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
72 module_param(fbdev, bool, 0600);
75 static char *vram = "16m";
76 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
77 module_param(vram, charp, 0);
79 bool dumpstate = false;
80 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
81 module_param(dumpstate, bool, 0600);
83 static bool modeset = true;
84 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
85 module_param(modeset, bool, 0600);
91 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
97 snprintf(n, sizeof(n), "%s_clk", name);
99 for (i = 0; bulk && i < count; i++) {
100 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
108 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
113 clk = devm_clk_get(&pdev->dev, name);
114 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
117 snprintf(name2, sizeof(name2), "%s_clk", name);
119 clk = devm_clk_get(&pdev->dev, name2);
121 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
122 "\"%s\" instead of \"%s\"\n", name, name2);
127 static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name,
128 const char *dbgname, bool quiet, phys_addr_t *psize)
130 struct resource *res;
135 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
137 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
141 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
142 return ERR_PTR(-EINVAL);
145 size = resource_size(res);
147 ptr = devm_ioremap(&pdev->dev, res->start, size);
150 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
151 return ERR_PTR(-ENOMEM);
155 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
163 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
166 return _msm_ioremap(pdev, name, dbgname, false, NULL);
169 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
172 return _msm_ioremap(pdev, name, dbgname, true, NULL);
175 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
176 const char *dbgname, phys_addr_t *psize)
178 return _msm_ioremap(pdev, name, dbgname, false, psize);
181 void msm_writel(u32 data, void __iomem *addr)
184 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
188 u32 msm_readl(const void __iomem *addr)
190 u32 val = readl(addr);
192 pr_err("IO:R %p %08x\n", addr, val);
196 void msm_rmw(void __iomem *addr, u32 mask, u32 or)
198 u32 val = msm_readl(addr);
201 msm_writel(val | or, addr);
204 static irqreturn_t msm_irq(int irq, void *arg)
206 struct drm_device *dev = arg;
207 struct msm_drm_private *priv = dev->dev_private;
208 struct msm_kms *kms = priv->kms;
212 return kms->funcs->irq(kms);
215 static void msm_irq_preinstall(struct drm_device *dev)
217 struct msm_drm_private *priv = dev->dev_private;
218 struct msm_kms *kms = priv->kms;
222 kms->funcs->irq_preinstall(kms);
225 static int msm_irq_postinstall(struct drm_device *dev)
227 struct msm_drm_private *priv = dev->dev_private;
228 struct msm_kms *kms = priv->kms;
232 if (kms->funcs->irq_postinstall)
233 return kms->funcs->irq_postinstall(kms);
238 static int msm_irq_install(struct drm_device *dev, unsigned int irq)
242 if (irq == IRQ_NOTCONNECTED)
245 msm_irq_preinstall(dev);
247 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
251 ret = msm_irq_postinstall(dev);
260 static void msm_irq_uninstall(struct drm_device *dev)
262 struct msm_drm_private *priv = dev->dev_private;
263 struct msm_kms *kms = priv->kms;
265 kms->funcs->irq_uninstall(kms);
266 free_irq(kms->irq, dev);
269 struct msm_vblank_work {
270 struct work_struct work;
273 struct msm_drm_private *priv;
276 static void vblank_ctrl_worker(struct work_struct *work)
278 struct msm_vblank_work *vbl_work = container_of(work,
279 struct msm_vblank_work, work);
280 struct msm_drm_private *priv = vbl_work->priv;
281 struct msm_kms *kms = priv->kms;
283 if (vbl_work->enable)
284 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
286 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
291 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
292 int crtc_id, bool enable)
294 struct msm_vblank_work *vbl_work;
296 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
300 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
302 vbl_work->crtc_id = crtc_id;
303 vbl_work->enable = enable;
304 vbl_work->priv = priv;
306 queue_work(priv->wq, &vbl_work->work);
311 static int msm_drm_uninit(struct device *dev)
313 struct platform_device *pdev = to_platform_device(dev);
314 struct drm_device *ddev = platform_get_drvdata(pdev);
315 struct msm_drm_private *priv = ddev->dev_private;
316 struct msm_kms *kms = priv->kms;
317 struct msm_mdss *mdss = priv->mdss;
321 * Shutdown the hw if we're far enough along where things might be on.
322 * If we run this too early, we'll end up panicking in any variety of
323 * places. Since we don't register the drm device until late in
324 * msm_drm_init, drm_dev->registered is used as an indicator that the
325 * shutdown will be successful.
327 if (ddev->registered) {
328 drm_dev_unregister(ddev);
329 drm_atomic_helper_shutdown(ddev);
332 /* We must cancel and cleanup any pending vblank enable/disable
333 * work before msm_irq_uninstall() to avoid work re-enabling an
334 * irq after uninstall has disabled it.
337 flush_workqueue(priv->wq);
339 /* clean up event worker threads */
340 for (i = 0; i < priv->num_crtcs; i++) {
341 if (priv->event_thread[i].worker)
342 kthread_destroy_worker(priv->event_thread[i].worker);
345 msm_gem_shrinker_cleanup(ddev);
347 drm_kms_helper_poll_fini(ddev);
349 msm_perf_debugfs_cleanup(priv);
350 msm_rd_debugfs_cleanup(priv);
352 #ifdef CONFIG_DRM_FBDEV_EMULATION
353 if (fbdev && priv->fbdev)
354 msm_fbdev_free(ddev);
357 msm_disp_snapshot_destroy(ddev);
359 drm_mode_config_cleanup(ddev);
361 pm_runtime_get_sync(dev);
362 msm_irq_uninstall(ddev);
363 pm_runtime_put_sync(dev);
365 if (kms && kms->funcs)
366 kms->funcs->destroy(kms);
368 if (priv->vram.paddr) {
369 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
370 drm_mm_takedown(&priv->vram.mm);
371 dma_free_attrs(dev, priv->vram.size, NULL,
372 priv->vram.paddr, attrs);
375 component_unbind_all(dev, ddev);
377 if (mdss && mdss->funcs)
378 mdss->funcs->destroy(ddev);
380 ddev->dev_private = NULL;
383 destroy_workqueue(priv->wq);
393 static int get_mdp_ver(struct platform_device *pdev)
395 struct device *dev = &pdev->dev;
397 return (int) (unsigned long) of_device_get_match_data(dev);
400 #include <linux/of_address.h>
402 bool msm_use_mmu(struct drm_device *dev)
404 struct msm_drm_private *priv = dev->dev_private;
406 /* a2xx comes with its own MMU */
407 return priv->is_a2xx || iommu_present(&platform_bus_type);
410 static int msm_init_vram(struct drm_device *dev)
412 struct msm_drm_private *priv = dev->dev_private;
413 struct device_node *node;
414 unsigned long size = 0;
417 /* In the device-tree world, we could have a 'memory-region'
418 * phandle, which gives us a link to our "vram". Allocating
419 * is all nicely abstracted behind the dma api, but we need
420 * to know the entire size to allocate it all in one go. There
422 * 1) device with no IOMMU, in which case we need exclusive
423 * access to a VRAM carveout big enough for all gpu
425 * 2) device with IOMMU, but where the bootloader puts up
426 * a splash screen. In this case, the VRAM carveout
427 * need only be large enough for fbdev fb. But we need
428 * exclusive access to the buffer to avoid the kernel
429 * using those pages for other purposes (which appears
430 * as corruption on screen before we have a chance to
431 * load and do initial modeset)
434 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
437 ret = of_address_to_resource(node, 0, &r);
441 size = r.end - r.start + 1;
442 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
444 /* if we have no IOMMU, then we need to use carveout allocator.
445 * Grab the entire CMA chunk carved out in early startup in
448 } else if (!msm_use_mmu(dev)) {
449 DRM_INFO("using %s VRAM carveout\n", vram);
450 size = memparse(vram, NULL);
454 unsigned long attrs = 0;
457 priv->vram.size = size;
459 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
460 spin_lock_init(&priv->vram.lock);
462 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
463 attrs |= DMA_ATTR_WRITE_COMBINE;
465 /* note that for no-kernel-mapping, the vaddr returned
466 * is bogus, but non-null if allocation succeeded:
468 p = dma_alloc_attrs(dev->dev, size,
469 &priv->vram.paddr, GFP_KERNEL, attrs);
471 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
472 priv->vram.paddr = 0;
476 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
477 (uint32_t)priv->vram.paddr,
478 (uint32_t)(priv->vram.paddr + size));
484 static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
486 struct platform_device *pdev = to_platform_device(dev);
487 struct drm_device *ddev;
488 struct msm_drm_private *priv;
490 struct msm_mdss *mdss;
493 ddev = drm_dev_alloc(drv, dev);
495 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
496 return PTR_ERR(ddev);
499 platform_set_drvdata(pdev, ddev);
501 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
504 goto err_put_drm_dev;
507 ddev->dev_private = priv;
510 switch (get_mdp_ver(pdev)) {
512 ret = mdp5_mdss_init(ddev);
515 ret = dpu_mdss_init(ddev);
526 priv->wq = alloc_ordered_workqueue("msm", 0);
527 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
529 INIT_LIST_HEAD(&priv->objects);
530 mutex_init(&priv->obj_lock);
532 INIT_LIST_HEAD(&priv->inactive_willneed);
533 INIT_LIST_HEAD(&priv->inactive_dontneed);
534 INIT_LIST_HEAD(&priv->inactive_unpinned);
535 mutex_init(&priv->mm_lock);
537 /* Teach lockdep about lock ordering wrt. shrinker: */
538 fs_reclaim_acquire(GFP_KERNEL);
539 might_lock(&priv->mm_lock);
540 fs_reclaim_release(GFP_KERNEL);
542 drm_mode_config_init(ddev);
544 ret = msm_init_vram(ddev);
546 goto err_destroy_mdss;
548 /* Bind all our sub-components: */
549 ret = component_bind_all(dev, ddev);
551 goto err_destroy_mdss;
553 dma_set_max_seg_size(dev, UINT_MAX);
555 msm_gem_shrinker_init(ddev);
557 switch (get_mdp_ver(pdev)) {
559 kms = mdp4_kms_init(ddev);
563 kms = mdp5_kms_init(ddev);
566 kms = dpu_kms_init(ddev);
570 /* valid only for the dummy headless case, where of_node=NULL */
571 WARN_ON(dev->of_node);
577 DRM_DEV_ERROR(dev, "failed to load kms\n");
583 /* Enable normalization of plane zpos */
584 ddev->mode_config.normalize_zpos = true;
588 ret = kms->funcs->hw_init(kms);
590 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
595 ddev->mode_config.funcs = &mode_config_funcs;
596 ddev->mode_config.helper_private = &mode_config_helper_funcs;
598 for (i = 0; i < priv->num_crtcs; i++) {
599 /* initialize event thread */
600 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
601 priv->event_thread[i].dev = ddev;
602 priv->event_thread[i].worker = kthread_create_worker(0,
603 "crtc_event:%d", priv->event_thread[i].crtc_id);
604 if (IS_ERR(priv->event_thread[i].worker)) {
605 ret = PTR_ERR(priv->event_thread[i].worker);
606 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
607 ret = PTR_ERR(priv->event_thread[i].worker);
611 sched_set_fifo(priv->event_thread[i].worker->task);
614 ret = drm_vblank_init(ddev, priv->num_crtcs);
616 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
621 pm_runtime_get_sync(dev);
622 ret = msm_irq_install(ddev, kms->irq);
623 pm_runtime_put_sync(dev);
625 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
630 ret = drm_dev_register(ddev, 0);
635 ret = msm_disp_snapshot_init(ddev);
637 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
639 drm_mode_config_reset(ddev);
641 #ifdef CONFIG_DRM_FBDEV_EMULATION
643 priv->fbdev = msm_fbdev_init(ddev);
646 ret = msm_debugfs_late_init(ddev);
650 drm_kms_helper_poll_init(ddev);
658 if (mdss && mdss->funcs)
659 mdss->funcs->destroy(ddev);
664 platform_set_drvdata(pdev, NULL);
672 static void load_gpu(struct drm_device *dev)
674 static DEFINE_MUTEX(init_lock);
675 struct msm_drm_private *priv = dev->dev_private;
677 mutex_lock(&init_lock);
680 priv->gpu = adreno_load_gpu(dev);
682 mutex_unlock(&init_lock);
685 static int context_init(struct drm_device *dev, struct drm_file *file)
687 static atomic_t ident = ATOMIC_INIT(0);
688 struct msm_drm_private *priv = dev->dev_private;
689 struct msm_file_private *ctx;
691 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
695 INIT_LIST_HEAD(&ctx->submitqueues);
696 rwlock_init(&ctx->queuelock);
698 kref_init(&ctx->ref);
699 msm_submitqueue_init(dev, ctx);
701 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
702 file->driver_priv = ctx;
704 ctx->seqno = atomic_inc_return(&ident);
709 static int msm_open(struct drm_device *dev, struct drm_file *file)
711 /* For now, load gpu on open.. to avoid the requirement of having
712 * firmware in the initrd.
716 return context_init(dev, file);
719 static void context_close(struct msm_file_private *ctx)
721 msm_submitqueue_close(ctx);
722 msm_file_private_put(ctx);
725 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
727 struct msm_drm_private *priv = dev->dev_private;
728 struct msm_file_private *ctx = file->driver_priv;
730 mutex_lock(&dev->struct_mutex);
731 if (ctx == priv->lastctx)
732 priv->lastctx = NULL;
733 mutex_unlock(&dev->struct_mutex);
738 int msm_crtc_enable_vblank(struct drm_crtc *crtc)
740 struct drm_device *dev = crtc->dev;
741 unsigned int pipe = crtc->index;
742 struct msm_drm_private *priv = dev->dev_private;
743 struct msm_kms *kms = priv->kms;
746 drm_dbg_vbl(dev, "crtc=%u", pipe);
747 return vblank_ctrl_queue_work(priv, pipe, true);
750 void msm_crtc_disable_vblank(struct drm_crtc *crtc)
752 struct drm_device *dev = crtc->dev;
753 unsigned int pipe = crtc->index;
754 struct msm_drm_private *priv = dev->dev_private;
755 struct msm_kms *kms = priv->kms;
758 drm_dbg_vbl(dev, "crtc=%u", pipe);
759 vblank_ctrl_queue_work(priv, pipe, false);
766 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
767 struct drm_file *file)
769 struct msm_drm_private *priv = dev->dev_private;
770 struct drm_msm_param *args = data;
773 /* for now, we just have 3d pipe.. eventually this would need to
774 * be more clever to dispatch to appropriate gpu module:
776 if (args->pipe != MSM_PIPE_3D0)
784 return gpu->funcs->get_param(gpu, args->param, &args->value);
787 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
788 struct drm_file *file)
790 struct drm_msm_gem_new *args = data;
792 if (args->flags & ~MSM_BO_FLAGS) {
793 DRM_ERROR("invalid flags: %08x\n", args->flags);
797 return msm_gem_new_handle(dev, file, args->size,
798 args->flags, &args->handle, NULL);
801 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
803 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
806 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
807 struct drm_file *file)
809 struct drm_msm_gem_cpu_prep *args = data;
810 struct drm_gem_object *obj;
811 ktime_t timeout = to_ktime(args->timeout);
814 if (args->op & ~MSM_PREP_FLAGS) {
815 DRM_ERROR("invalid op: %08x\n", args->op);
819 obj = drm_gem_object_lookup(file, args->handle);
823 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
825 drm_gem_object_put(obj);
830 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
831 struct drm_file *file)
833 struct drm_msm_gem_cpu_fini *args = data;
834 struct drm_gem_object *obj;
837 obj = drm_gem_object_lookup(file, args->handle);
841 ret = msm_gem_cpu_fini(obj);
843 drm_gem_object_put(obj);
848 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
849 struct drm_file *file, struct drm_gem_object *obj,
852 struct msm_drm_private *priv = dev->dev_private;
853 struct msm_file_private *ctx = file->driver_priv;
859 * Don't pin the memory here - just get an address so that userspace can
862 return msm_gem_get_iova(obj, ctx->aspace, iova);
865 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
866 struct drm_file *file)
868 struct drm_msm_gem_info *args = data;
869 struct drm_gem_object *obj;
870 struct msm_gem_object *msm_obj;
876 switch (args->info) {
877 case MSM_INFO_GET_OFFSET:
878 case MSM_INFO_GET_IOVA:
879 /* value returned as immediate, not pointer, so len==0: */
883 case MSM_INFO_SET_NAME:
884 case MSM_INFO_GET_NAME:
890 obj = drm_gem_object_lookup(file, args->handle);
894 msm_obj = to_msm_bo(obj);
896 switch (args->info) {
897 case MSM_INFO_GET_OFFSET:
898 args->value = msm_gem_mmap_offset(obj);
900 case MSM_INFO_GET_IOVA:
901 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
903 case MSM_INFO_SET_NAME:
904 /* length check should leave room for terminating null: */
905 if (args->len >= sizeof(msm_obj->name)) {
909 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
911 msm_obj->name[0] = '\0';
915 msm_obj->name[args->len] = '\0';
916 for (i = 0; i < args->len; i++) {
917 if (!isprint(msm_obj->name[i])) {
918 msm_obj->name[i] = '\0';
923 case MSM_INFO_GET_NAME:
924 if (args->value && (args->len < strlen(msm_obj->name))) {
928 args->len = strlen(msm_obj->name);
930 if (copy_to_user(u64_to_user_ptr(args->value),
931 msm_obj->name, args->len))
937 drm_gem_object_put(obj);
942 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
945 struct dma_fence *fence;
948 if (fence_id > queue->last_fence) {
949 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
950 fence_id, queue->last_fence);
955 * Map submitqueue scoped "seqno" (which is actually an idr key)
956 * back to underlying dma-fence
958 * The fence is removed from the fence_idr when the submit is
959 * retired, so if the fence is not found it means there is nothing
962 ret = mutex_lock_interruptible(&queue->lock);
965 fence = idr_find(&queue->fence_idr, fence_id);
967 fence = dma_fence_get_rcu(fence);
968 mutex_unlock(&queue->lock);
973 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
976 } else if (ret != -ERESTARTSYS) {
980 dma_fence_put(fence);
985 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
986 struct drm_file *file)
988 struct msm_drm_private *priv = dev->dev_private;
989 struct drm_msm_wait_fence *args = data;
990 struct msm_gpu_submitqueue *queue;
994 DRM_ERROR("invalid pad: %08x\n", args->pad);
1001 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
1005 ret = wait_fence(queue, args->fence, to_ktime(args->timeout));
1007 msm_submitqueue_put(queue);
1012 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
1013 struct drm_file *file)
1015 struct drm_msm_gem_madvise *args = data;
1016 struct drm_gem_object *obj;
1019 switch (args->madv) {
1020 case MSM_MADV_DONTNEED:
1021 case MSM_MADV_WILLNEED:
1027 obj = drm_gem_object_lookup(file, args->handle);
1032 ret = msm_gem_madvise(obj, args->madv);
1034 args->retained = ret;
1038 drm_gem_object_put(obj);
1044 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
1045 struct drm_file *file)
1047 struct drm_msm_submitqueue *args = data;
1049 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
1052 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
1053 args->flags, &args->id);
1056 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
1057 struct drm_file *file)
1059 return msm_submitqueue_query(dev, file->driver_priv, data);
1062 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
1063 struct drm_file *file)
1065 u32 id = *(u32 *) data;
1067 return msm_submitqueue_remove(file->driver_priv, id);
1070 static const struct drm_ioctl_desc msm_ioctls[] = {
1071 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
1072 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
1073 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
1074 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
1075 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
1076 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
1077 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
1078 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
1079 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
1080 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
1081 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
1084 DEFINE_DRM_GEM_FOPS(fops);
1086 static const struct drm_driver msm_driver = {
1087 .driver_features = DRIVER_GEM |
1093 .postclose = msm_postclose,
1094 .lastclose = drm_fb_helper_lastclose,
1095 .dumb_create = msm_gem_dumb_create,
1096 .dumb_map_offset = msm_gem_dumb_map_offset,
1097 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1098 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1099 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1100 .gem_prime_mmap = drm_gem_prime_mmap,
1101 #ifdef CONFIG_DEBUG_FS
1102 .debugfs_init = msm_debugfs_init,
1104 .ioctls = msm_ioctls,
1105 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1108 .desc = "MSM Snapdragon DRM",
1110 .major = MSM_VERSION_MAJOR,
1111 .minor = MSM_VERSION_MINOR,
1112 .patchlevel = MSM_VERSION_PATCHLEVEL,
1115 static int __maybe_unused msm_runtime_suspend(struct device *dev)
1117 struct drm_device *ddev = dev_get_drvdata(dev);
1118 struct msm_drm_private *priv = ddev->dev_private;
1119 struct msm_mdss *mdss = priv->mdss;
1123 if (mdss && mdss->funcs)
1124 return mdss->funcs->disable(mdss);
1129 static int __maybe_unused msm_runtime_resume(struct device *dev)
1131 struct drm_device *ddev = dev_get_drvdata(dev);
1132 struct msm_drm_private *priv = ddev->dev_private;
1133 struct msm_mdss *mdss = priv->mdss;
1137 if (mdss && mdss->funcs)
1138 return mdss->funcs->enable(mdss);
1143 static int __maybe_unused msm_pm_suspend(struct device *dev)
1146 if (pm_runtime_suspended(dev))
1149 return msm_runtime_suspend(dev);
1152 static int __maybe_unused msm_pm_resume(struct device *dev)
1154 if (pm_runtime_suspended(dev))
1157 return msm_runtime_resume(dev);
1160 static int __maybe_unused msm_pm_prepare(struct device *dev)
1162 struct drm_device *ddev = dev_get_drvdata(dev);
1163 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL;
1165 if (!priv || !priv->kms)
1168 return drm_mode_config_helper_suspend(ddev);
1171 static void __maybe_unused msm_pm_complete(struct device *dev)
1173 struct drm_device *ddev = dev_get_drvdata(dev);
1174 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL;
1176 if (!priv || !priv->kms)
1179 drm_mode_config_helper_resume(ddev);
1182 static const struct dev_pm_ops msm_pm_ops = {
1183 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1184 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1185 .prepare = msm_pm_prepare,
1186 .complete = msm_pm_complete,
1190 * Componentized driver support:
1194 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1195 * so probably some room for some helpers
1197 static int compare_of(struct device *dev, void *data)
1199 return dev->of_node == data;
1203 * Identify what components need to be added by parsing what remote-endpoints
1204 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1205 * is no external component that we need to add since LVDS is within MDP4
1208 static int add_components_mdp(struct device *mdp_dev,
1209 struct component_match **matchptr)
1211 struct device_node *np = mdp_dev->of_node;
1212 struct device_node *ep_node;
1213 struct device *master_dev;
1216 * on MDP4 based platforms, the MDP platform device is the component
1217 * master that adds other display interface components to itself.
1219 * on MDP5 based platforms, the MDSS platform device is the component
1220 * master that adds MDP5 and other display interface components to
1223 if (of_device_is_compatible(np, "qcom,mdp4"))
1224 master_dev = mdp_dev;
1226 master_dev = mdp_dev->parent;
1228 for_each_endpoint_of_node(np, ep_node) {
1229 struct device_node *intf;
1230 struct of_endpoint ep;
1233 ret = of_graph_parse_endpoint(ep_node, &ep);
1235 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1236 of_node_put(ep_node);
1241 * The LCDC/LVDS port on MDP4 is a speacial case where the
1242 * remote-endpoint isn't a component that we need to add
1244 if (of_device_is_compatible(np, "qcom,mdp4") &&
1249 * It's okay if some of the ports don't have a remote endpoint
1250 * specified. It just means that the port isn't connected to
1251 * any external interface.
1253 intf = of_graph_get_remote_port_parent(ep_node);
1257 if (of_device_is_available(intf))
1258 drm_of_component_match_add(master_dev, matchptr,
1267 static int compare_name_mdp(struct device *dev, void *data)
1269 return (strstr(dev_name(dev), "mdp") != NULL);
1272 static int add_display_components(struct platform_device *pdev,
1273 struct component_match **matchptr)
1275 struct device *mdp_dev;
1276 struct device *dev = &pdev->dev;
1280 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1281 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1282 * Populate the children devices, find the MDP5/DPU node, and then add
1283 * the interfaces to our components list.
1285 switch (get_mdp_ver(pdev)) {
1288 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1290 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1294 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1296 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1297 of_platform_depopulate(dev);
1301 put_device(mdp_dev);
1303 /* add the MDP component itself */
1304 drm_of_component_match_add(dev, matchptr, compare_of,
1313 ret = add_components_mdp(mdp_dev, matchptr);
1315 of_platform_depopulate(dev);
1321 * We don't know what's the best binding to link the gpu with the drm device.
1322 * Fow now, we just hunt for all the possible gpus that we support, and add them
1325 static const struct of_device_id msm_gpu_match[] = {
1326 { .compatible = "qcom,adreno" },
1327 { .compatible = "qcom,adreno-3xx" },
1328 { .compatible = "amd,imageon" },
1329 { .compatible = "qcom,kgsl-3d0" },
1333 static int add_gpu_components(struct device *dev,
1334 struct component_match **matchptr)
1336 struct device_node *np;
1338 np = of_find_matching_node(NULL, msm_gpu_match);
1342 if (of_device_is_available(np))
1343 drm_of_component_match_add(dev, matchptr, compare_of, np);
1350 static int msm_drm_bind(struct device *dev)
1352 return msm_drm_init(dev, &msm_driver);
1355 static void msm_drm_unbind(struct device *dev)
1357 msm_drm_uninit(dev);
1360 static const struct component_master_ops msm_drm_ops = {
1361 .bind = msm_drm_bind,
1362 .unbind = msm_drm_unbind,
1369 static int msm_pdev_probe(struct platform_device *pdev)
1371 struct component_match *match = NULL;
1374 if (get_mdp_ver(pdev)) {
1375 ret = add_display_components(pdev, &match);
1380 ret = add_gpu_components(&pdev->dev, &match);
1384 /* on all devices that I am aware of, iommu's which can map
1385 * any address the cpu can see are used:
1387 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1391 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1398 of_platform_depopulate(&pdev->dev);
1402 static int msm_pdev_remove(struct platform_device *pdev)
1404 component_master_del(&pdev->dev, &msm_drm_ops);
1405 of_platform_depopulate(&pdev->dev);
1410 static void msm_pdev_shutdown(struct platform_device *pdev)
1412 struct drm_device *drm = platform_get_drvdata(pdev);
1413 struct msm_drm_private *priv = drm ? drm->dev_private : NULL;
1415 if (!priv || !priv->kms)
1418 drm_atomic_helper_shutdown(drm);
1421 static const struct of_device_id dt_match[] = {
1422 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1423 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1424 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1425 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
1426 { .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU },
1427 { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
1428 { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
1431 MODULE_DEVICE_TABLE(of, dt_match);
1433 static struct platform_driver msm_platform_driver = {
1434 .probe = msm_pdev_probe,
1435 .remove = msm_pdev_remove,
1436 .shutdown = msm_pdev_shutdown,
1439 .of_match_table = dt_match,
1444 static int __init msm_drm_register(void)
1454 msm_hdmi_register();
1457 return platform_driver_register(&msm_platform_driver);
1460 static void __exit msm_drm_unregister(void)
1463 platform_driver_unregister(&msm_platform_driver);
1464 msm_dp_unregister();
1465 msm_hdmi_unregister();
1466 adreno_unregister();
1467 msm_edp_unregister();
1468 msm_dsi_unregister();
1469 msm_mdp_unregister();
1470 msm_dpu_unregister();
1473 module_init(msm_drm_register);
1474 module_exit(msm_drm_unregister);
1476 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1477 MODULE_DESCRIPTION("MSM DRM Driver");
1478 MODULE_LICENSE("GPL");