1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/dma-mapping.h>
9 #include <linux/fault-inject.h>
10 #include <linux/kthread.h>
11 #include <linux/sched/mm.h>
12 #include <linux/uaccess.h>
13 #include <uapi/linux/sched/types.h>
15 #include <drm/drm_bridge.h>
16 #include <drm/drm_drv.h>
17 #include <drm/drm_file.h>
18 #include <drm/drm_ioctl.h>
19 #include <drm/drm_prime.h>
20 #include <drm/drm_of.h>
21 #include <drm/drm_vblank.h>
23 #include "disp/msm_disp_snapshot.h"
25 #include "msm_debugfs.h"
26 #include "msm_fence.h"
31 #include "adreno/adreno_gpu.h"
35 * - 1.0.0 - initial interface
36 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
37 * - 1.2.0 - adds explicit fence support for submit ioctl
38 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
39 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
41 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
42 * GEM object's debug name
43 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
44 * - 1.6.0 - Syncobj support
45 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
46 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
47 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
49 #define MSM_VERSION_MAJOR 1
50 #define MSM_VERSION_MINOR 9
51 #define MSM_VERSION_PATCHLEVEL 0
53 static const struct drm_mode_config_funcs mode_config_funcs = {
54 .fb_create = msm_framebuffer_create,
55 .output_poll_changed = drm_fb_helper_output_poll_changed,
56 .atomic_check = drm_atomic_helper_check,
57 .atomic_commit = drm_atomic_helper_commit,
60 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
61 .atomic_commit_tail = msm_atomic_commit_tail,
64 #ifdef CONFIG_DRM_FBDEV_EMULATION
65 static bool fbdev = true;
66 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
67 module_param(fbdev, bool, 0600);
70 static char *vram = "16m";
71 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
72 module_param(vram, charp, 0);
75 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
76 module_param(dumpstate, bool, 0600);
78 static bool modeset = true;
79 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
80 module_param(modeset, bool, 0600);
82 #ifdef CONFIG_FAULT_INJECTION
83 DECLARE_FAULT_ATTR(fail_gem_alloc);
84 DECLARE_FAULT_ATTR(fail_gem_iova);
87 static irqreturn_t msm_irq(int irq, void *arg)
89 struct drm_device *dev = arg;
90 struct msm_drm_private *priv = dev->dev_private;
91 struct msm_kms *kms = priv->kms;
95 return kms->funcs->irq(kms);
98 static void msm_irq_preinstall(struct drm_device *dev)
100 struct msm_drm_private *priv = dev->dev_private;
101 struct msm_kms *kms = priv->kms;
105 kms->funcs->irq_preinstall(kms);
108 static int msm_irq_postinstall(struct drm_device *dev)
110 struct msm_drm_private *priv = dev->dev_private;
111 struct msm_kms *kms = priv->kms;
115 if (kms->funcs->irq_postinstall)
116 return kms->funcs->irq_postinstall(kms);
121 static int msm_irq_install(struct drm_device *dev, unsigned int irq)
123 struct msm_drm_private *priv = dev->dev_private;
124 struct msm_kms *kms = priv->kms;
127 if (irq == IRQ_NOTCONNECTED)
130 msm_irq_preinstall(dev);
132 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
136 kms->irq_requested = true;
138 ret = msm_irq_postinstall(dev);
147 static void msm_irq_uninstall(struct drm_device *dev)
149 struct msm_drm_private *priv = dev->dev_private;
150 struct msm_kms *kms = priv->kms;
152 kms->funcs->irq_uninstall(kms);
153 if (kms->irq_requested)
154 free_irq(kms->irq, dev);
157 struct msm_vblank_work {
158 struct work_struct work;
161 struct msm_drm_private *priv;
164 static void vblank_ctrl_worker(struct work_struct *work)
166 struct msm_vblank_work *vbl_work = container_of(work,
167 struct msm_vblank_work, work);
168 struct msm_drm_private *priv = vbl_work->priv;
169 struct msm_kms *kms = priv->kms;
171 if (vbl_work->enable)
172 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
174 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
179 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
180 int crtc_id, bool enable)
182 struct msm_vblank_work *vbl_work;
184 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
188 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
190 vbl_work->crtc_id = crtc_id;
191 vbl_work->enable = enable;
192 vbl_work->priv = priv;
194 queue_work(priv->wq, &vbl_work->work);
199 static int msm_drm_uninit(struct device *dev)
201 struct platform_device *pdev = to_platform_device(dev);
202 struct msm_drm_private *priv = platform_get_drvdata(pdev);
203 struct drm_device *ddev = priv->dev;
204 struct msm_kms *kms = priv->kms;
208 * Shutdown the hw if we're far enough along where things might be on.
209 * If we run this too early, we'll end up panicking in any variety of
210 * places. Since we don't register the drm device until late in
211 * msm_drm_init, drm_dev->registered is used as an indicator that the
212 * shutdown will be successful.
214 if (ddev->registered) {
215 drm_dev_unregister(ddev);
216 drm_atomic_helper_shutdown(ddev);
219 /* We must cancel and cleanup any pending vblank enable/disable
220 * work before msm_irq_uninstall() to avoid work re-enabling an
221 * irq after uninstall has disabled it.
224 flush_workqueue(priv->wq);
226 /* clean up event worker threads */
227 for (i = 0; i < priv->num_crtcs; i++) {
228 if (priv->event_thread[i].worker)
229 kthread_destroy_worker(priv->event_thread[i].worker);
232 msm_gem_shrinker_cleanup(ddev);
234 drm_kms_helper_poll_fini(ddev);
236 msm_perf_debugfs_cleanup(priv);
237 msm_rd_debugfs_cleanup(priv);
239 #ifdef CONFIG_DRM_FBDEV_EMULATION
240 if (fbdev && priv->fbdev)
241 msm_fbdev_free(ddev);
244 msm_disp_snapshot_destroy(ddev);
246 drm_mode_config_cleanup(ddev);
248 for (i = 0; i < priv->num_bridges; i++)
249 drm_bridge_remove(priv->bridges[i]);
251 pm_runtime_get_sync(dev);
252 msm_irq_uninstall(ddev);
253 pm_runtime_put_sync(dev);
255 if (kms && kms->funcs)
256 kms->funcs->destroy(kms);
258 if (priv->vram.paddr) {
259 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
260 drm_mm_takedown(&priv->vram.mm);
261 dma_free_attrs(dev, priv->vram.size, NULL,
262 priv->vram.paddr, attrs);
265 component_unbind_all(dev, ddev);
267 ddev->dev_private = NULL;
270 destroy_workqueue(priv->wq);
275 #include <linux/of_address.h>
277 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
279 struct iommu_domain *domain;
280 struct msm_gem_address_space *aspace;
282 struct device *mdp_dev = dev->dev;
283 struct device *mdss_dev = mdp_dev->parent;
284 struct device *iommu_dev;
287 * IOMMUs can be a part of MDSS device tree binding, or the
290 if (device_iommu_mapped(mdp_dev))
293 iommu_dev = mdss_dev;
295 domain = iommu_domain_alloc(iommu_dev->bus);
297 drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n");
301 mmu = msm_iommu_new(iommu_dev, domain);
303 iommu_domain_free(domain);
304 return ERR_CAST(mmu);
307 aspace = msm_gem_address_space_create(mmu, "mdp_kms",
308 0x1000, 0x100000000 - 0x1000);
310 mmu->funcs->destroy(mmu);
315 bool msm_use_mmu(struct drm_device *dev)
317 struct msm_drm_private *priv = dev->dev_private;
320 * a2xx comes with its own MMU
321 * On other platforms IOMMU can be declared specified either for the
322 * MDP/DPU device or for its parent, MDSS device.
324 return priv->is_a2xx ||
325 device_iommu_mapped(dev->dev) ||
326 device_iommu_mapped(dev->dev->parent);
329 static int msm_init_vram(struct drm_device *dev)
331 struct msm_drm_private *priv = dev->dev_private;
332 struct device_node *node;
333 unsigned long size = 0;
336 /* In the device-tree world, we could have a 'memory-region'
337 * phandle, which gives us a link to our "vram". Allocating
338 * is all nicely abstracted behind the dma api, but we need
339 * to know the entire size to allocate it all in one go. There
341 * 1) device with no IOMMU, in which case we need exclusive
342 * access to a VRAM carveout big enough for all gpu
344 * 2) device with IOMMU, but where the bootloader puts up
345 * a splash screen. In this case, the VRAM carveout
346 * need only be large enough for fbdev fb. But we need
347 * exclusive access to the buffer to avoid the kernel
348 * using those pages for other purposes (which appears
349 * as corruption on screen before we have a chance to
350 * load and do initial modeset)
353 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
356 ret = of_address_to_resource(node, 0, &r);
360 size = r.end - r.start + 1;
361 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
363 /* if we have no IOMMU, then we need to use carveout allocator.
364 * Grab the entire DMA chunk carved out in early startup in
367 } else if (!msm_use_mmu(dev)) {
368 DRM_INFO("using %s VRAM carveout\n", vram);
369 size = memparse(vram, NULL);
373 unsigned long attrs = 0;
376 priv->vram.size = size;
378 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
379 spin_lock_init(&priv->vram.lock);
381 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
382 attrs |= DMA_ATTR_WRITE_COMBINE;
384 /* note that for no-kernel-mapping, the vaddr returned
385 * is bogus, but non-null if allocation succeeded:
387 p = dma_alloc_attrs(dev->dev, size,
388 &priv->vram.paddr, GFP_KERNEL, attrs);
390 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
391 priv->vram.paddr = 0;
395 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
396 (uint32_t)priv->vram.paddr,
397 (uint32_t)(priv->vram.paddr + size));
403 static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
405 struct msm_drm_private *priv = dev_get_drvdata(dev);
406 struct drm_device *ddev;
410 if (drm_firmware_drivers_only())
413 ddev = drm_dev_alloc(drv, dev);
415 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
416 return PTR_ERR(ddev);
418 ddev->dev_private = priv;
421 priv->wq = alloc_ordered_workqueue("msm", 0);
422 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
424 INIT_LIST_HEAD(&priv->objects);
425 mutex_init(&priv->obj_lock);
428 * Initialize the LRUs:
430 mutex_init(&priv->lru.lock);
431 drm_gem_lru_init(&priv->lru.unbacked, &priv->lru.lock);
432 drm_gem_lru_init(&priv->lru.pinned, &priv->lru.lock);
433 drm_gem_lru_init(&priv->lru.willneed, &priv->lru.lock);
434 drm_gem_lru_init(&priv->lru.dontneed, &priv->lru.lock);
436 /* Teach lockdep about lock ordering wrt. shrinker: */
437 fs_reclaim_acquire(GFP_KERNEL);
438 might_lock(&priv->lru.lock);
439 fs_reclaim_release(GFP_KERNEL);
441 drm_mode_config_init(ddev);
443 ret = msm_init_vram(ddev);
447 /* Bind all our sub-components: */
448 ret = component_bind_all(dev, ddev);
452 dma_set_max_seg_size(dev, UINT_MAX);
454 msm_gem_shrinker_init(ddev);
456 if (priv->kms_init) {
457 ret = priv->kms_init(ddev);
459 DRM_DEV_ERROR(dev, "failed to load kms\n");
465 /* valid only for the dummy headless case, where of_node=NULL */
466 WARN_ON(dev->of_node);
470 /* Enable normalization of plane zpos */
471 ddev->mode_config.normalize_zpos = true;
475 ret = kms->funcs->hw_init(kms);
477 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
482 drm_helper_move_panel_connectors_to_head(ddev);
484 ddev->mode_config.funcs = &mode_config_funcs;
485 ddev->mode_config.helper_private = &mode_config_helper_funcs;
487 for (i = 0; i < priv->num_crtcs; i++) {
488 /* initialize event thread */
489 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
490 priv->event_thread[i].dev = ddev;
491 priv->event_thread[i].worker = kthread_create_worker(0,
492 "crtc_event:%d", priv->event_thread[i].crtc_id);
493 if (IS_ERR(priv->event_thread[i].worker)) {
494 ret = PTR_ERR(priv->event_thread[i].worker);
495 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
496 ret = PTR_ERR(priv->event_thread[i].worker);
500 sched_set_fifo(priv->event_thread[i].worker->task);
503 ret = drm_vblank_init(ddev, priv->num_crtcs);
505 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
510 pm_runtime_get_sync(dev);
511 ret = msm_irq_install(ddev, kms->irq);
512 pm_runtime_put_sync(dev);
514 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
519 ret = drm_dev_register(ddev, 0);
524 ret = msm_disp_snapshot_init(ddev);
526 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
528 drm_mode_config_reset(ddev);
530 #ifdef CONFIG_DRM_FBDEV_EMULATION
532 priv->fbdev = msm_fbdev_init(ddev);
535 ret = msm_debugfs_late_init(ddev);
539 drm_kms_helper_poll_init(ddev);
552 static void load_gpu(struct drm_device *dev)
554 static DEFINE_MUTEX(init_lock);
555 struct msm_drm_private *priv = dev->dev_private;
557 mutex_lock(&init_lock);
560 priv->gpu = adreno_load_gpu(dev);
562 mutex_unlock(&init_lock);
565 static int context_init(struct drm_device *dev, struct drm_file *file)
567 static atomic_t ident = ATOMIC_INIT(0);
568 struct msm_drm_private *priv = dev->dev_private;
569 struct msm_file_private *ctx;
571 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
575 INIT_LIST_HEAD(&ctx->submitqueues);
576 rwlock_init(&ctx->queuelock);
578 kref_init(&ctx->ref);
579 msm_submitqueue_init(dev, ctx);
581 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
582 file->driver_priv = ctx;
584 ctx->seqno = atomic_inc_return(&ident);
589 static int msm_open(struct drm_device *dev, struct drm_file *file)
591 /* For now, load gpu on open.. to avoid the requirement of having
592 * firmware in the initrd.
596 return context_init(dev, file);
599 static void context_close(struct msm_file_private *ctx)
601 msm_submitqueue_close(ctx);
602 msm_file_private_put(ctx);
605 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
607 struct msm_drm_private *priv = dev->dev_private;
608 struct msm_file_private *ctx = file->driver_priv;
611 * It is not possible to set sysprof param to non-zero if gpu
612 * is not initialized:
615 msm_file_private_set_sysprof(ctx, priv->gpu, 0);
620 int msm_crtc_enable_vblank(struct drm_crtc *crtc)
622 struct drm_device *dev = crtc->dev;
623 unsigned int pipe = crtc->index;
624 struct msm_drm_private *priv = dev->dev_private;
625 struct msm_kms *kms = priv->kms;
628 drm_dbg_vbl(dev, "crtc=%u", pipe);
629 return vblank_ctrl_queue_work(priv, pipe, true);
632 void msm_crtc_disable_vblank(struct drm_crtc *crtc)
634 struct drm_device *dev = crtc->dev;
635 unsigned int pipe = crtc->index;
636 struct msm_drm_private *priv = dev->dev_private;
637 struct msm_kms *kms = priv->kms;
640 drm_dbg_vbl(dev, "crtc=%u", pipe);
641 vblank_ctrl_queue_work(priv, pipe, false);
648 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
649 struct drm_file *file)
651 struct msm_drm_private *priv = dev->dev_private;
652 struct drm_msm_param *args = data;
655 /* for now, we just have 3d pipe.. eventually this would need to
656 * be more clever to dispatch to appropriate gpu module:
658 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
666 return gpu->funcs->get_param(gpu, file->driver_priv,
667 args->param, &args->value, &args->len);
670 static int msm_ioctl_set_param(struct drm_device *dev, void *data,
671 struct drm_file *file)
673 struct msm_drm_private *priv = dev->dev_private;
674 struct drm_msm_param *args = data;
677 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
685 return gpu->funcs->set_param(gpu, file->driver_priv,
686 args->param, args->value, args->len);
689 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
690 struct drm_file *file)
692 struct drm_msm_gem_new *args = data;
693 uint32_t flags = args->flags;
695 if (args->flags & ~MSM_BO_FLAGS) {
696 DRM_ERROR("invalid flags: %08x\n", args->flags);
701 * Uncached CPU mappings are deprecated, as of:
703 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)")
705 * So promote them to WC.
707 if (flags & MSM_BO_UNCACHED) {
708 flags &= ~MSM_BO_CACHED;
712 if (should_fail(&fail_gem_alloc, args->size))
715 return msm_gem_new_handle(dev, file, args->size,
716 args->flags, &args->handle, NULL);
719 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
721 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
724 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
725 struct drm_file *file)
727 struct drm_msm_gem_cpu_prep *args = data;
728 struct drm_gem_object *obj;
729 ktime_t timeout = to_ktime(args->timeout);
732 if (args->op & ~MSM_PREP_FLAGS) {
733 DRM_ERROR("invalid op: %08x\n", args->op);
737 obj = drm_gem_object_lookup(file, args->handle);
741 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
743 drm_gem_object_put(obj);
748 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
749 struct drm_file *file)
751 struct drm_msm_gem_cpu_fini *args = data;
752 struct drm_gem_object *obj;
755 obj = drm_gem_object_lookup(file, args->handle);
759 ret = msm_gem_cpu_fini(obj);
761 drm_gem_object_put(obj);
766 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
767 struct drm_file *file, struct drm_gem_object *obj,
770 struct msm_drm_private *priv = dev->dev_private;
771 struct msm_file_private *ctx = file->driver_priv;
776 if (should_fail(&fail_gem_iova, obj->size))
780 * Don't pin the memory here - just get an address so that userspace can
783 return msm_gem_get_iova(obj, ctx->aspace, iova);
786 static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,
787 struct drm_file *file, struct drm_gem_object *obj,
790 struct msm_drm_private *priv = dev->dev_private;
791 struct msm_file_private *ctx = file->driver_priv;
796 /* Only supported if per-process address space is supported: */
797 if (priv->gpu->aspace == ctx->aspace)
800 if (should_fail(&fail_gem_iova, obj->size))
803 return msm_gem_set_iova(obj, ctx->aspace, iova);
806 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
807 struct drm_file *file)
809 struct drm_msm_gem_info *args = data;
810 struct drm_gem_object *obj;
811 struct msm_gem_object *msm_obj;
817 switch (args->info) {
818 case MSM_INFO_GET_OFFSET:
819 case MSM_INFO_GET_IOVA:
820 case MSM_INFO_SET_IOVA:
821 /* value returned as immediate, not pointer, so len==0: */
825 case MSM_INFO_SET_NAME:
826 case MSM_INFO_GET_NAME:
832 obj = drm_gem_object_lookup(file, args->handle);
836 msm_obj = to_msm_bo(obj);
838 switch (args->info) {
839 case MSM_INFO_GET_OFFSET:
840 args->value = msm_gem_mmap_offset(obj);
842 case MSM_INFO_GET_IOVA:
843 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
845 case MSM_INFO_SET_IOVA:
846 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
848 case MSM_INFO_SET_NAME:
849 /* length check should leave room for terminating null: */
850 if (args->len >= sizeof(msm_obj->name)) {
854 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
856 msm_obj->name[0] = '\0';
860 msm_obj->name[args->len] = '\0';
861 for (i = 0; i < args->len; i++) {
862 if (!isprint(msm_obj->name[i])) {
863 msm_obj->name[i] = '\0';
868 case MSM_INFO_GET_NAME:
869 if (args->value && (args->len < strlen(msm_obj->name))) {
873 args->len = strlen(msm_obj->name);
875 if (copy_to_user(u64_to_user_ptr(args->value),
876 msm_obj->name, args->len))
882 drm_gem_object_put(obj);
887 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
890 struct dma_fence *fence;
893 if (fence_after(fence_id, queue->last_fence)) {
894 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
895 fence_id, queue->last_fence);
900 * Map submitqueue scoped "seqno" (which is actually an idr key)
901 * back to underlying dma-fence
903 * The fence is removed from the fence_idr when the submit is
904 * retired, so if the fence is not found it means there is nothing
907 ret = mutex_lock_interruptible(&queue->idr_lock);
910 fence = idr_find(&queue->fence_idr, fence_id);
912 fence = dma_fence_get_rcu(fence);
913 mutex_unlock(&queue->idr_lock);
918 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
921 } else if (ret != -ERESTARTSYS) {
925 dma_fence_put(fence);
930 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
931 struct drm_file *file)
933 struct msm_drm_private *priv = dev->dev_private;
934 struct drm_msm_wait_fence *args = data;
935 struct msm_gpu_submitqueue *queue;
939 DRM_ERROR("invalid pad: %08x\n", args->pad);
946 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
950 ret = wait_fence(queue, args->fence, to_ktime(args->timeout));
952 msm_submitqueue_put(queue);
957 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
958 struct drm_file *file)
960 struct drm_msm_gem_madvise *args = data;
961 struct drm_gem_object *obj;
964 switch (args->madv) {
965 case MSM_MADV_DONTNEED:
966 case MSM_MADV_WILLNEED:
972 obj = drm_gem_object_lookup(file, args->handle);
977 ret = msm_gem_madvise(obj, args->madv);
979 args->retained = ret;
983 drm_gem_object_put(obj);
989 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
990 struct drm_file *file)
992 struct drm_msm_submitqueue *args = data;
994 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
997 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
998 args->flags, &args->id);
1001 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
1002 struct drm_file *file)
1004 return msm_submitqueue_query(dev, file->driver_priv, data);
1007 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
1008 struct drm_file *file)
1010 u32 id = *(u32 *) data;
1012 return msm_submitqueue_remove(file->driver_priv, id);
1015 static const struct drm_ioctl_desc msm_ioctls[] = {
1016 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
1017 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW),
1018 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
1019 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
1020 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
1021 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
1022 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
1023 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
1024 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
1025 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
1026 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
1027 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
1030 static void msm_fop_show_fdinfo(struct seq_file *m, struct file *f)
1032 struct drm_file *file = f->private_data;
1033 struct drm_device *dev = file->minor->dev;
1034 struct msm_drm_private *priv = dev->dev_private;
1035 struct drm_printer p = drm_seq_file_printer(m);
1040 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, &p);
1043 static const struct file_operations fops = {
1044 .owner = THIS_MODULE,
1046 .show_fdinfo = msm_fop_show_fdinfo,
1049 static const struct drm_driver msm_driver = {
1050 .driver_features = DRIVER_GEM |
1056 .postclose = msm_postclose,
1057 .lastclose = drm_fb_helper_lastclose,
1058 .dumb_create = msm_gem_dumb_create,
1059 .dumb_map_offset = msm_gem_dumb_map_offset,
1060 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1061 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1062 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1063 .gem_prime_mmap = msm_gem_prime_mmap,
1064 #ifdef CONFIG_DEBUG_FS
1065 .debugfs_init = msm_debugfs_init,
1067 .ioctls = msm_ioctls,
1068 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1071 .desc = "MSM Snapdragon DRM",
1073 .major = MSM_VERSION_MAJOR,
1074 .minor = MSM_VERSION_MINOR,
1075 .patchlevel = MSM_VERSION_PATCHLEVEL,
1078 int msm_pm_prepare(struct device *dev)
1080 struct msm_drm_private *priv = dev_get_drvdata(dev);
1081 struct drm_device *ddev = priv ? priv->dev : NULL;
1083 if (!priv || !priv->kms)
1086 return drm_mode_config_helper_suspend(ddev);
1089 void msm_pm_complete(struct device *dev)
1091 struct msm_drm_private *priv = dev_get_drvdata(dev);
1092 struct drm_device *ddev = priv ? priv->dev : NULL;
1094 if (!priv || !priv->kms)
1097 drm_mode_config_helper_resume(ddev);
1100 static const struct dev_pm_ops msm_pm_ops = {
1101 .prepare = msm_pm_prepare,
1102 .complete = msm_pm_complete,
1106 * Componentized driver support:
1110 * Identify what components need to be added by parsing what remote-endpoints
1111 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1112 * is no external component that we need to add since LVDS is within MDP4
1115 static int add_components_mdp(struct device *master_dev,
1116 struct component_match **matchptr)
1118 struct device_node *np = master_dev->of_node;
1119 struct device_node *ep_node;
1121 for_each_endpoint_of_node(np, ep_node) {
1122 struct device_node *intf;
1123 struct of_endpoint ep;
1126 ret = of_graph_parse_endpoint(ep_node, &ep);
1128 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n");
1129 of_node_put(ep_node);
1134 * The LCDC/LVDS port on MDP4 is a speacial case where the
1135 * remote-endpoint isn't a component that we need to add
1137 if (of_device_is_compatible(np, "qcom,mdp4") &&
1142 * It's okay if some of the ports don't have a remote endpoint
1143 * specified. It just means that the port isn't connected to
1144 * any external interface.
1146 intf = of_graph_get_remote_port_parent(ep_node);
1150 if (of_device_is_available(intf))
1151 drm_of_component_match_add(master_dev, matchptr,
1152 component_compare_of, intf);
1161 * We don't know what's the best binding to link the gpu with the drm device.
1162 * Fow now, we just hunt for all the possible gpus that we support, and add them
1165 static const struct of_device_id msm_gpu_match[] = {
1166 { .compatible = "qcom,adreno" },
1167 { .compatible = "qcom,adreno-3xx" },
1168 { .compatible = "amd,imageon" },
1169 { .compatible = "qcom,kgsl-3d0" },
1173 static int add_gpu_components(struct device *dev,
1174 struct component_match **matchptr)
1176 struct device_node *np;
1178 np = of_find_matching_node(NULL, msm_gpu_match);
1182 if (of_device_is_available(np))
1183 drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1190 static int msm_drm_bind(struct device *dev)
1192 return msm_drm_init(dev, &msm_driver);
1195 static void msm_drm_unbind(struct device *dev)
1197 msm_drm_uninit(dev);
1200 const struct component_master_ops msm_drm_ops = {
1201 .bind = msm_drm_bind,
1202 .unbind = msm_drm_unbind,
1205 int msm_drv_probe(struct device *master_dev,
1206 int (*kms_init)(struct drm_device *dev))
1208 struct msm_drm_private *priv;
1209 struct component_match *match = NULL;
1212 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL);
1216 priv->kms_init = kms_init;
1217 dev_set_drvdata(master_dev, priv);
1219 /* Add mdp components if we have KMS. */
1221 ret = add_components_mdp(master_dev, &match);
1226 ret = add_gpu_components(master_dev, &match);
1230 /* on all devices that I am aware of, iommu's which can map
1231 * any address the cpu can see are used:
1233 ret = dma_set_mask_and_coherent(master_dev, ~0);
1237 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match);
1246 * Used only for headlesss GPU instances
1249 static int msm_pdev_probe(struct platform_device *pdev)
1251 return msm_drv_probe(&pdev->dev, NULL);
1254 static int msm_pdev_remove(struct platform_device *pdev)
1256 component_master_del(&pdev->dev, &msm_drm_ops);
1261 void msm_drv_shutdown(struct platform_device *pdev)
1263 struct msm_drm_private *priv = platform_get_drvdata(pdev);
1264 struct drm_device *drm = priv ? priv->dev : NULL;
1267 * Shutdown the hw if we're far enough along where things might be on.
1268 * If we run this too early, we'll end up panicking in any variety of
1269 * places. Since we don't register the drm device until late in
1270 * msm_drm_init, drm_dev->registered is used as an indicator that the
1271 * shutdown will be successful.
1273 if (drm && drm->registered)
1274 drm_atomic_helper_shutdown(drm);
1277 static struct platform_driver msm_platform_driver = {
1278 .probe = msm_pdev_probe,
1279 .remove = msm_pdev_remove,
1280 .shutdown = msm_drv_shutdown,
1287 static int __init msm_drm_register(void)
1296 msm_hdmi_register();
1299 msm_mdp4_register();
1300 msm_mdss_register();
1301 return platform_driver_register(&msm_platform_driver);
1304 static void __exit msm_drm_unregister(void)
1307 platform_driver_unregister(&msm_platform_driver);
1308 msm_mdss_unregister();
1309 msm_mdp4_unregister();
1310 msm_dp_unregister();
1311 msm_hdmi_unregister();
1312 adreno_unregister();
1313 msm_dsi_unregister();
1314 msm_mdp_unregister();
1315 msm_dpu_unregister();
1318 module_init(msm_drm_register);
1319 module_exit(msm_drm_unregister);
1321 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1322 MODULE_DESCRIPTION("MSM DRM Driver");
1323 MODULE_LICENSE("GPL");