1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/interrupt.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/of_irq.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/pm_opp.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spinlock.h>
22 #include <video/mipi_display.h>
31 #define DSI_RESET_TOGGLE_DELAY_MS 20
33 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
41 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
42 * makes all other registers 4-byte shifted down.
44 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
45 * older, we read the DSI_VERSION register without any shift(offset
46 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
47 * the case of DSI6G, this has to be zero (the offset points to a
48 * scratch register which we never touch)
51 ver = msm_readl(base + REG_DSI_VERSION);
53 /* older dsi host, there is no register shift */
54 ver = FIELD(ver, DSI_VERSION_MAJOR);
55 if (ver <= MSM_DSI_VER_MAJOR_V2) {
65 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
66 * registers are shifted down, read DSI_VERSION again with
69 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
70 ver = FIELD(ver, DSI_VERSION_MAJOR);
71 if (ver == MSM_DSI_VER_MAJOR_6G) {
74 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
82 #define DSI_ERR_STATE_ACK 0x0000
83 #define DSI_ERR_STATE_TIMEOUT 0x0001
84 #define DSI_ERR_STATE_DLN0_PHY 0x0002
85 #define DSI_ERR_STATE_FIFO 0x0004
86 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
87 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
88 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
90 #define DSI_CLK_CTRL_ENABLE_CLKS \
91 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
92 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
93 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
94 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
97 struct mipi_dsi_host base;
99 struct platform_device *pdev;
100 struct drm_device *dev;
104 void __iomem *ctrl_base;
105 phys_addr_t ctrl_size;
106 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
108 struct clk *bus_clks[DSI_BUS_CLK_MAX];
110 struct clk *byte_clk;
112 struct clk *pixel_clk;
113 struct clk *byte_clk_src;
114 struct clk *pixel_clk_src;
115 struct clk *byte_intf_clk;
121 /* DSI v2 specific clocks */
123 struct clk *esc_clk_src;
124 struct clk *dsi_clk_src;
128 struct gpio_desc *disp_en_gpio;
129 struct gpio_desc *te_gpio;
131 const struct msm_dsi_cfg_handler *cfg_hnd;
133 struct completion dma_comp;
134 struct completion video_comp;
135 struct mutex dev_mutex;
136 struct mutex cmd_mutex;
137 spinlock_t intr_lock; /* Protect interrupt ctrl register */
140 struct work_struct err_work;
141 struct work_struct hpd_work;
142 struct workqueue_struct *workqueue;
144 /* DSI 6G TX buffer*/
145 struct drm_gem_object *tx_gem_obj;
147 /* DSI v2 TX buffer */
149 dma_addr_t tx_buf_paddr;
157 struct drm_display_mode *mode;
159 /* connected device info */
160 struct device_node *device_node;
161 unsigned int channel;
163 enum mipi_dsi_pixel_format format;
164 unsigned long mode_flags;
166 /* lane data parsed via DT */
170 u32 dma_cmd_ctrl_restore;
178 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
181 case MIPI_DSI_FMT_RGB565: return 16;
182 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
183 case MIPI_DSI_FMT_RGB666:
184 case MIPI_DSI_FMT_RGB888:
189 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
191 return msm_readl(msm_host->ctrl_base + reg);
193 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
195 msm_writel(data, msm_host->ctrl_base + reg);
198 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
199 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
201 static const struct msm_dsi_cfg_handler *dsi_get_config(
202 struct msm_dsi_host *msm_host)
204 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
205 struct device *dev = &msm_host->pdev->dev;
206 struct regulator *gdsc_reg;
209 u32 major = 0, minor = 0;
211 gdsc_reg = regulator_get(dev, "gdsc");
212 if (IS_ERR(gdsc_reg)) {
213 pr_err("%s: cannot get gdsc\n", __func__);
217 ahb_clk = msm_clk_get(msm_host->pdev, "iface");
218 if (IS_ERR(ahb_clk)) {
219 pr_err("%s: cannot get interface clock\n", __func__);
223 pm_runtime_get_sync(dev);
225 ret = regulator_enable(gdsc_reg);
227 pr_err("%s: unable to enable gdsc\n", __func__);
231 ret = clk_prepare_enable(ahb_clk);
233 pr_err("%s: unable to enable ahb_clk\n", __func__);
237 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
239 pr_err("%s: Invalid version\n", __func__);
243 cfg_hnd = msm_dsi_cfg_get(major, minor);
245 DBG("%s: Version %x:%x\n", __func__, major, minor);
248 clk_disable_unprepare(ahb_clk);
250 regulator_disable(gdsc_reg);
251 pm_runtime_put_sync(dev);
253 regulator_put(gdsc_reg);
258 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
260 return container_of(host, struct msm_dsi_host, base);
263 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
265 struct regulator_bulk_data *s = msm_host->supplies;
266 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
267 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
271 for (i = num - 1; i >= 0; i--)
272 if (regs[i].disable_load >= 0)
273 regulator_set_load(s[i].consumer,
274 regs[i].disable_load);
276 regulator_bulk_disable(num, s);
279 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
281 struct regulator_bulk_data *s = msm_host->supplies;
282 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
283 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
287 for (i = 0; i < num; i++) {
288 if (regs[i].enable_load >= 0) {
289 ret = regulator_set_load(s[i].consumer,
290 regs[i].enable_load);
292 pr_err("regulator %d set op mode failed, %d\n",
299 ret = regulator_bulk_enable(num, s);
301 pr_err("regulator enable failed, %d\n", ret);
308 for (i--; i >= 0; i--)
309 regulator_set_load(s[i].consumer, regs[i].disable_load);
313 static int dsi_regulator_init(struct msm_dsi_host *msm_host)
315 struct regulator_bulk_data *s = msm_host->supplies;
316 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
317 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
320 for (i = 0; i < num; i++)
321 s[i].supply = regs[i].name;
323 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
325 pr_err("%s: failed to init regulator, ret=%d\n",
333 int dsi_clk_init_v2(struct msm_dsi_host *msm_host)
335 struct platform_device *pdev = msm_host->pdev;
338 msm_host->src_clk = msm_clk_get(pdev, "src");
340 if (IS_ERR(msm_host->src_clk)) {
341 ret = PTR_ERR(msm_host->src_clk);
342 pr_err("%s: can't find src clock. ret=%d\n",
344 msm_host->src_clk = NULL;
348 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
349 if (!msm_host->esc_clk_src) {
351 pr_err("%s: can't get esc clock parent. ret=%d\n",
356 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
357 if (!msm_host->dsi_clk_src) {
359 pr_err("%s: can't get src clock parent. ret=%d\n",
366 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
368 struct platform_device *pdev = msm_host->pdev;
371 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
372 if (IS_ERR(msm_host->byte_intf_clk)) {
373 ret = PTR_ERR(msm_host->byte_intf_clk);
374 pr_err("%s: can't find byte_intf clock. ret=%d\n",
381 static int dsi_clk_init(struct msm_dsi_host *msm_host)
383 struct platform_device *pdev = msm_host->pdev;
384 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
385 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
389 for (i = 0; i < cfg->num_bus_clks; i++) {
390 msm_host->bus_clks[i] = msm_clk_get(pdev,
391 cfg->bus_clk_names[i]);
392 if (IS_ERR(msm_host->bus_clks[i])) {
393 ret = PTR_ERR(msm_host->bus_clks[i]);
394 pr_err("%s: Unable to get %s clock, ret = %d\n",
395 __func__, cfg->bus_clk_names[i], ret);
400 /* get link and source clocks */
401 msm_host->byte_clk = msm_clk_get(pdev, "byte");
402 if (IS_ERR(msm_host->byte_clk)) {
403 ret = PTR_ERR(msm_host->byte_clk);
404 pr_err("%s: can't find dsi_byte clock. ret=%d\n",
406 msm_host->byte_clk = NULL;
410 msm_host->pixel_clk = msm_clk_get(pdev, "pixel");
411 if (IS_ERR(msm_host->pixel_clk)) {
412 ret = PTR_ERR(msm_host->pixel_clk);
413 pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
415 msm_host->pixel_clk = NULL;
419 msm_host->esc_clk = msm_clk_get(pdev, "core");
420 if (IS_ERR(msm_host->esc_clk)) {
421 ret = PTR_ERR(msm_host->esc_clk);
422 pr_err("%s: can't find dsi_esc clock. ret=%d\n",
424 msm_host->esc_clk = NULL;
428 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
429 if (IS_ERR(msm_host->byte_clk_src)) {
430 ret = PTR_ERR(msm_host->byte_clk_src);
431 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret);
435 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
436 if (IS_ERR(msm_host->pixel_clk_src)) {
437 ret = PTR_ERR(msm_host->pixel_clk_src);
438 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret);
442 if (cfg_hnd->ops->clk_init_ver)
443 ret = cfg_hnd->ops->clk_init_ver(msm_host);
448 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
450 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
453 DBG("id=%d", msm_host->id);
455 for (i = 0; i < cfg->num_bus_clks; i++) {
456 ret = clk_prepare_enable(msm_host->bus_clks[i]);
458 pr_err("%s: failed to enable bus clock %d ret %d\n",
467 clk_disable_unprepare(msm_host->bus_clks[i]);
472 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
474 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
479 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
480 clk_disable_unprepare(msm_host->bus_clks[i]);
483 int msm_dsi_runtime_suspend(struct device *dev)
485 struct platform_device *pdev = to_platform_device(dev);
486 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
487 struct mipi_dsi_host *host = msm_dsi->host;
488 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
490 if (!msm_host->cfg_hnd)
493 dsi_bus_clk_disable(msm_host);
498 int msm_dsi_runtime_resume(struct device *dev)
500 struct platform_device *pdev = to_platform_device(dev);
501 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
502 struct mipi_dsi_host *host = msm_dsi->host;
503 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
505 if (!msm_host->cfg_hnd)
508 return dsi_bus_clk_enable(msm_host);
511 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
515 DBG("Set clk rates: pclk=%d, byteclk=%d",
516 msm_host->mode->clock, msm_host->byte_clk_rate);
518 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev,
519 msm_host->byte_clk_rate);
521 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret);
525 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
527 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
531 if (msm_host->byte_intf_clk) {
532 ret = clk_set_rate(msm_host->byte_intf_clk,
533 msm_host->byte_clk_rate / 2);
535 pr_err("%s: Failed to set rate byte intf clk, %d\n",
545 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
549 ret = clk_prepare_enable(msm_host->esc_clk);
551 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
555 ret = clk_prepare_enable(msm_host->byte_clk);
557 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
561 ret = clk_prepare_enable(msm_host->pixel_clk);
563 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
567 if (msm_host->byte_intf_clk) {
568 ret = clk_prepare_enable(msm_host->byte_intf_clk);
570 pr_err("%s: Failed to enable byte intf clk\n",
572 goto byte_intf_clk_err;
579 clk_disable_unprepare(msm_host->pixel_clk);
581 clk_disable_unprepare(msm_host->byte_clk);
583 clk_disable_unprepare(msm_host->esc_clk);
588 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host)
592 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
593 msm_host->mode->clock, msm_host->byte_clk_rate,
594 msm_host->esc_clk_rate, msm_host->src_clk_rate);
596 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
598 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
602 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
604 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
608 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
610 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
614 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
616 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
623 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
627 ret = clk_prepare_enable(msm_host->byte_clk);
629 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
633 ret = clk_prepare_enable(msm_host->esc_clk);
635 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
639 ret = clk_prepare_enable(msm_host->src_clk);
641 pr_err("%s: Failed to enable dsi src clk\n", __func__);
645 ret = clk_prepare_enable(msm_host->pixel_clk);
647 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
654 clk_disable_unprepare(msm_host->src_clk);
656 clk_disable_unprepare(msm_host->esc_clk);
658 clk_disable_unprepare(msm_host->byte_clk);
663 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
665 /* Drop the performance state vote */
666 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0);
667 clk_disable_unprepare(msm_host->esc_clk);
668 clk_disable_unprepare(msm_host->pixel_clk);
669 if (msm_host->byte_intf_clk)
670 clk_disable_unprepare(msm_host->byte_intf_clk);
671 clk_disable_unprepare(msm_host->byte_clk);
674 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
676 clk_disable_unprepare(msm_host->pixel_clk);
677 clk_disable_unprepare(msm_host->src_clk);
678 clk_disable_unprepare(msm_host->esc_clk);
679 clk_disable_unprepare(msm_host->byte_clk);
682 static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
684 struct drm_display_mode *mode = msm_host->mode;
687 pclk_rate = mode->clock * 1000;
690 * For dual DSI mode, the current DRM mode has the complete width of the
691 * panel. Since, the complete panel is driven by two DSI controllers,
692 * the clock rates have to be split between the two dsi controllers.
693 * Adjust the byte and pixel clock rates for each dsi host accordingly.
701 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi)
703 u8 lanes = msm_host->lanes;
704 u32 bpp = dsi_get_bpp(msm_host->format);
705 u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_dual_dsi);
706 u64 pclk_bpp = (u64)pclk_rate * bpp;
709 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
713 do_div(pclk_bpp, (8 * lanes));
715 msm_host->pixel_clk_rate = pclk_rate;
716 msm_host->byte_clk_rate = pclk_bpp;
718 DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
719 msm_host->byte_clk_rate);
723 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi)
725 if (!msm_host->mode) {
726 pr_err("%s: mode not set\n", __func__);
730 dsi_calc_pclk(msm_host, is_dual_dsi);
731 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
735 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi)
737 u32 bpp = dsi_get_bpp(msm_host->format);
739 unsigned int esc_mhz, esc_div;
740 unsigned long byte_mhz;
742 dsi_calc_pclk(msm_host, is_dual_dsi);
744 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_dual_dsi) * bpp;
746 msm_host->src_clk_rate = pclk_bpp;
749 * esc clock is byte clock followed by a 4 bit divider,
750 * we need to find an escape clock frequency within the
751 * mipi DSI spec range within the maximum divider limit
752 * We iterate here between an escape clock frequencey
753 * between 20 Mhz to 5 Mhz and pick up the first one
754 * that can be supported by our divider
757 byte_mhz = msm_host->byte_clk_rate / 1000000;
759 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
760 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
763 * TODO: Ideally, we shouldn't know what sort of divider
764 * is available in mmss_cc, we're just assuming that
765 * it'll always be a 4 bit divider. Need to come up with
768 if (esc_div >= 1 && esc_div <= 16)
775 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
777 DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
778 msm_host->src_clk_rate);
783 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
788 spin_lock_irqsave(&msm_host->intr_lock, flags);
789 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
796 DBG("intr=%x enable=%d", intr, enable);
798 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
799 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
802 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
804 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
806 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
807 return NON_BURST_SYNCH_PULSE;
809 return NON_BURST_SYNCH_EVENT;
812 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
813 const enum mipi_dsi_pixel_format mipi_fmt)
816 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
817 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
818 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
819 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
820 default: return VID_DST_FORMAT_RGB888;
824 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
825 const enum mipi_dsi_pixel_format mipi_fmt)
828 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
829 case MIPI_DSI_FMT_RGB666_PACKED:
830 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666;
831 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
832 default: return CMD_DST_FORMAT_RGB888;
836 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
837 struct msm_dsi_phy_shared_timings *phy_shared_timings)
839 u32 flags = msm_host->mode_flags;
840 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
841 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
842 u32 data = 0, lane_ctrl = 0;
845 dsi_write(msm_host, REG_DSI_CTRL, 0);
849 if (flags & MIPI_DSI_MODE_VIDEO) {
850 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
851 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
852 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
853 data |= DSI_VID_CFG0_HFP_POWER_STOP;
854 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
855 data |= DSI_VID_CFG0_HBP_POWER_STOP;
856 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
857 data |= DSI_VID_CFG0_HSA_POWER_STOP;
858 /* Always set low power stop mode for BLLP
859 * to let command engine send packets
861 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
862 DSI_VID_CFG0_BLLP_POWER_STOP;
863 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
864 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
865 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
866 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
868 /* Do not swap RGB colors */
869 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
870 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
872 /* Do not swap RGB colors */
873 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
874 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
875 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
877 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
878 DSI_CMD_CFG1_WR_MEM_CONTINUE(
879 MIPI_DCS_WRITE_MEMORY_CONTINUE);
880 /* Always insert DCS command */
881 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
882 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
885 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
886 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
887 DSI_CMD_DMA_CTRL_LOW_POWER);
890 /* Always assume dedicated TE pin */
891 data |= DSI_TRIG_CTRL_TE;
892 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
893 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
894 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
895 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
896 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
897 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
898 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
900 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
901 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
902 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
904 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
905 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
906 phy_shared_timings->clk_pre_inc_by_2)
907 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
908 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
911 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET))
912 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
913 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
915 /* allow only ack-err-status to generate interrupt */
916 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
918 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
920 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
922 data = DSI_CTRL_CLK_EN;
924 DBG("lane number=%d", msm_host->lanes);
925 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
927 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
928 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
930 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) {
931 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
932 dsi_write(msm_host, REG_DSI_LANE_CTRL,
933 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
936 data |= DSI_CTRL_ENABLE;
938 dsi_write(msm_host, REG_DSI_CTRL, data);
941 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi)
943 struct drm_display_mode *mode = msm_host->mode;
944 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
945 u32 h_total = mode->htotal;
946 u32 v_total = mode->vtotal;
947 u32 hs_end = mode->hsync_end - mode->hsync_start;
948 u32 vs_end = mode->vsync_end - mode->vsync_start;
949 u32 ha_start = h_total - mode->hsync_start;
950 u32 ha_end = ha_start + mode->hdisplay;
951 u32 va_start = v_total - mode->vsync_start;
952 u32 va_end = va_start + mode->vdisplay;
953 u32 hdisplay = mode->hdisplay;
959 * For dual DSI mode, the current DRM mode has
960 * the complete width of the panel. Since, the complete
961 * panel is driven by two DSI controllers, the horizontal
962 * timings have to be split between the two dsi controllers.
963 * Adjust the DSI host timing values accordingly.
973 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
974 dsi_write(msm_host, REG_DSI_ACTIVE_H,
975 DSI_ACTIVE_H_START(ha_start) |
976 DSI_ACTIVE_H_END(ha_end));
977 dsi_write(msm_host, REG_DSI_ACTIVE_V,
978 DSI_ACTIVE_V_START(va_start) |
979 DSI_ACTIVE_V_END(va_end));
980 dsi_write(msm_host, REG_DSI_TOTAL,
981 DSI_TOTAL_H_TOTAL(h_total - 1) |
982 DSI_TOTAL_V_TOTAL(v_total - 1));
984 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
985 DSI_ACTIVE_HSYNC_START(hs_start) |
986 DSI_ACTIVE_HSYNC_END(hs_end));
987 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
988 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
989 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
990 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
991 } else { /* command mode */
992 /* image data and 1 byte write_memory_start cmd */
993 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
995 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
996 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
997 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(
999 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(
1000 MIPI_DSI_DCS_LONG_WRITE));
1002 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
1003 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) |
1004 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay));
1008 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
1010 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1011 wmb(); /* clocks need to be enabled before reset */
1013 dsi_write(msm_host, REG_DSI_RESET, 1);
1014 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1015 dsi_write(msm_host, REG_DSI_RESET, 0);
1018 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
1019 bool video_mode, bool enable)
1023 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
1026 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
1027 DSI_CTRL_CMD_MODE_EN);
1028 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
1029 DSI_IRQ_MASK_VIDEO_DONE, 0);
1032 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
1033 } else { /* command mode */
1034 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
1035 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
1037 dsi_ctrl |= DSI_CTRL_ENABLE;
1040 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
1043 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
1047 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
1050 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
1052 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
1054 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
1057 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
1060 struct device *dev = &msm_host->pdev->dev;
1062 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
1064 reinit_completion(&msm_host->video_comp);
1066 ret = wait_for_completion_timeout(&msm_host->video_comp,
1067 msecs_to_jiffies(70));
1070 DRM_DEV_ERROR(dev, "wait for video done timed out\n");
1072 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
1075 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
1077 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
1080 if (msm_host->power_on && msm_host->enabled) {
1081 dsi_wait4video_done(msm_host);
1082 /* delay 4 ms to skip BLLP */
1083 usleep_range(2000, 4000);
1087 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size)
1089 struct drm_device *dev = msm_host->dev;
1090 struct msm_drm_private *priv = dev->dev_private;
1094 data = msm_gem_kernel_new(dev, size, MSM_BO_WC,
1096 &msm_host->tx_gem_obj, &iova);
1099 msm_host->tx_gem_obj = NULL;
1100 return PTR_ERR(data);
1103 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem");
1105 msm_host->tx_size = msm_host->tx_gem_obj->size;
1110 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size)
1112 struct drm_device *dev = msm_host->dev;
1114 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1115 &msm_host->tx_buf_paddr, GFP_KERNEL);
1116 if (!msm_host->tx_buf)
1119 msm_host->tx_size = size;
1124 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1126 struct drm_device *dev = msm_host->dev;
1127 struct msm_drm_private *priv;
1130 * This is possible if we're tearing down before we've had a chance to
1131 * fully initialize. A very real possibility if our probe is deferred,
1132 * in which case we'll hit msm_dsi_host_destroy() without having run
1133 * through the dsi_tx_buf_alloc().
1138 priv = dev->dev_private;
1139 if (msm_host->tx_gem_obj) {
1140 msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace);
1141 drm_gem_object_put(msm_host->tx_gem_obj);
1142 msm_host->tx_gem_obj = NULL;
1145 if (msm_host->tx_buf)
1146 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1147 msm_host->tx_buf_paddr);
1150 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host)
1152 return msm_gem_get_vaddr(msm_host->tx_gem_obj);
1155 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host)
1157 return msm_host->tx_buf;
1160 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host)
1162 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1166 * prepare cmd buffer to be txed
1168 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1169 const struct mipi_dsi_msg *msg)
1171 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1172 struct mipi_dsi_packet packet;
1177 ret = mipi_dsi_create_packet(&packet, msg);
1179 pr_err("%s: create packet failed, %d\n", __func__, ret);
1182 len = (packet.size + 3) & (~0x3);
1184 if (len > msm_host->tx_size) {
1185 pr_err("%s: packet size is too big\n", __func__);
1189 data = cfg_hnd->ops->tx_buf_get(msm_host);
1191 ret = PTR_ERR(data);
1192 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1196 /* MSM specific command format in memory */
1197 data[0] = packet.header[1];
1198 data[1] = packet.header[2];
1199 data[2] = packet.header[0];
1200 data[3] = BIT(7); /* Last packet */
1201 if (mipi_dsi_packet_format_is_long(msg->type))
1203 if (msg->rx_buf && msg->rx_len)
1207 if (packet.payload && packet.payload_length)
1208 memcpy(data + 4, packet.payload, packet.payload_length);
1210 /* Append 0xff to the end */
1211 if (packet.size < len)
1212 memset(data + packet.size, 0xff, len - packet.size);
1214 if (cfg_hnd->ops->tx_buf_put)
1215 cfg_hnd->ops->tx_buf_put(msm_host);
1221 * dsi_short_read1_resp: 1 parameter
1223 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1225 u8 *data = msg->rx_buf;
1226 if (data && (msg->rx_len >= 1)) {
1227 *data = buf[1]; /* strip out dcs type */
1230 pr_err("%s: read data does not match with rx_buf len %zu\n",
1231 __func__, msg->rx_len);
1237 * dsi_short_read2_resp: 2 parameter
1239 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1241 u8 *data = msg->rx_buf;
1242 if (data && (msg->rx_len >= 2)) {
1243 data[0] = buf[1]; /* strip out dcs type */
1247 pr_err("%s: read data does not match with rx_buf len %zu\n",
1248 __func__, msg->rx_len);
1253 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1255 /* strip out 4 byte dcs header */
1256 if (msg->rx_buf && msg->rx_len)
1257 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1262 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1264 struct drm_device *dev = msm_host->dev;
1265 struct msm_drm_private *priv = dev->dev_private;
1270 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj,
1271 priv->kms->aspace, dma_base);
1274 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1279 *dma_base = msm_host->tx_buf_paddr;
1283 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1285 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1290 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base);
1292 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1296 reinit_completion(&msm_host->dma_comp);
1298 dsi_wait4video_eng_busy(msm_host);
1300 triggered = msm_dsi_manager_cmd_xfer_trigger(
1301 msm_host->id, dma_base, len);
1303 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1304 msecs_to_jiffies(200));
1316 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1317 u8 *buf, int rx_byte, int pkt_size)
1323 int repeated_bytes = 0;
1324 int buf_offset = buf - msm_host->rx_buf;
1327 cnt = (rx_byte + 3) >> 2;
1329 cnt = 4; /* 4 x 32 bits registers only */
1334 read_cnt = pkt_size + 6;
1337 * In case of multiple reads from the panel, after the first read, there
1338 * is possibility that there are some bytes in the payload repeating in
1339 * the RDBK_DATA registers. Since we read all the parameters from the
1340 * panel right from the first byte for every pass. We need to skip the
1341 * repeating bytes and then append the new parameters to the rx buffer.
1343 if (read_cnt > 16) {
1345 /* Any data more than 16 bytes will be shifted out.
1346 * The temp read buffer should already contain these bytes.
1347 * The remaining bytes in read buffer are the repeated bytes.
1349 bytes_shifted = read_cnt - 16;
1350 repeated_bytes = buf_offset - bytes_shifted;
1353 for (i = cnt - 1; i >= 0; i--) {
1354 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1355 *temp++ = ntohl(data); /* to host byte order */
1356 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1359 for (i = repeated_bytes; i < 16; i++)
1365 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1366 const struct mipi_dsi_msg *msg)
1369 int bllp_len = msm_host->mode->hdisplay *
1370 dsi_get_bpp(msm_host->format) / 8;
1372 len = dsi_cmd_dma_add(msm_host, msg);
1374 pr_err("%s: failed to add cmd type = 0x%x\n",
1375 __func__, msg->type);
1379 /* for video mode, do not send cmds more than
1380 * one pixel line, since it only transmit it
1383 /* TODO: if the command is sent in LP mode, the bit rate is only
1384 * half of esc clk rate. In this case, if the video is already
1385 * actively streaming, we need to check more carefully if the
1386 * command can be fit into one BLLP.
1388 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1389 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1394 ret = dsi_cmd_dma_tx(msm_host, len);
1396 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1397 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1404 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1408 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1410 data1 &= ~DSI_CTRL_ENABLE;
1411 dsi_write(msm_host, REG_DSI_CTRL, data1);
1413 * dsi controller need to be disabled before
1418 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1419 wmb(); /* make sure clocks enabled */
1421 /* dsi controller can only be reset while clocks are running */
1422 dsi_write(msm_host, REG_DSI_RESET, 1);
1423 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1424 dsi_write(msm_host, REG_DSI_RESET, 0);
1425 wmb(); /* controller out of reset */
1426 dsi_write(msm_host, REG_DSI_CTRL, data0);
1427 wmb(); /* make sure dsi controller enabled again */
1430 static void dsi_hpd_worker(struct work_struct *work)
1432 struct msm_dsi_host *msm_host =
1433 container_of(work, struct msm_dsi_host, hpd_work);
1435 drm_helper_hpd_irq_event(msm_host->dev);
1438 static void dsi_err_worker(struct work_struct *work)
1440 struct msm_dsi_host *msm_host =
1441 container_of(work, struct msm_dsi_host, err_work);
1442 u32 status = msm_host->err_work_state;
1444 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1445 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1446 dsi_sw_reset_restore(msm_host);
1448 /* It is safe to clear here because error irq is disabled. */
1449 msm_host->err_work_state = 0;
1451 /* enable dsi error interrupt */
1452 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1455 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1459 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1462 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1463 /* Writing of an extra 0 needed to clear error bits */
1464 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1465 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1469 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1473 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1476 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1477 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1481 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1485 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1487 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1488 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1489 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1490 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1491 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1492 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1493 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1497 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1501 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1503 /* fifo underflow, overflow */
1505 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1506 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1507 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1508 msm_host->err_work_state |=
1509 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1513 static void dsi_status(struct msm_dsi_host *msm_host)
1517 status = dsi_read(msm_host, REG_DSI_STATUS0);
1519 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1520 dsi_write(msm_host, REG_DSI_STATUS0, status);
1521 msm_host->err_work_state |=
1522 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1526 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1530 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1532 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1533 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1534 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1538 static void dsi_error(struct msm_dsi_host *msm_host)
1540 /* disable dsi error interrupt */
1541 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1543 dsi_clk_status(msm_host);
1544 dsi_fifo_status(msm_host);
1545 dsi_ack_err_status(msm_host);
1546 dsi_timeout_status(msm_host);
1547 dsi_status(msm_host);
1548 dsi_dln0_phy_err(msm_host);
1550 queue_work(msm_host->workqueue, &msm_host->err_work);
1553 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1555 struct msm_dsi_host *msm_host = ptr;
1557 unsigned long flags;
1559 if (!msm_host->ctrl_base)
1562 spin_lock_irqsave(&msm_host->intr_lock, flags);
1563 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1564 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1565 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1567 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1569 if (isr & DSI_IRQ_ERROR)
1570 dsi_error(msm_host);
1572 if (isr & DSI_IRQ_VIDEO_DONE)
1573 complete(&msm_host->video_comp);
1575 if (isr & DSI_IRQ_CMD_DMA_DONE)
1576 complete(&msm_host->dma_comp);
1581 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1582 struct device *panel_device)
1584 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1587 if (IS_ERR(msm_host->disp_en_gpio)) {
1588 DBG("cannot get disp-enable-gpios %ld",
1589 PTR_ERR(msm_host->disp_en_gpio));
1590 return PTR_ERR(msm_host->disp_en_gpio);
1593 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1595 if (IS_ERR(msm_host->te_gpio)) {
1596 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1597 return PTR_ERR(msm_host->te_gpio);
1603 static int dsi_host_attach(struct mipi_dsi_host *host,
1604 struct mipi_dsi_device *dsi)
1606 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1609 if (dsi->lanes > msm_host->num_data_lanes)
1612 msm_host->channel = dsi->channel;
1613 msm_host->lanes = dsi->lanes;
1614 msm_host->format = dsi->format;
1615 msm_host->mode_flags = dsi->mode_flags;
1617 /* Some gpios defined in panel DT need to be controlled by host */
1618 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1622 DBG("id=%d", msm_host->id);
1624 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1629 static int dsi_host_detach(struct mipi_dsi_host *host,
1630 struct mipi_dsi_device *dsi)
1632 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1634 msm_host->device_node = NULL;
1636 DBG("id=%d", msm_host->id);
1638 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1643 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1644 const struct mipi_dsi_msg *msg)
1646 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1649 if (!msg || !msm_host->power_on)
1652 mutex_lock(&msm_host->cmd_mutex);
1653 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1654 mutex_unlock(&msm_host->cmd_mutex);
1659 static const struct mipi_dsi_host_ops dsi_host_ops = {
1660 .attach = dsi_host_attach,
1661 .detach = dsi_host_detach,
1662 .transfer = dsi_host_transfer,
1666 * List of supported physical to logical lane mappings.
1667 * For example, the 2nd entry represents the following mapping:
1669 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1671 static const int supported_data_lane_swaps[][4] = {
1682 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1683 struct device_node *ep)
1685 struct device *dev = &msm_host->pdev->dev;
1686 struct property *prop;
1688 int ret, i, len, num_lanes;
1690 prop = of_find_property(ep, "data-lanes", &len);
1693 "failed to find data lane mapping, using default\n");
1697 num_lanes = len / sizeof(u32);
1699 if (num_lanes < 1 || num_lanes > 4) {
1700 DRM_DEV_ERROR(dev, "bad number of data lanes\n");
1704 msm_host->num_data_lanes = num_lanes;
1706 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1709 DRM_DEV_ERROR(dev, "failed to read lane data\n");
1714 * compare DT specified physical-logical lane mappings with the ones
1715 * supported by hardware
1717 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1718 const int *swap = supported_data_lane_swaps[i];
1722 * the data-lanes array we get from DT has a logical->physical
1723 * mapping. The "data lane swap" register field represents
1724 * supported configurations in a physical->logical mapping.
1725 * Translate the DT mapping to what we understand and find a
1726 * configuration that works.
1728 for (j = 0; j < num_lanes; j++) {
1729 if (lane_map[j] < 0 || lane_map[j] > 3)
1730 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n",
1733 if (swap[lane_map[j]] != j)
1737 if (j == num_lanes) {
1738 msm_host->dlane_swap = i;
1746 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1748 struct device *dev = &msm_host->pdev->dev;
1749 struct device_node *np = dev->of_node;
1750 struct device_node *endpoint, *device_node;
1754 * Get the endpoint of the output port of the DSI host. In our case,
1755 * this is mapped to port number with reg = 1. Don't return an error if
1756 * the remote endpoint isn't defined. It's possible that there is
1757 * nothing connected to the dsi output.
1759 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1761 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__);
1765 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1767 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n",
1773 /* Get panel node from the output port's endpoint data */
1774 device_node = of_graph_get_remote_node(np, 1, 0);
1776 DRM_DEV_DEBUG(dev, "%s: no valid device\n", __func__);
1781 msm_host->device_node = device_node;
1783 if (of_property_read_bool(np, "syscon-sfpb")) {
1784 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1786 if (IS_ERR(msm_host->sfpb)) {
1787 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n",
1789 ret = PTR_ERR(msm_host->sfpb);
1793 of_node_put(device_node);
1796 of_node_put(endpoint);
1801 static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1803 struct platform_device *pdev = msm_host->pdev;
1804 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1805 struct resource *res;
1808 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1812 for (i = 0; i < cfg->num_dsi; i++) {
1813 if (cfg->io_start[i] == res->start)
1820 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1822 struct msm_dsi_host *msm_host = NULL;
1823 struct platform_device *pdev = msm_dsi->pdev;
1826 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1832 msm_host->pdev = pdev;
1833 msm_dsi->host = &msm_host->base;
1835 ret = dsi_host_parse_dt(msm_host);
1837 pr_err("%s: failed to parse dt\n", __func__);
1841 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", "DSI CTRL", &msm_host->ctrl_size);
1842 if (IS_ERR(msm_host->ctrl_base)) {
1843 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1844 ret = PTR_ERR(msm_host->ctrl_base);
1848 pm_runtime_enable(&pdev->dev);
1850 msm_host->cfg_hnd = dsi_get_config(msm_host);
1851 if (!msm_host->cfg_hnd) {
1853 pr_err("%s: get config failed\n", __func__);
1857 msm_host->id = dsi_host_get_id(msm_host);
1858 if (msm_host->id < 0) {
1860 pr_err("%s: unable to identify DSI host index\n", __func__);
1864 /* fixup base address by io offset */
1865 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1867 ret = dsi_regulator_init(msm_host);
1869 pr_err("%s: regulator init failed\n", __func__);
1873 ret = dsi_clk_init(msm_host);
1875 pr_err("%s: unable to initialize dsi clks\n", __func__);
1879 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1880 if (!msm_host->rx_buf) {
1882 pr_err("%s: alloc rx temp buf failed\n", __func__);
1886 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte");
1889 /* OPP table is optional */
1890 ret = devm_pm_opp_of_add_table(&pdev->dev);
1891 if (ret && ret != -ENODEV) {
1892 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1896 init_completion(&msm_host->dma_comp);
1897 init_completion(&msm_host->video_comp);
1898 mutex_init(&msm_host->dev_mutex);
1899 mutex_init(&msm_host->cmd_mutex);
1900 spin_lock_init(&msm_host->intr_lock);
1902 /* setup workqueue */
1903 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1904 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1905 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker);
1907 msm_dsi->id = msm_host->id;
1909 DBG("Dsi Host %d initialized", msm_host->id);
1916 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1918 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1921 dsi_tx_buf_free(msm_host);
1922 if (msm_host->workqueue) {
1923 flush_workqueue(msm_host->workqueue);
1924 destroy_workqueue(msm_host->workqueue);
1925 msm_host->workqueue = NULL;
1928 mutex_destroy(&msm_host->cmd_mutex);
1929 mutex_destroy(&msm_host->dev_mutex);
1931 pm_runtime_disable(&msm_host->pdev->dev);
1934 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1935 struct drm_device *dev)
1937 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1938 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1939 struct platform_device *pdev = msm_host->pdev;
1942 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1943 if (msm_host->irq < 0) {
1944 ret = msm_host->irq;
1945 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret);
1949 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1950 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1951 "dsi_isr", msm_host);
1953 DRM_DEV_ERROR(&pdev->dev, "failed to request IRQ%u: %d\n",
1954 msm_host->irq, ret);
1958 msm_host->dev = dev;
1959 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
1961 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1968 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1970 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1973 /* Register mipi dsi host */
1974 if (!msm_host->registered) {
1975 host->dev = &msm_host->pdev->dev;
1976 host->ops = &dsi_host_ops;
1977 ret = mipi_dsi_host_register(host);
1981 msm_host->registered = true;
1983 /* If the panel driver has not been probed after host register,
1984 * we should defer the host's probe.
1985 * It makes sure panel is connected when fbcon detects
1986 * connector status and gets the proper display mode to
1987 * create framebuffer.
1988 * Don't try to defer if there is nothing connected to the dsi
1991 if (check_defer && msm_host->device_node) {
1992 if (IS_ERR(of_drm_find_panel(msm_host->device_node)))
1993 if (!of_drm_find_bridge(msm_host->device_node))
1994 return -EPROBE_DEFER;
2001 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
2003 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2005 if (msm_host->registered) {
2006 mipi_dsi_host_unregister(host);
2009 msm_host->registered = false;
2013 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
2014 const struct mipi_dsi_msg *msg)
2016 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2017 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2019 /* TODO: make sure dsi_cmd_mdp is idle.
2020 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
2021 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
2022 * How to handle the old versions? Wait for mdp cmd done?
2026 * mdss interrupt is generated in mdp core clock domain
2027 * mdp clock need to be enabled to receive dsi interrupt
2029 pm_runtime_get_sync(&msm_host->pdev->dev);
2030 cfg_hnd->ops->link_clk_set_rate(msm_host);
2031 cfg_hnd->ops->link_clk_enable(msm_host);
2033 /* TODO: vote for bus bandwidth */
2035 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2036 dsi_set_tx_power_mode(0, msm_host);
2038 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
2039 dsi_write(msm_host, REG_DSI_CTRL,
2040 msm_host->dma_cmd_ctrl_restore |
2041 DSI_CTRL_CMD_MODE_EN |
2043 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
2048 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
2049 const struct mipi_dsi_msg *msg)
2051 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2052 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2054 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
2055 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
2057 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2058 dsi_set_tx_power_mode(1, msm_host);
2060 /* TODO: unvote for bus bandwidth */
2062 cfg_hnd->ops->link_clk_disable(msm_host);
2063 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2066 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
2067 const struct mipi_dsi_msg *msg)
2069 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2071 return dsi_cmds2buf_tx(msm_host, msg);
2074 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
2075 const struct mipi_dsi_msg *msg)
2077 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2078 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2079 int data_byte, rx_byte, dlen, end;
2080 int short_response, diff, pkt_size, ret = 0;
2082 int rlen = msg->rx_len;
2091 data_byte = 10; /* first read */
2092 if (rlen < data_byte)
2095 pkt_size = data_byte;
2096 rx_byte = data_byte + 6; /* 4 header + 2 crc */
2099 buf = msm_host->rx_buf;
2102 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
2103 struct mipi_dsi_msg max_pkt_size_msg = {
2104 .channel = msg->channel,
2105 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
2110 DBG("rlen=%d pkt_size=%d rx_byte=%d",
2111 rlen, pkt_size, rx_byte);
2113 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
2115 pr_err("%s: Set max pkt size failed, %d\n",
2120 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
2121 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
2122 /* Clear the RDBK_DATA registers */
2123 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
2124 DSI_RDBK_DATA_CTRL_CLR);
2125 wmb(); /* make sure the RDBK registers are cleared */
2126 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
2127 wmb(); /* release cleared status before transfer */
2130 ret = dsi_cmds2buf_tx(msm_host, msg);
2131 if (ret < msg->tx_len) {
2132 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
2137 * once cmd_dma_done interrupt received,
2138 * return data from client is ready and stored
2139 * at RDBK_DATA register already
2140 * since rx fifo is 16 bytes, dcs header is kept at first loop,
2141 * after that dcs header lost during shift into registers
2143 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
2151 if (rlen <= data_byte) {
2152 diff = data_byte - rlen;
2160 dlen -= 2; /* 2 crc */
2162 buf += dlen; /* next start position */
2163 data_byte = 14; /* NOT first read */
2164 if (rlen < data_byte)
2167 pkt_size += data_byte;
2168 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2173 * For single Long read, if the requested rlen < 10,
2174 * we need to shift the start position of rx
2175 * data buffer to skip the bytes which are not
2178 if (pkt_size < 10 && !short_response)
2179 buf = msm_host->rx_buf + (10 - rlen);
2181 buf = msm_host->rx_buf;
2185 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2186 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2189 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2190 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2191 ret = dsi_short_read1_resp(buf, msg);
2193 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2194 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2195 ret = dsi_short_read2_resp(buf, msg);
2197 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2198 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2199 ret = dsi_long_read_resp(buf, msg);
2202 pr_warn("%s:Invalid response cmd\n", __func__);
2209 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2212 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2214 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2215 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2216 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2218 /* Make sure trigger happens */
2222 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
2223 struct msm_dsi_phy *src_phy)
2225 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2226 struct clk *byte_clk_provider, *pixel_clk_provider;
2229 ret = msm_dsi_phy_get_clk_provider(src_phy,
2230 &byte_clk_provider, &pixel_clk_provider);
2232 pr_info("%s: can't get provider from pll, don't set parent\n",
2237 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
2239 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2244 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
2246 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2251 if (msm_host->dsi_clk_src) {
2252 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
2254 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2260 if (msm_host->esc_clk_src) {
2261 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
2263 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2273 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
2275 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2278 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
2279 /* Make sure fully reset */
2282 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
2286 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2287 struct msm_dsi_phy_clk_request *clk_req,
2290 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2291 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2294 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_dual_dsi);
2296 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2300 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2301 clk_req->escclk_rate = msm_host->esc_clk_rate;
2304 int msm_dsi_host_enable(struct mipi_dsi_host *host)
2306 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2308 dsi_op_mode_config(msm_host,
2309 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2311 /* TODO: clock should be turned off for command mode,
2312 * and only turned on before MDP START.
2313 * This part of code should be enabled once mdp driver support it.
2315 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
2316 * dsi_link_clk_disable(msm_host);
2317 * pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2320 msm_host->enabled = true;
2324 int msm_dsi_host_disable(struct mipi_dsi_host *host)
2326 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2328 msm_host->enabled = false;
2329 dsi_op_mode_config(msm_host,
2330 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2332 /* Since we have disabled INTF, the video engine won't stop so that
2333 * the cmd engine will be blocked.
2334 * Reset to disable video engine so that we can send off cmd.
2336 dsi_sw_reset(msm_host);
2341 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2343 enum sfpb_ahb_arb_master_port_en en;
2345 if (!msm_host->sfpb)
2348 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2350 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2351 SFPB_GPREG_MASTER_PORT_EN__MASK,
2352 SFPB_GPREG_MASTER_PORT_EN(en));
2355 int msm_dsi_host_power_on(struct mipi_dsi_host *host,
2356 struct msm_dsi_phy_shared_timings *phy_shared_timings,
2359 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2360 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2363 mutex_lock(&msm_host->dev_mutex);
2364 if (msm_host->power_on) {
2365 DBG("dsi host already on");
2369 msm_dsi_sfpb_config(msm_host, true);
2371 ret = dsi_host_regulator_enable(msm_host);
2373 pr_err("%s:Failed to enable vregs.ret=%d\n",
2378 pm_runtime_get_sync(&msm_host->pdev->dev);
2379 ret = cfg_hnd->ops->link_clk_set_rate(msm_host);
2381 ret = cfg_hnd->ops->link_clk_enable(msm_host);
2383 pr_err("%s: failed to enable link clocks. ret=%d\n",
2385 goto fail_disable_reg;
2388 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2390 pr_err("%s: failed to set pinctrl default state, %d\n",
2392 goto fail_disable_clk;
2395 dsi_timing_setup(msm_host, is_dual_dsi);
2396 dsi_sw_reset(msm_host);
2397 dsi_ctrl_config(msm_host, true, phy_shared_timings);
2399 if (msm_host->disp_en_gpio)
2400 gpiod_set_value(msm_host->disp_en_gpio, 1);
2402 msm_host->power_on = true;
2403 mutex_unlock(&msm_host->dev_mutex);
2408 cfg_hnd->ops->link_clk_disable(msm_host);
2409 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2411 dsi_host_regulator_disable(msm_host);
2413 mutex_unlock(&msm_host->dev_mutex);
2417 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2419 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2420 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2422 mutex_lock(&msm_host->dev_mutex);
2423 if (!msm_host->power_on) {
2424 DBG("dsi host already off");
2428 dsi_ctrl_config(msm_host, false, NULL);
2430 if (msm_host->disp_en_gpio)
2431 gpiod_set_value(msm_host->disp_en_gpio, 0);
2433 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2435 cfg_hnd->ops->link_clk_disable(msm_host);
2436 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2438 dsi_host_regulator_disable(msm_host);
2440 msm_dsi_sfpb_config(msm_host, false);
2444 msm_host->power_on = false;
2447 mutex_unlock(&msm_host->dev_mutex);
2451 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2452 const struct drm_display_mode *mode)
2454 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2456 if (msm_host->mode) {
2457 drm_mode_destroy(msm_host->dev, msm_host->mode);
2458 msm_host->mode = NULL;
2461 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2462 if (!msm_host->mode) {
2463 pr_err("%s: cannot duplicate mode\n", __func__);
2470 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host)
2472 return of_drm_find_panel(to_msm_dsi_host(host)->device_node);
2475 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host)
2477 return to_msm_dsi_host(host)->mode_flags;
2480 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
2482 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2484 return of_drm_find_bridge(msm_host->device_node);
2487 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host)
2489 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2491 pm_runtime_get_sync(&msm_host->pdev->dev);
2493 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size,
2494 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id);
2496 pm_runtime_put_sync(&msm_host->pdev->dev);