drivers/gpu/drm/msm/dp/dp_parser.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/of_gpio.h>
   7 #include <linux/phy/phy.h>
   8
   9 #include <drm/drm_of.h>
  10 #include <drm/drm_print.h>
  11
  12 #include "dp_parser.h"
  13 #include "dp_reg.h"
  14
  15 #define DP_DEFAULT_AHB_OFFSET   0x0000
  16 #define DP_DEFAULT_AHB_SIZE     0x0200
  17 #define DP_DEFAULT_AUX_OFFSET   0x0200
  18 #define DP_DEFAULT_AUX_SIZE     0x0200
  19 #define DP_DEFAULT_LINK_OFFSET  0x0400
  20 #define DP_DEFAULT_LINK_SIZE    0x0C00
  21 #define DP_DEFAULT_P0_OFFSET    0x1000
  22 #define DP_DEFAULT_P0_SIZE      0x0400
  23
  24 static const struct dp_regulator_cfg sdm845_dp_reg_cfg = {
  25         .num = 2,
  26         .regs = {
  27                 {"vdda-1p2", 21800, 4 },        /* 1.2 V */
  28                 {"vdda-0p9", 36000, 32 },       /* 0.9 V */
  29         },
  30 };
  31
  32 static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len)
  33 {
  34         struct resource *res;
  35         void __iomem *base;
  36
  37         base = devm_platform_get_and_ioremap_resource(pdev, idx, &res);
  38         if (!IS_ERR(base))
  39                 *len = resource_size(res);
  40
  41         return base;
  42 }
  43
  44 static int dp_parser_ctrl_res(struct dp_parser *parser)
  45 {
  46         struct platform_device *pdev = parser->pdev;
  47         struct dp_io *io = &parser->io;
  48         struct dss_io_data *dss = &io->dp_controller;
  49
  50         dss->ahb.base = dp_ioremap(pdev, 0, &dss->ahb.len);
  51         if (IS_ERR(dss->ahb.base))
  52                 return PTR_ERR(dss->ahb.base);
  53
  54         dss->aux.base = dp_ioremap(pdev, 1, &dss->aux.len);
  55         if (IS_ERR(dss->aux.base)) {
  56                 /*
  57                  * The initial binding had a single reg, but in order to
  58                  * support variation in the sub-region sizes this was split.
  59                  * dp_ioremap() will fail with -EINVAL here if only a single
  60                  * reg is specified, so fill in the sub-region offsets and
  61                  * lengths based on this single region.
  62                  */
  63                 if (PTR_ERR(dss->aux.base) == -EINVAL) {
  64                         if (dss->ahb.len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) {
  65                                 DRM_ERROR("legacy memory region not large enough\n");
  66                                 return -EINVAL;
  67                         }
  68
  69                         dss->ahb.len = DP_DEFAULT_AHB_SIZE;
  70                         dss->aux.base = dss->ahb.base + DP_DEFAULT_AUX_OFFSET;
  71                         dss->aux.len = DP_DEFAULT_AUX_SIZE;
  72                         dss->link.base = dss->ahb.base + DP_DEFAULT_LINK_OFFSET;
  73                         dss->link.len = DP_DEFAULT_LINK_SIZE;
  74                         dss->p0.base = dss->ahb.base + DP_DEFAULT_P0_OFFSET;
  75                         dss->p0.len = DP_DEFAULT_P0_SIZE;
  76                 } else {
  77                         DRM_ERROR("unable to remap aux region: %pe\n", dss->aux.base);
  78                         return PTR_ERR(dss->aux.base);
  79                 }
  80         } else {
  81                 dss->link.base = dp_ioremap(pdev, 2, &dss->link.len);
  82                 if (IS_ERR(dss->link.base)) {
  83                         DRM_ERROR("unable to remap link region: %pe\n", dss->link.base);
  84                         return PTR_ERR(dss->link.base);
  85                 }
  86
  87                 dss->p0.base = dp_ioremap(pdev, 3, &dss->p0.len);
  88                 if (IS_ERR(dss->p0.base)) {
  89                         DRM_ERROR("unable to remap p0 region: %pe\n", dss->p0.base);
  90                         return PTR_ERR(dss->p0.base);
  91                 }
  92         }
  93
  94         io->phy = devm_phy_get(&pdev->dev, "dp");
  95         if (IS_ERR(io->phy))
  96                 return PTR_ERR(io->phy);
  97
  98         return 0;
  99 }
 100
 101 static int dp_parser_misc(struct dp_parser *parser)
 102 {
 103         struct device_node *of_node = parser->pdev->dev.of_node;
 104         int len = 0;
 105         const char *data_lane_property = "data-lanes";
 106
 107         len = of_property_count_elems_of_size(of_node,
 108                          data_lane_property, sizeof(u32));
 109         if (len < 0) {
 110                 DRM_WARN("Invalid property %s, default max DP lanes = %d\n",
 111                                 data_lane_property, DP_MAX_NUM_DP_LANES);
 112                 len = DP_MAX_NUM_DP_LANES;
 113         }
 114
 115         parser->max_dp_lanes = len;
 116         return 0;
 117 }
 118
 119 static inline bool dp_parser_check_prefix(const char *clk_prefix,
 120                                                 const char *clk_name)
 121 {
 122         return !strncmp(clk_prefix, clk_name, strlen(clk_prefix));
 123 }
 124
 125 static int dp_parser_init_clk_data(struct dp_parser *parser)
 126 {
 127         int num_clk, i, rc;
 128         int core_clk_count = 0, ctrl_clk_count = 0, stream_clk_count = 0;
 129         const char *clk_name;
 130         struct device *dev = &parser->pdev->dev;
 131         struct dss_module_power *core_power = &parser->mp[DP_CORE_PM];
 132         struct dss_module_power *ctrl_power = &parser->mp[DP_CTRL_PM];
 133         struct dss_module_power *stream_power = &parser->mp[DP_STREAM_PM];
 134
 135         num_clk = of_property_count_strings(dev->of_node, "clock-names");
 136         if (num_clk <= 0) {
 137                 DRM_ERROR("no clocks are defined\n");
 138                 return -EINVAL;
 139         }
 140
 141         for (i = 0; i < num_clk; i++) {
 142                 rc = of_property_read_string_index(dev->of_node,
 143                                 "clock-names", i, &clk_name);
 144                 if (rc < 0)
 145                         return rc;
 146
 147                 if (dp_parser_check_prefix("core", clk_name))
 148                         core_clk_count++;
 149
 150                 if (dp_parser_check_prefix("ctrl", clk_name))
 151                         ctrl_clk_count++;
 152
 153                 if (dp_parser_check_prefix("stream", clk_name))
 154                         stream_clk_count++;
 155         }
 156
 157         /* Initialize the CORE power module */
 158         if (core_clk_count == 0) {
 159                 DRM_ERROR("no core clocks are defined\n");
 160                 return -EINVAL;
 161         }
 162
 163         core_power->num_clk = core_clk_count;
 164         core_power->clk_config = devm_kzalloc(dev,
 165                         sizeof(struct dss_clk) * core_power->num_clk,
 166                         GFP_KERNEL);
 167         if (!core_power->clk_config)
 168                 return -EINVAL;
 169
 170         /* Initialize the CTRL power module */
 171         if (ctrl_clk_count == 0) {
 172                 DRM_ERROR("no ctrl clocks are defined\n");
 173                 return -EINVAL;
 174         }
 175
 176         ctrl_power->num_clk = ctrl_clk_count;
 177         ctrl_power->clk_config = devm_kzalloc(dev,
 178                         sizeof(struct dss_clk) * ctrl_power->num_clk,
 179                         GFP_KERNEL);
 180         if (!ctrl_power->clk_config) {
 181                 ctrl_power->num_clk = 0;
 182                 return -EINVAL;
 183         }
 184
 185         /* Initialize the STREAM power module */
 186         if (stream_clk_count == 0) {
 187                 DRM_ERROR("no stream (pixel) clocks are defined\n");
 188                 return -EINVAL;
 189         }
 190
 191         stream_power->num_clk = stream_clk_count;
 192         stream_power->clk_config = devm_kzalloc(dev,
 193                         sizeof(struct dss_clk) * stream_power->num_clk,
 194                         GFP_KERNEL);
 195         if (!stream_power->clk_config) {
 196                 stream_power->num_clk = 0;
 197                 return -EINVAL;
 198         }
 199
 200         return 0;
 201 }
 202
 203 static int dp_parser_clock(struct dp_parser *parser)
 204 {
 205         int rc = 0, i = 0;
 206         int num_clk = 0;
 207         int core_clk_index = 0, ctrl_clk_index = 0, stream_clk_index = 0;
 208         int core_clk_count = 0, ctrl_clk_count = 0, stream_clk_count = 0;
 209         const char *clk_name;
 210         struct device *dev = &parser->pdev->dev;
 211         struct dss_module_power *core_power = &parser->mp[DP_CORE_PM];
 212         struct dss_module_power *ctrl_power = &parser->mp[DP_CTRL_PM];
 213         struct dss_module_power *stream_power = &parser->mp[DP_STREAM_PM];
 214
 215         rc =  dp_parser_init_clk_data(parser);
 216         if (rc) {
 217                 DRM_ERROR("failed to initialize power data %d\n", rc);
 218                 return -EINVAL;
 219         }
 220
 221         core_clk_count = core_power->num_clk;
 222         ctrl_clk_count = ctrl_power->num_clk;
 223         stream_clk_count = stream_power->num_clk;
 224
 225         num_clk = core_clk_count + ctrl_clk_count + stream_clk_count;
 226
 227         for (i = 0; i < num_clk; i++) {
 228                 rc = of_property_read_string_index(dev->of_node, "clock-names",
 229                                 i, &clk_name);
 230                 if (rc) {
 231                         DRM_ERROR("error reading clock-names %d\n", rc);
 232                         return rc;
 233                 }
 234                 if (dp_parser_check_prefix("core", clk_name) &&
 235                                 core_clk_index < core_clk_count) {
 236                         struct dss_clk *clk =
 237                                 &core_power->clk_config[core_clk_index];
 238                         strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
 239                         clk->type = DSS_CLK_AHB;
 240                         core_clk_index++;
 241                 } else if (dp_parser_check_prefix("stream", clk_name) &&
 242                                 stream_clk_index < stream_clk_count) {
 243                         struct dss_clk *clk =
 244                                 &stream_power->clk_config[stream_clk_index];
 245                         strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
 246                         clk->type = DSS_CLK_PCLK;
 247                         stream_clk_index++;
 248                 } else if (dp_parser_check_prefix("ctrl", clk_name) &&
 249                            ctrl_clk_index < ctrl_clk_count) {
 250                         struct dss_clk *clk =
 251                                 &ctrl_power->clk_config[ctrl_clk_index];
 252                         strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
 253                         ctrl_clk_index++;
 254                         if (dp_parser_check_prefix("ctrl_link", clk_name) ||
 255                             dp_parser_check_prefix("stream_pixel", clk_name))
 256                                 clk->type = DSS_CLK_PCLK;
 257                         else
 258                                 clk->type = DSS_CLK_AHB;
 259                 }
 260         }
 261
 262         DRM_DEBUG_DP("clock parsing successful\n");
 263
 264         return 0;
 265 }
 266
 267 static int dp_parser_find_panel(struct dp_parser *parser)
 268 {
 269         struct device *dev = &parser->pdev->dev;
 270         struct drm_panel *panel;
 271         int rc;
 272
 273         rc = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
 274         if (rc) {
 275                 DRM_ERROR("failed to acquire DRM panel: %d\n", rc);
 276                 return rc;
 277         }
 278
 279         parser->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
 280         if (IS_ERR(parser->panel_bridge)) {
 281                 DRM_ERROR("failed to create panel bridge\n");
 282                 return PTR_ERR(parser->panel_bridge);
 283         }
 284
 285         return 0;
 286 }
 287
 288 static int dp_parser_parse(struct dp_parser *parser, int connector_type)
 289 {
 290         int rc = 0;
 291
 292         if (!parser) {
 293                 DRM_ERROR("invalid input\n");
 294                 return -EINVAL;
 295         }
 296
 297         rc = dp_parser_ctrl_res(parser);
 298         if (rc)
 299                 return rc;
 300
 301         rc = dp_parser_misc(parser);
 302         if (rc)
 303                 return rc;
 304
 305         rc = dp_parser_clock(parser);
 306         if (rc)
 307                 return rc;
 308
 309         if (connector_type == DRM_MODE_CONNECTOR_eDP) {
 310                 rc = dp_parser_find_panel(parser);
 311                 if (rc)
 312                         return rc;
 313         }
 314
 315         /* Map the corresponding regulator information according to
 316          * version. Currently, since we only have one supported platform,
 317          * mapping the regulator directly.
 318          */
 319         parser->regulator_cfg = &sdm845_dp_reg_cfg;
 320
 321         return 0;
 322 }
 323
 324 struct dp_parser *dp_parser_get(struct platform_device *pdev)
 325 {
 326         struct dp_parser *parser;
 327
 328         parser = devm_kzalloc(&pdev->dev, sizeof(*parser), GFP_KERNEL);
 329         if (!parser)
 330                 return ERR_PTR(-ENOMEM);
 331
 332         parser->parse = dp_parser_parse;
 333         parser->pdev = pdev;
 334
 335         return parser;
 336 }