1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
8 #include <linux/types.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/phy/phy.h>
12 #include <linux/phy/phy-dp.h>
13 #include <linux/pm_opp.h>
15 #include <drm/display/drm_dp_helper.h>
16 #include <drm/drm_fixed.h>
17 #include <drm/drm_print.h>
23 #define DP_KHZ_TO_HZ 1000
24 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
25 #define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /* 300 ms */
26 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
28 #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
29 #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3)
31 #define MR_LINK_TRAINING1 0x8
32 #define MR_LINK_SYMBOL_ERM 0x80
33 #define MR_LINK_PRBS7 0x100
34 #define MR_LINK_CUSTOM80 0x200
35 #define MR_LINK_TRAINING4 0x40
43 struct dp_tu_calc_input {
44 u64 lclk; /* 162, 270, 540 and 810 */
45 u64 pclk_khz; /* in KHz */
46 u64 hactive; /* active h-width */
47 u64 hporch; /* bp + fp + pulse */
48 int nlanes; /* no.of.lanes */
50 int pixel_enc; /* 444, 420, 422 */
51 int dsc_en; /* dsc on/off */
52 int async_en; /* async mode */
54 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */
55 int num_of_dsc_slices; /* number of slices per line */
58 struct dp_vc_tu_mapping_table {
61 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
63 u8 valid_boundary_link;
65 bool boundary_moderation_en;
66 u8 valid_lower_boundary_link;
67 u8 upper_boundary_count;
68 u8 lower_boundary_count;
72 struct dp_ctrl_private {
73 struct dp_ctrl dp_ctrl;
74 struct drm_device *drm_dev;
76 struct drm_dp_aux *aux;
77 struct dp_panel *panel;
79 struct dp_power *power;
80 struct dp_parser *parser;
81 struct dp_catalog *catalog;
83 struct completion idle_comp;
84 struct completion psr_op_comp;
85 struct completion video_comp;
88 static int dp_aux_link_configure(struct drm_dp_aux *aux,
89 struct dp_link_info *link)
94 values[0] = drm_dp_link_rate_to_bw_code(link->rate);
95 values[1] = link->num_lanes;
97 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
98 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
100 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
107 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl)
109 struct dp_ctrl_private *ctrl;
111 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
113 reinit_completion(&ctrl->idle_comp);
114 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE);
116 if (!wait_for_completion_timeout(&ctrl->idle_comp,
117 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES))
118 pr_warn("PUSH_IDLE pattern timedout\n");
120 drm_dbg_dp(ctrl->drm_dev, "mainlink off\n");
123 static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
126 const u8 *dpcd = ctrl->panel->dpcd;
128 /* Default-> LSCLK DIV: 1/4 LCLK */
129 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT);
131 /* Scrambler reset enable */
132 if (drm_dp_alternate_scrambler_reset_cap(dpcd))
133 config |= DP_CONFIGURATION_CTRL_ASSR;
135 tbd = dp_link_get_test_bits_depth(ctrl->link,
136 ctrl->panel->dp_mode.bpp);
138 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT;
141 config |= ((ctrl->link->link_params.num_lanes - 1)
142 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT);
144 if (drm_dp_enhanced_frame_cap(dpcd))
145 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING;
147 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */
149 /* sync clock & static Mvid */
150 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
151 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
153 if (ctrl->panel->psr_cap.version)
154 config |= DP_CONFIGURATION_CTRL_SEND_VSC;
156 dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
159 static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl)
163 dp_catalog_ctrl_lane_mapping(ctrl->catalog);
164 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
166 dp_ctrl_config_ctrl(ctrl);
168 tb = dp_link_get_test_bits_depth(ctrl->link,
169 ctrl->panel->dp_mode.bpp);
170 cc = dp_link_get_colorimetry_config(ctrl->link);
171 dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb);
172 dp_panel_timing_cfg(ctrl->panel);
176 * The structure and few functions present below are IP/Hardware
177 * specific implementation. Most of the implementation will not
178 * have coding comments
180 struct tu_algo_data {
185 s64 hbp_relative_to_pclk;
186 s64 hbp_relative_to_pclk_fp;
194 uint delay_start_link_extra_pixclk;
195 int extra_buffer_margin;
197 s64 original_ratio_fp;
206 int valid_boundary_link;
207 s64 resulting_valid_fp;
209 s64 effective_valid_fp;
210 s64 effective_valid_recorded_fp;
215 int remainder_tus_upper;
216 int remainder_tus_lower;
219 int delay_start_link;
221 int extra_pclk_cycles;
222 int extra_pclk_cycles_in_link_clk;
224 s64 average_valid2_fp;
225 int new_valid_boundary_link;
226 int remainder_symbols_exist;
228 s64 n_remainder_symbols_per_lane_fp;
229 s64 last_partial_tu_fp;
232 int n_tus_incl_last_incomplete_tu;
233 int extra_pclk_cycles_tmp;
234 int extra_pclk_cycles_in_link_clk_tmp;
235 int extra_required_bytes_new_tmp;
237 int lower_filler_size_tmp;
238 int delay_start_link_tmp;
240 bool boundary_moderation_en;
241 int boundary_mod_lower_err;
242 int upper_boundary_count;
243 int lower_boundary_count;
244 int i_upper_boundary_count;
245 int i_lower_boundary_count;
246 int valid_lower_boundary_link;
247 int even_distribution_BF;
248 int even_distribution_legacy;
249 int even_distribution;
250 int min_hblank_violated;
251 s64 delay_start_time_fp;
259 static int _tu_param_compare(s64 a, s64 b)
263 s64 a_temp, b_temp, minus_1;
268 minus_1 = drm_fixp_from_fraction(-1, 1);
270 a_sign = (a >> 32) & 0x80000000 ? 1 : 0;
272 b_sign = (b >> 32) & 0x80000000 ? 1 : 0;
276 else if (b_sign > a_sign)
279 if (!a_sign && !b_sign) { /* positive */
284 } else { /* negative */
285 a_temp = drm_fixp_mul(a, minus_1);
286 b_temp = drm_fixp_mul(b, minus_1);
295 static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in,
296 struct tu_algo_data *tu)
298 int nlanes = in->nlanes;
299 int dsc_num_slices = in->num_of_dsc_slices;
300 int dsc_num_bytes = 0;
306 int tot_num_eoc_symbols = 0;
307 int tot_num_hor_bytes = 0;
308 int tot_num_dummy_bytes = 0;
309 int dwidth_dsc_bytes = 0;
312 s64 temp1_fp, temp2_fp, temp3_fp;
314 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1);
315 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000);
316 tu->lwidth = in->hactive;
317 tu->hbp_relative_to_pclk = in->hporch;
318 tu->nlanes = in->nlanes;
320 tu->pixelEnc = in->pixel_enc;
321 tu->dsc_en = in->dsc_en;
322 tu->async_en = in->async_en;
323 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1);
324 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1);
326 if (tu->pixelEnc == 420) {
327 temp1_fp = drm_fixp_from_fraction(2, 1);
328 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp);
329 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp);
330 tu->hbp_relative_to_pclk_fp =
331 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2);
334 if (tu->pixelEnc == 422) {
356 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100);
357 temp2_fp = drm_fixp_from_fraction(in->bpp, 1);
358 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
359 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp);
361 temp1_fp = drm_fixp_from_fraction(8, 1);
362 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
364 numerator = drm_fixp2int(temp3_fp);
366 dsc_num_bytes = numerator / dsc_num_slices;
367 eoc_bytes = dsc_num_bytes % nlanes;
368 tot_num_eoc_symbols = nlanes * dsc_num_slices;
369 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices;
370 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices;
372 if (dsc_num_bytes == 0)
373 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes);
375 dwidth_dsc_bytes = (tot_num_hor_bytes +
376 tot_num_eoc_symbols +
377 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes));
379 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3);
381 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp);
382 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp);
383 pclk_dsc_fp = temp1_fp;
385 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp);
386 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp);
387 hbp_dsc_fp = temp2_fp;
390 tu->pclk_fp = pclk_dsc_fp;
391 tu->lwidth_fp = dwidth_dsc_fp;
392 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp;
396 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */
397 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp);
401 static void _tu_valid_boundary_calc(struct tu_algo_data *tu)
403 s64 temp1_fp, temp2_fp, temp, temp1, temp2;
404 int compare_result_1, compare_result_2, compare_result_3;
406 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
407 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
409 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
411 temp = (tu->i_upper_boundary_count *
412 tu->new_valid_boundary_link +
413 tu->i_lower_boundary_count *
414 (tu->new_valid_boundary_link-1));
415 tu->average_valid2_fp = drm_fixp_from_fraction(temp,
416 (tu->i_upper_boundary_count +
417 tu->i_lower_boundary_count));
419 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
420 temp2_fp = tu->lwidth_fp;
421 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
422 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
423 tu->n_tus = drm_fixp2int(temp2_fp);
424 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
427 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1);
428 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp);
429 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1);
430 temp2_fp = temp1_fp - temp2_fp;
431 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
432 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
433 tu->n_remainder_symbols_per_lane_fp = temp2_fp;
435 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
436 tu->last_partial_tu_fp =
437 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp,
440 if (tu->n_remainder_symbols_per_lane_fp != 0)
441 tu->remainder_symbols_exist = 1;
443 tu->remainder_symbols_exist = 0;
445 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes);
446 tu->n_tus_per_lane = drm_fixp2int(temp1_fp);
448 tu->paired_tus = (int)((tu->n_tus_per_lane) /
449 (tu->i_upper_boundary_count +
450 tu->i_lower_boundary_count));
452 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus *
453 (tu->i_upper_boundary_count +
454 tu->i_lower_boundary_count);
456 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) {
457 tu->remainder_tus_upper = tu->i_upper_boundary_count;
458 tu->remainder_tus_lower = tu->remainder_tus -
459 tu->i_upper_boundary_count;
461 tu->remainder_tus_upper = tu->remainder_tus;
462 tu->remainder_tus_lower = 0;
465 temp = tu->paired_tus * (tu->i_upper_boundary_count *
466 tu->new_valid_boundary_link +
467 tu->i_lower_boundary_count *
468 (tu->new_valid_boundary_link - 1)) +
469 (tu->remainder_tus_upper *
470 tu->new_valid_boundary_link) +
471 (tu->remainder_tus_lower *
472 (tu->new_valid_boundary_link - 1));
473 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1);
475 if (tu->remainder_symbols_exist) {
476 temp1_fp = tu->total_valid_fp +
477 tu->n_remainder_symbols_per_lane_fp;
478 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
479 temp2_fp = temp2_fp + tu->last_partial_tu_fp;
480 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp);
482 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
483 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp);
485 tu->effective_valid_fp = temp1_fp;
487 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
488 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
489 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp;
491 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
492 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
493 tu->n_err_fp = tu->average_valid2_fp - temp2_fp;
495 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
497 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
498 temp2_fp = tu->lwidth_fp;
499 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
500 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
503 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp);
505 tu->n_tus_incl_last_incomplete_tu = 0;
508 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
509 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
510 temp1_fp = tu->average_valid2_fp - temp2_fp;
511 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1);
512 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
515 temp1 = drm_fixp2int_ceil(temp1_fp);
517 temp = tu->i_upper_boundary_count * tu->nlanes;
518 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
519 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
520 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1);
521 temp2_fp = temp1_fp - temp2_fp;
522 temp1_fp = drm_fixp_from_fraction(temp, 1);
523 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
526 temp2 = drm_fixp2int_ceil(temp2_fp);
529 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2);
531 temp1_fp = drm_fixp_from_fraction(8, tu->bpp);
532 temp2_fp = drm_fixp_from_fraction(
533 tu->extra_required_bytes_new_tmp, 1);
534 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
537 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp);
539 tu->extra_pclk_cycles_tmp = 0;
541 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1);
542 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
543 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
546 tu->extra_pclk_cycles_in_link_clk_tmp =
547 drm_fixp2int_ceil(temp1_fp);
549 tu->extra_pclk_cycles_in_link_clk_tmp = 0;
551 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link;
553 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1;
555 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp +
556 tu->lower_filler_size_tmp +
557 tu->extra_buffer_margin;
559 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1);
560 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
562 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp);
563 if (compare_result_1 == 2)
564 compare_result_1 = 1;
566 compare_result_1 = 0;
568 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp);
569 if (compare_result_2 == 2)
570 compare_result_2 = 1;
572 compare_result_2 = 0;
574 compare_result_3 = _tu_param_compare(tu->hbp_time_fp,
575 tu->delay_start_time_fp);
576 if (compare_result_3 == 2)
577 compare_result_3 = 0;
579 compare_result_3 = 1;
581 if (((tu->even_distribution == 1) ||
582 ((tu->even_distribution_BF == 0) &&
583 (tu->even_distribution_legacy == 0))) &&
584 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 &&
586 (compare_result_1 || (tu->min_hblank_violated == 1)) &&
587 (tu->new_valid_boundary_link - 1) > 0 &&
589 (tu->delay_start_link_tmp <= 1023)) {
590 tu->upper_boundary_count = tu->i_upper_boundary_count;
591 tu->lower_boundary_count = tu->i_lower_boundary_count;
592 tu->err_fp = tu->n_n_err_fp;
593 tu->boundary_moderation_en = true;
594 tu->tu_size_desired = tu->tu_size;
595 tu->valid_boundary_link = tu->new_valid_boundary_link;
596 tu->effective_valid_recorded_fp = tu->effective_valid_fp;
597 tu->even_distribution_BF = 1;
598 tu->delay_start_link = tu->delay_start_link_tmp;
599 } else if (tu->boundary_mod_lower_err == 0) {
600 compare_result_1 = _tu_param_compare(tu->n_n_err_fp,
602 if (compare_result_1 == 2)
603 tu->boundary_mod_lower_err = 1;
607 static void _dp_ctrl_calc_tu(struct dp_ctrl_private *ctrl,
608 struct dp_tu_calc_input *in,
609 struct dp_vc_tu_mapping_table *tu_table)
611 struct tu_algo_data *tu;
612 int compare_result_1, compare_result_2;
614 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0;
616 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */
617 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */
618 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */
619 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000);
621 u8 DP_BRUTE_FORCE = 1;
622 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */
623 uint EXTRA_PIXCLK_CYCLE_DELAY = 4;
624 uint HBLANK_MARGIN = 4;
626 tu = kzalloc(sizeof(*tu), GFP_KERNEL);
630 dp_panel_update_tu_timings(in, tu);
632 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */
634 temp1_fp = drm_fixp_from_fraction(4, 1);
635 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp);
636 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp);
637 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp);
639 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
640 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp);
641 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
642 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
643 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp);
645 tu->original_ratio_fp = tu->ratio_fp;
646 tu->boundary_moderation_en = false;
647 tu->upper_boundary_count = 0;
648 tu->lower_boundary_count = 0;
649 tu->i_upper_boundary_count = 0;
650 tu->i_lower_boundary_count = 0;
651 tu->valid_lower_boundary_link = 0;
652 tu->even_distribution_BF = 0;
653 tu->even_distribution_legacy = 0;
654 tu->even_distribution = 0;
655 tu->delay_start_time_fp = 0;
657 tu->err_fp = drm_fixp_from_fraction(1000, 1);
661 tu->ratio = drm_fixp2int(tu->ratio_fp);
662 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
663 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp);
665 !tu->ratio && tu->dsc_en == 0) {
666 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp);
667 tu->ratio = drm_fixp2int(tu->ratio_fp);
669 tu->ratio_fp = drm_fixp_from_fraction(1, 1);
678 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp);
679 if (!compare_result_1 || compare_result_1 == 1)
680 compare_result_1 = 1;
682 compare_result_1 = 0;
684 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp);
685 if (!compare_result_2 || compare_result_2 == 2)
686 compare_result_2 = 1;
688 compare_result_2 = 0;
690 if (tu->dsc_en && compare_result_1 && compare_result_2) {
692 drm_dbg_dp(ctrl->drm_dev,
693 "increase HBLANK_MARGIN to %d\n", HBLANK_MARGIN);
697 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
698 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
699 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
700 temp = drm_fixp2int_ceil(temp2_fp);
701 temp1_fp = drm_fixp_from_fraction(temp, 1);
702 tu->n_err_fp = temp1_fp - temp2_fp;
704 if (tu->n_err_fp < tu->err_fp) {
705 tu->err_fp = tu->n_err_fp;
706 tu->tu_size_desired = tu->tu_size;
710 tu->tu_size_minus1 = tu->tu_size_desired - 1;
712 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
713 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
714 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
716 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
717 temp2_fp = tu->lwidth_fp;
718 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp);
720 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
721 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
722 tu->n_tus = drm_fixp2int(temp2_fp);
723 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
726 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
728 drm_dbg_dp(ctrl->drm_dev,
729 "n_sym = %d, num_of_tus = %d\n",
730 tu->valid_boundary_link, tu->n_tus);
732 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
733 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
734 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
735 temp2_fp = temp1_fp - temp2_fp;
736 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1);
737 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
739 temp = drm_fixp2int(temp2_fp);
740 if (temp && temp2_fp)
741 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp);
745 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1);
746 temp2_fp = drm_fixp_from_fraction(8, tu->bpp);
747 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
749 if (temp && temp1_fp)
750 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp);
752 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp);
754 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
755 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1);
756 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
759 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp);
761 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp);
763 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link;
765 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
766 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
768 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk +
769 tu->filler_size + tu->extra_buffer_margin;
771 tu->resulting_valid_fp =
772 drm_fixp_from_fraction(tu->valid_boundary_link, 1);
774 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
775 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
776 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
778 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1);
779 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp;
780 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp);
782 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
783 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
785 compare_result_1 = _tu_param_compare(tu->hbp_time_fp,
786 tu->delay_start_time_fp);
787 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */
788 tu->min_hblank_violated = 1;
790 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp);
792 compare_result_2 = _tu_param_compare(tu->hactive_time_fp,
793 tu->delay_start_time_fp);
794 if (compare_result_2 == 2)
795 tu->min_hblank_violated = 1;
797 tu->delay_start_time_fp = 0;
801 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY;
802 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp;
804 temp = drm_fixp2int(tu->diff_abs_fp);
805 if (!temp && tu->diff_abs_fp <= 0xffff)
808 /* if(diff_abs < 0) diff_abs *= -1 */
809 if (tu->diff_abs_fp < 0)
810 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1);
812 tu->boundary_mod_lower_err = 0;
813 if ((tu->diff_abs_fp != 0 &&
814 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) ||
815 (tu->even_distribution_legacy == 0) ||
816 (DP_BRUTE_FORCE == 1))) ||
817 (tu->min_hblank_violated == 1)) {
819 tu->err_fp = drm_fixp_from_fraction(1000, 1);
821 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
822 temp2_fp = drm_fixp_from_fraction(
823 tu->delay_start_link_extra_pixclk, 1);
824 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
827 tu->extra_buffer_margin =
828 drm_fixp2int_ceil(temp1_fp);
830 tu->extra_buffer_margin = 0;
832 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
833 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
836 tu->n_symbols = drm_fixp2int_ceil(temp1_fp);
840 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
841 for (tu->i_upper_boundary_count = 1;
842 tu->i_upper_boundary_count <= 15;
843 tu->i_upper_boundary_count++) {
844 for (tu->i_lower_boundary_count = 1;
845 tu->i_lower_boundary_count <= 15;
846 tu->i_lower_boundary_count++) {
847 _tu_valid_boundary_calc(tu);
851 tu->delay_start_link_extra_pixclk--;
852 } while (tu->boundary_moderation_en != true &&
853 tu->boundary_mod_lower_err == 1 &&
854 tu->delay_start_link_extra_pixclk != 0);
856 if (tu->boundary_moderation_en == true) {
857 temp1_fp = drm_fixp_from_fraction(
858 (tu->upper_boundary_count *
859 tu->valid_boundary_link +
860 tu->lower_boundary_count *
861 (tu->valid_boundary_link - 1)), 1);
862 temp2_fp = drm_fixp_from_fraction(
863 (tu->upper_boundary_count +
864 tu->lower_boundary_count), 1);
865 tu->resulting_valid_fp =
866 drm_fixp_div(temp1_fp, temp2_fp);
868 temp1_fp = drm_fixp_from_fraction(
869 tu->tu_size_desired, 1);
871 drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
873 tu->valid_lower_boundary_link =
874 tu->valid_boundary_link - 1;
876 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
877 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
878 temp2_fp = drm_fixp_div(temp1_fp,
879 tu->resulting_valid_fp);
880 tu->n_tus = drm_fixp2int(temp2_fp);
882 tu->tu_size_minus1 = tu->tu_size_desired - 1;
883 tu->even_distribution_BF = 1;
886 drm_fixp_from_fraction(tu->tu_size_desired, 1);
888 drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
889 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
893 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp);
896 temp = drm_fixp2int_ceil(temp2_fp);
900 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
901 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
902 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
903 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp);
904 temp1_fp = drm_fixp_from_fraction(temp, 1);
905 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
906 temp = drm_fixp2int(temp2_fp);
909 tu->delay_start_link += (int)temp;
911 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
912 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
915 tu_table->valid_boundary_link = tu->valid_boundary_link;
916 tu_table->delay_start_link = tu->delay_start_link;
917 tu_table->boundary_moderation_en = tu->boundary_moderation_en;
918 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link;
919 tu_table->upper_boundary_count = tu->upper_boundary_count;
920 tu_table->lower_boundary_count = tu->lower_boundary_count;
921 tu_table->tu_size_minus1 = tu->tu_size_minus1;
923 drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n",
924 tu_table->valid_boundary_link);
925 drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n",
926 tu_table->delay_start_link);
927 drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n",
928 tu_table->boundary_moderation_en);
929 drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n",
930 tu_table->valid_lower_boundary_link);
931 drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n",
932 tu_table->upper_boundary_count);
933 drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n",
934 tu_table->lower_boundary_count);
935 drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n",
936 tu_table->tu_size_minus1);
941 static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl,
942 struct dp_vc_tu_mapping_table *tu_table)
944 struct dp_tu_calc_input in;
945 struct drm_display_mode *drm_mode;
947 drm_mode = &ctrl->panel->dp_mode.drm_mode;
949 in.lclk = ctrl->link->link_params.rate / 1000;
950 in.pclk_khz = drm_mode->clock;
951 in.hactive = drm_mode->hdisplay;
952 in.hporch = drm_mode->htotal - drm_mode->hdisplay;
953 in.nlanes = ctrl->link->link_params.num_lanes;
954 in.bpp = ctrl->panel->dp_mode.bpp;
959 in.num_of_dsc_slices = 0;
960 in.compress_ratio = 100;
962 _dp_ctrl_calc_tu(ctrl, &in, tu_table);
965 static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl)
968 u32 valid_boundary = 0x0;
969 u32 valid_boundary2 = 0x0;
970 struct dp_vc_tu_mapping_table tu_calc_table;
972 dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table);
974 dp_tu |= tu_calc_table.tu_size_minus1;
975 valid_boundary |= tu_calc_table.valid_boundary_link;
976 valid_boundary |= (tu_calc_table.delay_start_link << 16);
978 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1);
979 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16);
980 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20);
982 if (tu_calc_table.boundary_moderation_en)
983 valid_boundary2 |= BIT(0);
985 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n",
986 dp_tu, valid_boundary, valid_boundary2);
988 dp_catalog_ctrl_update_transfer_unit(ctrl->catalog,
989 dp_tu, valid_boundary, valid_boundary2);
992 static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl)
996 if (!wait_for_completion_timeout(&ctrl->video_comp,
997 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) {
998 DRM_ERROR("wait4video timedout\n");
1004 static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
1006 struct dp_link *link = ctrl->link;
1007 int ret = 0, lane, lane_cnt;
1009 u32 max_level_reached = 0;
1010 u32 voltage_swing_level = link->phy_params.v_level;
1011 u32 pre_emphasis_level = link->phy_params.p_level;
1013 drm_dbg_dp(ctrl->drm_dev,
1014 "voltage level: %d emphasis level: %d\n",
1015 voltage_swing_level, pre_emphasis_level);
1016 ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1017 voltage_swing_level, pre_emphasis_level);
1022 if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) {
1023 drm_dbg_dp(ctrl->drm_dev,
1024 "max. voltage swing level reached %d\n",
1025 voltage_swing_level);
1026 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
1029 if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) {
1030 drm_dbg_dp(ctrl->drm_dev,
1031 "max. pre-emphasis level reached %d\n",
1032 pre_emphasis_level);
1033 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1036 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;
1038 lane_cnt = ctrl->link->link_params.num_lanes;
1039 for (lane = 0; lane < lane_cnt; lane++)
1040 buf[lane] = voltage_swing_level | pre_emphasis_level
1041 | max_level_reached;
1043 drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n",
1044 voltage_swing_level | pre_emphasis_level);
1045 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET,
1047 if (ret == lane_cnt)
1053 static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl,
1059 drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern);
1063 if (pattern && pattern != DP_TRAINING_PATTERN_4)
1064 buf |= DP_LINK_SCRAMBLING_DISABLE;
1066 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf);
1070 static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,
1075 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1076 if (len != DP_LINK_STATUS_SIZE) {
1077 DRM_ERROR("DP link status read failed, err: %d\n", len);
1084 static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,
1087 int tries, old_v_level, ret = 0;
1088 u8 link_status[DP_LINK_STATUS_SIZE];
1089 int const maximum_retries = 4;
1091 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1093 *training_step = DP_TRAINING_1;
1095 ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1);
1098 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
1099 DP_LINK_SCRAMBLING_DISABLE);
1101 ret = dp_ctrl_update_vx_px(ctrl);
1106 old_v_level = ctrl->link->phy_params.v_level;
1107 for (tries = 0; tries < maximum_retries; tries++) {
1108 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd);
1110 ret = dp_ctrl_read_link_status(ctrl, link_status);
1114 if (drm_dp_clock_recovery_ok(link_status,
1115 ctrl->link->link_params.num_lanes)) {
1119 if (ctrl->link->phy_params.v_level >=
1120 DP_TRAIN_VOLTAGE_SWING_MAX) {
1121 DRM_ERROR_RATELIMITED("max v_level reached\n");
1125 if (old_v_level != ctrl->link->phy_params.v_level) {
1127 old_v_level = ctrl->link->phy_params.v_level;
1130 dp_link_adjust_levels(ctrl->link, link_status);
1131 ret = dp_ctrl_update_vx_px(ctrl);
1136 DRM_ERROR("max tries reached\n");
1140 static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl)
1144 switch (ctrl->link->link_params.rate) {
1146 ctrl->link->link_params.rate = 540000;
1149 ctrl->link->link_params.rate = 270000;
1152 ctrl->link->link_params.rate = 162000;
1161 drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n",
1162 ctrl->link->link_params.rate);
1168 static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl)
1171 if (ctrl->link->link_params.num_lanes == 1)
1174 ctrl->link->link_params.num_lanes /= 2;
1175 ctrl->link->link_params.rate = ctrl->panel->link_info.rate;
1177 ctrl->link->phy_params.p_level = 0;
1178 ctrl->link->phy_params.v_level = 0;
1183 static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
1185 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE);
1186 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1189 static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl,
1192 int tries = 0, ret = 0;
1195 int const maximum_retries = 5;
1196 u8 link_status[DP_LINK_STATUS_SIZE];
1198 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1200 *training_step = DP_TRAINING_2;
1202 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) {
1203 pattern = DP_TRAINING_PATTERN_4;
1205 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) {
1206 pattern = DP_TRAINING_PATTERN_3;
1209 pattern = DP_TRAINING_PATTERN_2;
1213 ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit);
1217 dp_ctrl_train_pattern_set(ctrl, pattern);
1219 for (tries = 0; tries <= maximum_retries; tries++) {
1220 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1222 ret = dp_ctrl_read_link_status(ctrl, link_status);
1226 if (drm_dp_channel_eq_ok(link_status,
1227 ctrl->link->link_params.num_lanes)) {
1231 dp_link_adjust_levels(ctrl->link, link_status);
1232 ret = dp_ctrl_update_vx_px(ctrl);
1241 static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
1245 const u8 *dpcd = ctrl->panel->dpcd;
1246 u8 encoding[] = { 0, DP_SET_ANSI_8B10B };
1248 struct dp_link_info link_info = {0};
1250 dp_ctrl_config_ctrl(ctrl);
1252 link_info.num_lanes = ctrl->link->link_params.num_lanes;
1253 link_info.rate = ctrl->link->link_params.rate;
1254 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
1256 dp_aux_link_configure(ctrl->aux, &link_info);
1258 if (drm_dp_max_downspread(dpcd))
1259 encoding[0] |= DP_SPREAD_AMP_0_5;
1261 /* config DOWNSPREAD_CTRL and MAIN_LINK_CHANNEL_CODING_SET */
1262 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2);
1264 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
1265 assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
1266 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,
1270 ret = dp_ctrl_link_train_1(ctrl, training_step);
1272 DRM_ERROR("link training #1 failed. ret=%d\n", ret);
1276 /* print success info as this is a result of user initiated action */
1277 drm_dbg_dp(ctrl->drm_dev, "link training #1 successful\n");
1279 ret = dp_ctrl_link_train_2(ctrl, training_step);
1281 DRM_ERROR("link training #2 failed. ret=%d\n", ret);
1285 /* print success info as this is a result of user initiated action */
1286 drm_dbg_dp(ctrl->drm_dev, "link training #2 successful\n");
1289 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1294 static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl,
1299 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
1301 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1305 * As part of previous calls, DP controller state might have
1306 * transitioned to PUSH_IDLE. In order to start transmitting
1307 * a link training pattern, we have to first do soft reset.
1310 ret = dp_ctrl_link_train(ctrl, training_step);
1315 static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
1316 enum dp_pm_type module, char *name, unsigned long rate)
1318 u32 num = ctrl->parser->mp[module].num_clk;
1319 struct clk_bulk_data *cfg = ctrl->parser->mp[module].clocks;
1321 while (num && strcmp(cfg->id, name)) {
1326 drm_dbg_dp(ctrl->drm_dev, "setting rate=%lu on clk=%s\n",
1330 clk_set_rate(cfg->clk, rate);
1332 DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
1336 static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
1339 struct dp_io *dp_io = &ctrl->parser->io;
1340 struct phy *phy = dp_io->phy;
1341 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1342 const u8 *dpcd = ctrl->panel->dpcd;
1344 opts_dp->lanes = ctrl->link->link_params.num_lanes;
1345 opts_dp->link_rate = ctrl->link->link_params.rate / 100;
1346 opts_dp->ssc = drm_dp_max_downspread(dpcd);
1348 phy_configure(phy, &dp_io->phy_opts);
1351 dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000);
1352 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
1354 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
1356 drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate);
1361 void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable)
1363 struct dp_ctrl_private *ctrl;
1365 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1367 dp_catalog_ctrl_reset(ctrl->catalog);
1370 * all dp controller programmable registers will not
1371 * be reset to default value after DP_SW_RESET
1372 * therefore interrupt mask bits have to be updated
1373 * to enable/disable interrupts
1375 dp_catalog_ctrl_enable_irq(ctrl->catalog, enable);
1378 void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl)
1381 struct dp_ctrl_private *ctrl = container_of(dp_ctrl,
1382 struct dp_ctrl_private, dp_ctrl);
1384 if (!ctrl->panel->psr_cap.version)
1387 dp_catalog_ctrl_config_psr(ctrl->catalog);
1389 cfg = DP_PSR_ENABLE;
1390 drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1);
1393 void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enter)
1395 struct dp_ctrl_private *ctrl = container_of(dp_ctrl,
1396 struct dp_ctrl_private, dp_ctrl);
1398 if (!ctrl->panel->psr_cap.version)
1402 * When entering PSR,
1403 * 1. Send PSR enter SDP and wait for the PSR_UPDATE_INT
1405 * 3. Disable the mainlink
1408 * 1. Enable the mainlink
1409 * 2. Send the PSR exit SDP
1412 reinit_completion(&ctrl->psr_op_comp);
1413 dp_catalog_ctrl_set_psr(ctrl->catalog, true);
1415 if (!wait_for_completion_timeout(&ctrl->psr_op_comp,
1416 PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) {
1417 DRM_ERROR("PSR_ENTRY timedout\n");
1418 dp_catalog_ctrl_set_psr(ctrl->catalog, false);
1422 dp_ctrl_push_idle(dp_ctrl);
1423 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1425 dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false);
1427 dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true);
1429 dp_catalog_ctrl_set_psr(ctrl->catalog, false);
1430 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1431 dp_ctrl_wait4video_ready(ctrl);
1432 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1436 void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl)
1438 struct dp_ctrl_private *ctrl;
1439 struct dp_io *dp_io;
1442 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1443 dp_io = &ctrl->parser->io;
1446 dp_catalog_ctrl_phy_reset(ctrl->catalog);
1449 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1450 phy, phy->init_count, phy->power_count);
1453 void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl)
1455 struct dp_ctrl_private *ctrl;
1456 struct dp_io *dp_io;
1459 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1460 dp_io = &ctrl->parser->io;
1463 dp_catalog_ctrl_phy_reset(ctrl->catalog);
1465 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1466 phy, phy->init_count, phy->power_count);
1469 static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
1471 const u8 *dpcd = ctrl->panel->dpcd;
1474 * For better interop experience, used a fixed NVID=0x8000
1475 * whenever connected to a VGA dongle downstream.
1477 if (drm_dp_is_branch(dpcd))
1478 return (drm_dp_has_quirk(&ctrl->panel->desc,
1479 DP_DPCD_QUIRK_CONSTANT_N));
1484 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
1487 struct dp_io *dp_io = &ctrl->parser->io;
1488 struct phy *phy = dp_io->phy;
1489 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1491 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1492 opts_dp->lanes = ctrl->link->link_params.num_lanes;
1493 phy_configure(phy, &dp_io->phy_opts);
1495 * Disable and re-enable the mainlink clock since the
1496 * link clock might have been adjusted as part of the
1499 dev_pm_opp_set_rate(ctrl->dev, 0);
1500 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1502 DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
1506 /* hw recommended delay before re-enabling clocks */
1509 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1511 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret);
1518 static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl)
1520 struct dp_io *dp_io;
1524 dp_io = &ctrl->parser->io;
1527 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1529 dp_catalog_ctrl_reset(ctrl->catalog);
1531 dev_pm_opp_set_rate(ctrl->dev, 0);
1532 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1534 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1539 /* aux channel down, reinit phy */
1543 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1544 phy, phy->init_count, phy->power_count);
1548 static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl)
1551 int training_step = DP_TRAINING_NONE;
1553 dp_ctrl_push_idle(&ctrl->dp_ctrl);
1555 ctrl->link->phy_params.p_level = 0;
1556 ctrl->link->phy_params.v_level = 0;
1558 ret = dp_ctrl_setup_main_link(ctrl, &training_step);
1562 dp_ctrl_clear_training_pattern(ctrl);
1564 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1566 ret = dp_ctrl_wait4video_ready(ctrl);
1571 static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl)
1573 bool success = false;
1574 u32 pattern_sent = 0x0;
1575 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
1577 drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested);
1579 if (dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1580 ctrl->link->phy_params.v_level,
1581 ctrl->link->phy_params.p_level)) {
1582 DRM_ERROR("Failed to set v/p levels\n");
1585 dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested);
1586 dp_ctrl_update_vx_px(ctrl);
1587 dp_link_send_test_response(ctrl->link);
1589 pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog);
1591 switch (pattern_sent) {
1592 case MR_LINK_TRAINING1:
1593 success = (pattern_requested ==
1594 DP_PHY_TEST_PATTERN_D10_2);
1596 case MR_LINK_SYMBOL_ERM:
1597 success = ((pattern_requested ==
1598 DP_PHY_TEST_PATTERN_ERROR_COUNT) ||
1599 (pattern_requested ==
1600 DP_PHY_TEST_PATTERN_CP2520));
1603 success = (pattern_requested ==
1604 DP_PHY_TEST_PATTERN_PRBS7);
1606 case MR_LINK_CUSTOM80:
1607 success = (pattern_requested ==
1608 DP_PHY_TEST_PATTERN_80BIT_CUSTOM);
1610 case MR_LINK_TRAINING4:
1611 success = (pattern_requested ==
1612 DP_PHY_TEST_PATTERN_SEL_MASK);
1618 drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n",
1619 success ? "success" : "failed", pattern_requested);
1623 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
1626 unsigned long pixel_rate;
1628 if (!ctrl->link->phy_params.phy_test_pattern_sel) {
1629 drm_dbg_dp(ctrl->drm_dev,
1630 "no test pattern selected by sink\n");
1635 * The global reset will need DP link related clocks to be
1636 * running. Add the global reset just before disabling the
1637 * link clocks and core clocks.
1639 ret = dp_ctrl_off(&ctrl->dp_ctrl);
1641 DRM_ERROR("failed to disable DP controller\n");
1645 ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
1647 DRM_ERROR("failed to enable DP link controller\n");
1651 pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1652 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000);
1654 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
1656 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
1660 dp_ctrl_send_phy_test_pattern(ctrl);
1665 void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl)
1667 struct dp_ctrl_private *ctrl;
1668 u32 sink_request = 0x0;
1671 DRM_ERROR("invalid input\n");
1675 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1676 sink_request = ctrl->link->sink_request;
1678 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1679 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n");
1680 if (dp_ctrl_process_phy_test_request(ctrl)) {
1681 DRM_ERROR("process phy_test_req failed\n");
1686 if (sink_request & DP_LINK_STATUS_UPDATED) {
1687 if (dp_ctrl_link_maintenance(ctrl)) {
1688 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1693 if (sink_request & DP_TEST_LINK_TRAINING) {
1694 dp_link_send_test_response(ctrl->link);
1695 if (dp_ctrl_link_maintenance(ctrl)) {
1696 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1702 static bool dp_ctrl_clock_recovery_any_ok(
1703 const u8 link_status[DP_LINK_STATUS_SIZE],
1708 if (lane_count <= 1)
1712 * only interested in the lane number after reduced
1713 * lane_count = 4, then only interested in 2 lanes
1714 * lane_count = 2, then only interested in 1 lane
1716 reduced_cnt = lane_count >> 1;
1718 return drm_dp_clock_recovery_ok(link_status, reduced_cnt);
1721 static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl)
1723 u8 link_status[DP_LINK_STATUS_SIZE];
1724 int num_lanes = ctrl->link->link_params.num_lanes;
1726 dp_ctrl_read_link_status(ctrl, link_status);
1728 return drm_dp_channel_eq_ok(link_status, num_lanes);
1731 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
1734 struct dp_ctrl_private *ctrl;
1736 int link_train_max_retries = 5;
1737 u32 const phy_cts_pixel_clk_khz = 148500;
1738 u8 link_status[DP_LINK_STATUS_SIZE];
1739 unsigned int training_step;
1740 unsigned long pixel_rate;
1745 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1747 rate = ctrl->panel->link_info.rate;
1748 pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1750 dp_power_clk_enable(ctrl->power, DP_CORE_PM, true);
1752 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1753 drm_dbg_dp(ctrl->drm_dev,
1754 "using phy test link parameters\n");
1756 pixel_rate = phy_cts_pixel_clk_khz;
1758 ctrl->link->link_params.rate = rate;
1759 ctrl->link->link_params.num_lanes =
1760 ctrl->panel->link_info.num_lanes;
1763 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
1764 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes,
1767 rc = dp_ctrl_enable_mainlink_clocks(ctrl);
1771 while (--link_train_max_retries) {
1772 training_step = DP_TRAINING_NONE;
1773 rc = dp_ctrl_setup_main_link(ctrl, &training_step);
1775 /* training completed successfully */
1777 } else if (training_step == DP_TRAINING_1) {
1778 /* link train_1 failed */
1779 if (!dp_catalog_link_is_connected(ctrl->catalog))
1782 dp_ctrl_read_link_status(ctrl, link_status);
1784 rc = dp_ctrl_link_rate_down_shift(ctrl);
1785 if (rc < 0) { /* already in RBR = 1.6G */
1786 if (dp_ctrl_clock_recovery_any_ok(link_status,
1787 ctrl->link->link_params.num_lanes)) {
1789 * some lanes are ready,
1790 * reduce lane number
1792 rc = dp_ctrl_link_lane_down_shift(ctrl);
1793 if (rc < 0) { /* lane == 1 already */
1794 /* end with failure */
1798 /* end with failure */
1799 break; /* lane == 1 already */
1802 } else if (training_step == DP_TRAINING_2) {
1803 /* link train_2 failed */
1804 if (!dp_catalog_link_is_connected(ctrl->catalog))
1807 dp_ctrl_read_link_status(ctrl, link_status);
1809 if (!drm_dp_clock_recovery_ok(link_status,
1810 ctrl->link->link_params.num_lanes))
1811 rc = dp_ctrl_link_rate_down_shift(ctrl);
1813 rc = dp_ctrl_link_lane_down_shift(ctrl);
1816 /* end with failure */
1817 break; /* lane == 1 already */
1820 /* stop link training before start re training */
1821 dp_ctrl_clear_training_pattern(ctrl);
1824 rc = dp_ctrl_reinitialize_mainlink(ctrl);
1826 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", rc);
1831 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1834 if (rc == 0) { /* link train successfully */
1836 * do not stop train pattern here
1837 * stop link training at on_stream
1838 * to pass compliance test
1842 * link training failed
1843 * end txing train pattern here
1845 dp_ctrl_clear_training_pattern(ctrl);
1847 dp_ctrl_deinitialize_mainlink(ctrl);
1854 static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl)
1856 int training_step = DP_TRAINING_NONE;
1858 return dp_ctrl_setup_main_link(ctrl, &training_step);
1861 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
1864 bool mainlink_ready = false;
1865 struct dp_ctrl_private *ctrl;
1866 unsigned long pixel_rate;
1867 unsigned long pixel_rate_orig;
1872 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1874 pixel_rate = pixel_rate_orig = ctrl->panel->dp_mode.drm_mode.clock;
1876 if (dp_ctrl->wide_bus_en)
1879 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
1880 ctrl->link->link_params.rate,
1881 ctrl->link->link_params.num_lanes, pixel_rate);
1883 if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */
1884 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1886 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret);
1891 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000);
1893 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
1895 DRM_ERROR("Unable to start pixel clocks. ret=%d\n", ret);
1899 if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl))
1900 dp_ctrl_link_retrain(ctrl);
1902 /* stop txing train pattern to end link training */
1903 dp_ctrl_clear_training_pattern(ctrl);
1906 * Set up transfer unit values and set controller state to send
1909 reinit_completion(&ctrl->video_comp);
1911 dp_ctrl_configure_source_params(ctrl);
1913 dp_catalog_ctrl_config_msa(ctrl->catalog,
1914 ctrl->link->link_params.rate,
1915 pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl));
1917 dp_ctrl_setup_tr_unit(ctrl);
1919 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1921 ret = dp_ctrl_wait4video_ready(ctrl);
1925 mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog);
1926 drm_dbg_dp(ctrl->drm_dev,
1927 "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY");
1933 int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
1935 struct dp_ctrl_private *ctrl;
1936 struct dp_io *dp_io;
1940 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1941 dp_io = &ctrl->parser->io;
1944 /* set dongle to D3 (power off) mode */
1945 dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
1947 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1949 if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) {
1950 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1952 DRM_ERROR("Failed to disable pclk. ret=%d\n", ret);
1957 dev_pm_opp_set_rate(ctrl->dev, 0);
1958 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1960 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1966 /* aux channel down, reinit phy */
1970 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1971 phy, phy->init_count, phy->power_count);
1975 int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl)
1977 struct dp_ctrl_private *ctrl;
1978 struct dp_io *dp_io;
1982 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1983 dp_io = &ctrl->parser->io;
1986 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1988 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1990 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1993 DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n",
1994 phy, phy->init_count, phy->power_count);
1998 DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n",
1999 phy, phy->init_count, phy->power_count);
2004 int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
2006 struct dp_ctrl_private *ctrl;
2007 struct dp_io *dp_io;
2014 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
2015 dp_io = &ctrl->parser->io;
2018 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
2020 dp_catalog_ctrl_reset(ctrl->catalog);
2022 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
2024 DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret);
2026 dev_pm_opp_set_rate(ctrl->dev, 0);
2027 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
2029 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
2033 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
2034 phy, phy->init_count, phy->power_count);
2039 irqreturn_t dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
2041 struct dp_ctrl_private *ctrl;
2043 irqreturn_t ret = IRQ_NONE;
2048 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
2050 if (ctrl->panel->psr_cap.version) {
2051 isr = dp_catalog_ctrl_read_psr_interrupt_status(ctrl->catalog);
2054 complete(&ctrl->psr_op_comp);
2056 if (isr & PSR_EXIT_INT)
2057 drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n");
2059 if (isr & PSR_UPDATE_INT)
2060 drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n");
2062 if (isr & PSR_CAPTURE_INT)
2063 drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n");
2066 isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
2069 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
2070 drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n");
2071 complete(&ctrl->video_comp);
2075 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) {
2076 drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n");
2077 complete(&ctrl->idle_comp);
2084 struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
2085 struct dp_panel *panel, struct drm_dp_aux *aux,
2086 struct dp_power *power, struct dp_catalog *catalog,
2087 struct dp_parser *parser)
2089 struct dp_ctrl_private *ctrl;
2092 if (!dev || !panel || !aux ||
2093 !link || !catalog) {
2094 DRM_ERROR("invalid input\n");
2095 return ERR_PTR(-EINVAL);
2098 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2100 DRM_ERROR("Mem allocation failure\n");
2101 return ERR_PTR(-ENOMEM);
2104 ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
2106 dev_err(dev, "invalid DP OPP table in device tree\n");
2107 /* caller do PTR_ERR(opp_table) */
2108 return (struct dp_ctrl *)ERR_PTR(ret);
2111 /* OPP table is optional */
2112 ret = devm_pm_opp_of_add_table(dev);
2114 dev_err(dev, "failed to add DP OPP table\n");
2116 init_completion(&ctrl->idle_comp);
2117 init_completion(&ctrl->psr_op_comp);
2118 init_completion(&ctrl->video_comp);
2121 ctrl->parser = parser;
2122 ctrl->panel = panel;
2123 ctrl->power = power;
2126 ctrl->catalog = catalog;
2129 return &ctrl->dp_ctrl;