drivers/gpu/drm/msm/dp/dp_ctrl.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #define pr_fmt(fmt)     "[drm-dp] %s: " fmt, __func__
   7
   8 #include <linux/types.h>
   9 #include <linux/completion.h>
  10 #include <linux/delay.h>
  11 #include <linux/phy/phy.h>
  12 #include <linux/phy/phy-dp.h>
  13 #include <linux/pm_opp.h>
  14 #include <drm/drm_fixed.h>
  15 #include <drm/dp/drm_dp_helper.h>
  16 #include <drm/drm_print.h>
  17
  18 #include "dp_reg.h"
  19 #include "dp_ctrl.h"
  20 #include "dp_link.h"
  21
  22 #define DP_KHZ_TO_HZ 1000
  23 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
  24 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
  25
  26 #define DP_CTRL_INTR_READY_FOR_VIDEO     BIT(0)
  27 #define DP_CTRL_INTR_IDLE_PATTERN_SENT  BIT(3)
  28
  29 #define MR_LINK_TRAINING1  0x8
  30 #define MR_LINK_SYMBOL_ERM 0x80
  31 #define MR_LINK_PRBS7 0x100
  32 #define MR_LINK_CUSTOM80 0x200
  33 #define MR_LINK_TRAINING4  0x40
  34
  35 enum {
  36         DP_TRAINING_NONE,
  37         DP_TRAINING_1,
  38         DP_TRAINING_2,
  39 };
  40
  41 struct dp_tu_calc_input {
  42         u64 lclk;        /* 162, 270, 540 and 810 */
  43         u64 pclk_khz;    /* in KHz */
  44         u64 hactive;     /* active h-width */
  45         u64 hporch;      /* bp + fp + pulse */
  46         int nlanes;      /* no.of.lanes */
  47         int bpp;         /* bits */
  48         int pixel_enc;   /* 444, 420, 422 */
  49         int dsc_en;     /* dsc on/off */
  50         int async_en;   /* async mode */
  51         int fec_en;     /* fec */
  52         int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */
  53         int num_of_dsc_slices; /* number of slices per line */
  54 };
  55
  56 struct dp_vc_tu_mapping_table {
  57         u32 vic;
  58         u8 lanes;
  59         u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
  60         u8 bpp;
  61         u8 valid_boundary_link;
  62         u16 delay_start_link;
  63         bool boundary_moderation_en;
  64         u8 valid_lower_boundary_link;
  65         u8 upper_boundary_count;
  66         u8 lower_boundary_count;
  67         u8 tu_size_minus1;
  68 };
  69
  70 struct dp_ctrl_private {
  71         struct dp_ctrl dp_ctrl;
  72         struct drm_device *drm_dev;
  73         struct device *dev;
  74         struct drm_dp_aux *aux;
  75         struct dp_panel *panel;
  76         struct dp_link *link;
  77         struct dp_power *power;
  78         struct dp_parser *parser;
  79         struct dp_catalog *catalog;
  80
  81         struct completion idle_comp;
  82         struct completion video_comp;
  83 };
  84
  85 static int dp_aux_link_configure(struct drm_dp_aux *aux,
  86                                         struct dp_link_info *link)
  87 {
  88         u8 values[2];
  89         int err;
  90
  91         values[0] = drm_dp_link_rate_to_bw_code(link->rate);
  92         values[1] = link->num_lanes;
  93
  94         if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
  95                 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  96
  97         err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
  98         if (err < 0)
  99                 return err;
 100
 101         return 0;
 102 }
 103
 104 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl)
 105 {
 106         struct dp_ctrl_private *ctrl;
 107
 108         ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
 109
 110         reinit_completion(&ctrl->idle_comp);
 111         dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE);
 112
 113         if (!wait_for_completion_timeout(&ctrl->idle_comp,
 114                         IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES))
 115                 pr_warn("PUSH_IDLE pattern timedout\n");
 116
 117         drm_dbg_dp(ctrl->drm_dev, "mainlink off\n");
 118 }
 119
 120 static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
 121 {
 122         u32 config = 0, tbd;
 123         const u8 *dpcd = ctrl->panel->dpcd;
 124
 125         /* Default-> LSCLK DIV: 1/4 LCLK  */
 126         config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT);
 127
 128         /* Scrambler reset enable */
 129         if (drm_dp_alternate_scrambler_reset_cap(dpcd))
 130                 config |= DP_CONFIGURATION_CTRL_ASSR;
 131
 132         tbd = dp_link_get_test_bits_depth(ctrl->link,
 133                         ctrl->panel->dp_mode.bpp);
 134
 135         if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) {
 136                 pr_debug("BIT_DEPTH not set. Configure default\n");
 137                 tbd = DP_TEST_BIT_DEPTH_8;
 138         }
 139
 140         config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT;
 141
 142         /* Num of Lanes */
 143         config |= ((ctrl->link->link_params.num_lanes - 1)
 144                         << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT);
 145
 146         if (drm_dp_enhanced_frame_cap(dpcd))
 147                 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING;
 148
 149         config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */
 150
 151         /* sync clock & static Mvid */
 152         config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
 153         config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
 154
 155         dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
 156 }
 157
 158 static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl)
 159 {
 160         u32 cc, tb;
 161
 162         dp_catalog_ctrl_lane_mapping(ctrl->catalog);
 163         dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
 164
 165         dp_ctrl_config_ctrl(ctrl);
 166
 167         tb = dp_link_get_test_bits_depth(ctrl->link,
 168                 ctrl->panel->dp_mode.bpp);
 169         cc = dp_link_get_colorimetry_config(ctrl->link);
 170         dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb);
 171         dp_panel_timing_cfg(ctrl->panel);
 172 }
 173
 174 /*
 175  * The structure and few functions present below are IP/Hardware
 176  * specific implementation. Most of the implementation will not
 177  * have coding comments
 178  */
 179 struct tu_algo_data {
 180         s64 lclk_fp;
 181         s64 pclk_fp;
 182         s64 lwidth;
 183         s64 lwidth_fp;
 184         s64 hbp_relative_to_pclk;
 185         s64 hbp_relative_to_pclk_fp;
 186         int nlanes;
 187         int bpp;
 188         int pixelEnc;
 189         int dsc_en;
 190         int async_en;
 191         int bpc;
 192
 193         uint delay_start_link_extra_pixclk;
 194         int extra_buffer_margin;
 195         s64 ratio_fp;
 196         s64 original_ratio_fp;
 197
 198         s64 err_fp;
 199         s64 n_err_fp;
 200         s64 n_n_err_fp;
 201         int tu_size;
 202         int tu_size_desired;
 203         int tu_size_minus1;
 204
 205         int valid_boundary_link;
 206         s64 resulting_valid_fp;
 207         s64 total_valid_fp;
 208         s64 effective_valid_fp;
 209         s64 effective_valid_recorded_fp;
 210         int n_tus;
 211         int n_tus_per_lane;
 212         int paired_tus;
 213         int remainder_tus;
 214         int remainder_tus_upper;
 215         int remainder_tus_lower;
 216         int extra_bytes;
 217         int filler_size;
 218         int delay_start_link;
 219
 220         int extra_pclk_cycles;
 221         int extra_pclk_cycles_in_link_clk;
 222         s64 ratio_by_tu_fp;
 223         s64 average_valid2_fp;
 224         int new_valid_boundary_link;
 225         int remainder_symbols_exist;
 226         int n_symbols;
 227         s64 n_remainder_symbols_per_lane_fp;
 228         s64 last_partial_tu_fp;
 229         s64 TU_ratio_err_fp;
 230
 231         int n_tus_incl_last_incomplete_tu;
 232         int extra_pclk_cycles_tmp;
 233         int extra_pclk_cycles_in_link_clk_tmp;
 234         int extra_required_bytes_new_tmp;
 235         int filler_size_tmp;
 236         int lower_filler_size_tmp;
 237         int delay_start_link_tmp;
 238
 239         bool boundary_moderation_en;
 240         int boundary_mod_lower_err;
 241         int upper_boundary_count;
 242         int lower_boundary_count;
 243         int i_upper_boundary_count;
 244         int i_lower_boundary_count;
 245         int valid_lower_boundary_link;
 246         int even_distribution_BF;
 247         int even_distribution_legacy;
 248         int even_distribution;
 249         int min_hblank_violated;
 250         s64 delay_start_time_fp;
 251         s64 hbp_time_fp;
 252         s64 hactive_time_fp;
 253         s64 diff_abs_fp;
 254
 255         s64 ratio;
 256 };
 257
 258 static int _tu_param_compare(s64 a, s64 b)
 259 {
 260         u32 a_sign;
 261         u32 b_sign;
 262         s64 a_temp, b_temp, minus_1;
 263
 264         if (a == b)
 265                 return 0;
 266
 267         minus_1 = drm_fixp_from_fraction(-1, 1);
 268
 269         a_sign = (a >> 32) & 0x80000000 ? 1 : 0;
 270
 271         b_sign = (b >> 32) & 0x80000000 ? 1 : 0;
 272
 273         if (a_sign > b_sign)
 274                 return 2;
 275         else if (b_sign > a_sign)
 276                 return 1;
 277
 278         if (!a_sign && !b_sign) { /* positive */
 279                 if (a > b)
 280                         return 1;
 281                 else
 282                         return 2;
 283         } else { /* negative */
 284                 a_temp = drm_fixp_mul(a, minus_1);
 285                 b_temp = drm_fixp_mul(b, minus_1);
 286
 287                 if (a_temp > b_temp)
 288                         return 2;
 289                 else
 290                         return 1;
 291         }
 292 }
 293
 294 static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in,
 295                                         struct tu_algo_data *tu)
 296 {
 297         int nlanes = in->nlanes;
 298         int dsc_num_slices = in->num_of_dsc_slices;
 299         int dsc_num_bytes  = 0;
 300         int numerator;
 301         s64 pclk_dsc_fp;
 302         s64 dwidth_dsc_fp;
 303         s64 hbp_dsc_fp;
 304
 305         int tot_num_eoc_symbols = 0;
 306         int tot_num_hor_bytes   = 0;
 307         int tot_num_dummy_bytes = 0;
 308         int dwidth_dsc_bytes    = 0;
 309         int  eoc_bytes           = 0;
 310
 311         s64 temp1_fp, temp2_fp, temp3_fp;
 312
 313         tu->lclk_fp              = drm_fixp_from_fraction(in->lclk, 1);
 314         tu->pclk_fp              = drm_fixp_from_fraction(in->pclk_khz, 1000);
 315         tu->lwidth               = in->hactive;
 316         tu->hbp_relative_to_pclk = in->hporch;
 317         tu->nlanes               = in->nlanes;
 318         tu->bpp                  = in->bpp;
 319         tu->pixelEnc             = in->pixel_enc;
 320         tu->dsc_en               = in->dsc_en;
 321         tu->async_en             = in->async_en;
 322         tu->lwidth_fp            = drm_fixp_from_fraction(in->hactive, 1);
 323         tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1);
 324
 325         if (tu->pixelEnc == 420) {
 326                 temp1_fp = drm_fixp_from_fraction(2, 1);
 327                 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp);
 328                 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp);
 329                 tu->hbp_relative_to_pclk_fp =
 330                                 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2);
 331         }
 332
 333         if (tu->pixelEnc == 422) {
 334                 switch (tu->bpp) {
 335                 case 24:
 336                         tu->bpp = 16;
 337                         tu->bpc = 8;
 338                         break;
 339                 case 30:
 340                         tu->bpp = 20;
 341                         tu->bpc = 10;
 342                         break;
 343                 default:
 344                         tu->bpp = 16;
 345                         tu->bpc = 8;
 346                         break;
 347                 }
 348         } else {
 349                 tu->bpc = tu->bpp/3;
 350         }
 351
 352         if (!in->dsc_en)
 353                 goto fec_check;
 354
 355         temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100);
 356         temp2_fp = drm_fixp_from_fraction(in->bpp, 1);
 357         temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
 358         temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp);
 359
 360         temp1_fp = drm_fixp_from_fraction(8, 1);
 361         temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
 362
 363         numerator = drm_fixp2int(temp3_fp);
 364
 365         dsc_num_bytes  = numerator / dsc_num_slices;
 366         eoc_bytes           = dsc_num_bytes % nlanes;
 367         tot_num_eoc_symbols = nlanes * dsc_num_slices;
 368         tot_num_hor_bytes   = dsc_num_bytes * dsc_num_slices;
 369         tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices;
 370
 371         if (dsc_num_bytes == 0)
 372                 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes);
 373
 374         dwidth_dsc_bytes = (tot_num_hor_bytes +
 375                                 tot_num_eoc_symbols +
 376                                 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes));
 377
 378         dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3);
 379
 380         temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp);
 381         temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp);
 382         pclk_dsc_fp = temp1_fp;
 383
 384         temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp);
 385         temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp);
 386         hbp_dsc_fp = temp2_fp;
 387
 388         /* output */
 389         tu->pclk_fp = pclk_dsc_fp;
 390         tu->lwidth_fp = dwidth_dsc_fp;
 391         tu->hbp_relative_to_pclk_fp = hbp_dsc_fp;
 392
 393 fec_check:
 394         if (in->fec_en) {
 395                 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */
 396                 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp);
 397         }
 398 }
 399
 400 static void _tu_valid_boundary_calc(struct tu_algo_data *tu)
 401 {
 402         s64 temp1_fp, temp2_fp, temp, temp1, temp2;
 403         int compare_result_1, compare_result_2, compare_result_3;
 404
 405         temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
 406         temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
 407
 408         tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
 409
 410         temp = (tu->i_upper_boundary_count *
 411                                 tu->new_valid_boundary_link +
 412                                 tu->i_lower_boundary_count *
 413                                 (tu->new_valid_boundary_link-1));
 414         tu->average_valid2_fp = drm_fixp_from_fraction(temp,
 415                                         (tu->i_upper_boundary_count +
 416                                         tu->i_lower_boundary_count));
 417
 418         temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
 419         temp2_fp = tu->lwidth_fp;
 420         temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
 421         temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
 422         tu->n_tus = drm_fixp2int(temp2_fp);
 423         if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
 424                 tu->n_tus += 1;
 425
 426         temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1);
 427         temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp);
 428         temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1);
 429         temp2_fp = temp1_fp - temp2_fp;
 430         temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
 431         temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
 432         tu->n_remainder_symbols_per_lane_fp = temp2_fp;
 433
 434         temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
 435         tu->last_partial_tu_fp =
 436                         drm_fixp_div(tu->n_remainder_symbols_per_lane_fp,
 437                                         temp1_fp);
 438
 439         if (tu->n_remainder_symbols_per_lane_fp != 0)
 440                 tu->remainder_symbols_exist = 1;
 441         else
 442                 tu->remainder_symbols_exist = 0;
 443
 444         temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes);
 445         tu->n_tus_per_lane = drm_fixp2int(temp1_fp);
 446
 447         tu->paired_tus = (int)((tu->n_tus_per_lane) /
 448                                         (tu->i_upper_boundary_count +
 449                                          tu->i_lower_boundary_count));
 450
 451         tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus *
 452                                                 (tu->i_upper_boundary_count +
 453                                                 tu->i_lower_boundary_count);
 454
 455         if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) {
 456                 tu->remainder_tus_upper = tu->i_upper_boundary_count;
 457                 tu->remainder_tus_lower = tu->remainder_tus -
 458                                                 tu->i_upper_boundary_count;
 459         } else {
 460                 tu->remainder_tus_upper = tu->remainder_tus;
 461                 tu->remainder_tus_lower = 0;
 462         }
 463
 464         temp = tu->paired_tus * (tu->i_upper_boundary_count *
 465                                 tu->new_valid_boundary_link +
 466                                 tu->i_lower_boundary_count *
 467                                 (tu->new_valid_boundary_link - 1)) +
 468                                 (tu->remainder_tus_upper *
 469                                  tu->new_valid_boundary_link) +
 470                                 (tu->remainder_tus_lower *
 471                                 (tu->new_valid_boundary_link - 1));
 472         tu->total_valid_fp = drm_fixp_from_fraction(temp, 1);
 473
 474         if (tu->remainder_symbols_exist) {
 475                 temp1_fp = tu->total_valid_fp +
 476                                 tu->n_remainder_symbols_per_lane_fp;
 477                 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
 478                 temp2_fp = temp2_fp + tu->last_partial_tu_fp;
 479                 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp);
 480         } else {
 481                 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
 482                 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp);
 483         }
 484         tu->effective_valid_fp = temp1_fp;
 485
 486         temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
 487         temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
 488         tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp;
 489
 490         temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
 491         temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
 492         tu->n_err_fp = tu->average_valid2_fp - temp2_fp;
 493
 494         tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
 495
 496         temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
 497         temp2_fp = tu->lwidth_fp;
 498         temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
 499         temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
 500
 501         if (temp2_fp)
 502                 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp);
 503         else
 504                 tu->n_tus_incl_last_incomplete_tu = 0;
 505
 506         temp1 = 0;
 507         temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
 508         temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
 509         temp1_fp = tu->average_valid2_fp - temp2_fp;
 510         temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1);
 511         temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
 512
 513         if (temp1_fp)
 514                 temp1 = drm_fixp2int_ceil(temp1_fp);
 515
 516         temp = tu->i_upper_boundary_count * tu->nlanes;
 517         temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
 518         temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
 519         temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1);
 520         temp2_fp = temp1_fp - temp2_fp;
 521         temp1_fp = drm_fixp_from_fraction(temp, 1);
 522         temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
 523
 524         if (temp2_fp)
 525                 temp2 = drm_fixp2int_ceil(temp2_fp);
 526         else
 527                 temp2 = 0;
 528         tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2);
 529
 530         temp1_fp = drm_fixp_from_fraction(8, tu->bpp);
 531         temp2_fp = drm_fixp_from_fraction(
 532         tu->extra_required_bytes_new_tmp, 1);
 533         temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
 534
 535         if (temp1_fp)
 536                 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp);
 537         else
 538                 tu->extra_pclk_cycles_tmp = 0;
 539
 540         temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1);
 541         temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
 542         temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
 543
 544         if (temp1_fp)
 545                 tu->extra_pclk_cycles_in_link_clk_tmp =
 546                                                 drm_fixp2int_ceil(temp1_fp);
 547         else
 548                 tu->extra_pclk_cycles_in_link_clk_tmp = 0;
 549
 550         tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link;
 551
 552         tu->lower_filler_size_tmp = tu->filler_size_tmp + 1;
 553
 554         tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp +
 555                                         tu->lower_filler_size_tmp +
 556                                         tu->extra_buffer_margin;
 557
 558         temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1);
 559         tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
 560
 561         compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp);
 562         if (compare_result_1 == 2)
 563                 compare_result_1 = 1;
 564         else
 565                 compare_result_1 = 0;
 566
 567         compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp);
 568         if (compare_result_2 == 2)
 569                 compare_result_2 = 1;
 570         else
 571                 compare_result_2 = 0;
 572
 573         compare_result_3 = _tu_param_compare(tu->hbp_time_fp,
 574                                         tu->delay_start_time_fp);
 575         if (compare_result_3 == 2)
 576                 compare_result_3 = 0;
 577         else
 578                 compare_result_3 = 1;
 579
 580         if (((tu->even_distribution == 1) ||
 581                         ((tu->even_distribution_BF == 0) &&
 582                         (tu->even_distribution_legacy == 0))) &&
 583                         tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 &&
 584                         compare_result_2 &&
 585                         (compare_result_1 || (tu->min_hblank_violated == 1)) &&
 586                         (tu->new_valid_boundary_link - 1) > 0 &&
 587                         compare_result_3 &&
 588                         (tu->delay_start_link_tmp <= 1023)) {
 589                 tu->upper_boundary_count = tu->i_upper_boundary_count;
 590                 tu->lower_boundary_count = tu->i_lower_boundary_count;
 591                 tu->err_fp = tu->n_n_err_fp;
 592                 tu->boundary_moderation_en = true;
 593                 tu->tu_size_desired = tu->tu_size;
 594                 tu->valid_boundary_link = tu->new_valid_boundary_link;
 595                 tu->effective_valid_recorded_fp = tu->effective_valid_fp;
 596                 tu->even_distribution_BF = 1;
 597                 tu->delay_start_link = tu->delay_start_link_tmp;
 598         } else if (tu->boundary_mod_lower_err == 0) {
 599                 compare_result_1 = _tu_param_compare(tu->n_n_err_fp,
 600                                                         tu->diff_abs_fp);
 601                 if (compare_result_1 == 2)
 602                         tu->boundary_mod_lower_err = 1;
 603         }
 604 }
 605
 606 static void _dp_ctrl_calc_tu(struct dp_ctrl_private *ctrl,
 607                                 struct dp_tu_calc_input *in,
 608                                 struct dp_vc_tu_mapping_table *tu_table)
 609 {
 610         struct tu_algo_data *tu;
 611         int compare_result_1, compare_result_2;
 612         u64 temp = 0;
 613         s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0;
 614
 615         s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */
 616         s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */
 617         s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */
 618         s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000);
 619
 620         u8 DP_BRUTE_FORCE = 1;
 621         s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */
 622         uint EXTRA_PIXCLK_CYCLE_DELAY = 4;
 623         uint HBLANK_MARGIN = 4;
 624
 625         tu = kzalloc(sizeof(*tu), GFP_KERNEL);
 626         if (!tu)
 627                 return;
 628
 629         dp_panel_update_tu_timings(in, tu);
 630
 631         tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */
 632
 633         temp1_fp = drm_fixp_from_fraction(4, 1);
 634         temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp);
 635         temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp);
 636         tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp);
 637
 638         temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
 639         temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp);
 640         temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
 641         temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
 642         tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp);
 643
 644         tu->original_ratio_fp = tu->ratio_fp;
 645         tu->boundary_moderation_en = false;
 646         tu->upper_boundary_count = 0;
 647         tu->lower_boundary_count = 0;
 648         tu->i_upper_boundary_count = 0;
 649         tu->i_lower_boundary_count = 0;
 650         tu->valid_lower_boundary_link = 0;
 651         tu->even_distribution_BF = 0;
 652         tu->even_distribution_legacy = 0;
 653         tu->even_distribution = 0;
 654         tu->delay_start_time_fp = 0;
 655
 656         tu->err_fp = drm_fixp_from_fraction(1000, 1);
 657         tu->n_err_fp = 0;
 658         tu->n_n_err_fp = 0;
 659
 660         tu->ratio = drm_fixp2int(tu->ratio_fp);
 661         temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
 662         div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp);
 663         if (temp2_fp != 0 &&
 664                         !tu->ratio && tu->dsc_en == 0) {
 665                 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp);
 666                 tu->ratio = drm_fixp2int(tu->ratio_fp);
 667                 if (tu->ratio)
 668                         tu->ratio_fp = drm_fixp_from_fraction(1, 1);
 669         }
 670
 671         if (tu->ratio > 1)
 672                 tu->ratio = 1;
 673
 674         if (tu->ratio == 1)
 675                 goto tu_size_calc;
 676
 677         compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp);
 678         if (!compare_result_1 || compare_result_1 == 1)
 679                 compare_result_1 = 1;
 680         else
 681                 compare_result_1 = 0;
 682
 683         compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp);
 684         if (!compare_result_2 || compare_result_2 == 2)
 685                 compare_result_2 = 1;
 686         else
 687                 compare_result_2 = 0;
 688
 689         if (tu->dsc_en && compare_result_1 && compare_result_2) {
 690                 HBLANK_MARGIN += 4;
 691                 drm_dbg_dp(ctrl->drm_dev,
 692                         "increase HBLANK_MARGIN to %d\n", HBLANK_MARGIN);
 693         }
 694
 695 tu_size_calc:
 696         for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
 697                 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
 698                 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
 699                 temp = drm_fixp2int_ceil(temp2_fp);
 700                 temp1_fp = drm_fixp_from_fraction(temp, 1);
 701                 tu->n_err_fp = temp1_fp - temp2_fp;
 702
 703                 if (tu->n_err_fp < tu->err_fp) {
 704                         tu->err_fp = tu->n_err_fp;
 705                         tu->tu_size_desired = tu->tu_size;
 706                 }
 707         }
 708
 709         tu->tu_size_minus1 = tu->tu_size_desired - 1;
 710
 711         temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
 712         temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
 713         tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
 714
 715         temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
 716         temp2_fp = tu->lwidth_fp;
 717         temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp);
 718
 719         temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
 720         temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
 721         tu->n_tus = drm_fixp2int(temp2_fp);
 722         if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
 723                 tu->n_tus += 1;
 724
 725         tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
 726
 727         drm_dbg_dp(ctrl->drm_dev,
 728                         "n_sym = %d, num_of_tus = %d\n",
 729                         tu->valid_boundary_link, tu->n_tus);
 730
 731         temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
 732         temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
 733         temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
 734         temp2_fp = temp1_fp - temp2_fp;
 735         temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1);
 736         temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
 737
 738         temp = drm_fixp2int(temp2_fp);
 739         if (temp && temp2_fp)
 740                 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp);
 741         else
 742                 tu->extra_bytes = 0;
 743
 744         temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1);
 745         temp2_fp = drm_fixp_from_fraction(8, tu->bpp);
 746         temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
 747
 748         if (temp && temp1_fp)
 749                 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp);
 750         else
 751                 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp);
 752
 753         temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
 754         temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1);
 755         temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
 756
 757         if (temp1_fp)
 758                 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp);
 759         else
 760                 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp);
 761
 762         tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link;
 763
 764         temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
 765         tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
 766
 767         tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk +
 768                                 tu->filler_size + tu->extra_buffer_margin;
 769
 770         tu->resulting_valid_fp =
 771                         drm_fixp_from_fraction(tu->valid_boundary_link, 1);
 772
 773         temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
 774         temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
 775         tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
 776
 777         temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1);
 778         temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp;
 779         tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp);
 780
 781         temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
 782         tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
 783
 784         compare_result_1 = _tu_param_compare(tu->hbp_time_fp,
 785                                         tu->delay_start_time_fp);
 786         if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */
 787                 tu->min_hblank_violated = 1;
 788
 789         tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp);
 790
 791         compare_result_2 = _tu_param_compare(tu->hactive_time_fp,
 792                                                 tu->delay_start_time_fp);
 793         if (compare_result_2 == 2)
 794                 tu->min_hblank_violated = 1;
 795
 796         tu->delay_start_time_fp = 0;
 797
 798         /* brute force */
 799
 800         tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY;
 801         tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp;
 802
 803         temp = drm_fixp2int(tu->diff_abs_fp);
 804         if (!temp && tu->diff_abs_fp <= 0xffff)
 805                 tu->diff_abs_fp = 0;
 806
 807         /* if(diff_abs < 0) diff_abs *= -1 */
 808         if (tu->diff_abs_fp < 0)
 809                 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1);
 810
 811         tu->boundary_mod_lower_err = 0;
 812         if ((tu->diff_abs_fp != 0 &&
 813                         ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) ||
 814                          (tu->even_distribution_legacy == 0) ||
 815                          (DP_BRUTE_FORCE == 1))) ||
 816                         (tu->min_hblank_violated == 1)) {
 817                 do {
 818                         tu->err_fp = drm_fixp_from_fraction(1000, 1);
 819
 820                         temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
 821                         temp2_fp = drm_fixp_from_fraction(
 822                                         tu->delay_start_link_extra_pixclk, 1);
 823                         temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
 824
 825                         if (temp1_fp)
 826                                 tu->extra_buffer_margin =
 827                                         drm_fixp2int_ceil(temp1_fp);
 828                         else
 829                                 tu->extra_buffer_margin = 0;
 830
 831                         temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
 832                         temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
 833
 834                         if (temp1_fp)
 835                                 tu->n_symbols = drm_fixp2int_ceil(temp1_fp);
 836                         else
 837                                 tu->n_symbols = 0;
 838
 839                         for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
 840                                 for (tu->i_upper_boundary_count = 1;
 841                                         tu->i_upper_boundary_count <= 15;
 842                                         tu->i_upper_boundary_count++) {
 843                                         for (tu->i_lower_boundary_count = 1;
 844                                                 tu->i_lower_boundary_count <= 15;
 845                                                 tu->i_lower_boundary_count++) {
 846                                                 _tu_valid_boundary_calc(tu);
 847                                         }
 848                                 }
 849                         }
 850                         tu->delay_start_link_extra_pixclk--;
 851                 } while (tu->boundary_moderation_en != true &&
 852                         tu->boundary_mod_lower_err == 1 &&
 853                         tu->delay_start_link_extra_pixclk != 0);
 854
 855                 if (tu->boundary_moderation_en == true) {
 856                         temp1_fp = drm_fixp_from_fraction(
 857                                         (tu->upper_boundary_count *
 858                                         tu->valid_boundary_link +
 859                                         tu->lower_boundary_count *
 860                                         (tu->valid_boundary_link - 1)), 1);
 861                         temp2_fp = drm_fixp_from_fraction(
 862                                         (tu->upper_boundary_count +
 863                                         tu->lower_boundary_count), 1);
 864                         tu->resulting_valid_fp =
 865                                         drm_fixp_div(temp1_fp, temp2_fp);
 866
 867                         temp1_fp = drm_fixp_from_fraction(
 868                                         tu->tu_size_desired, 1);
 869                         tu->ratio_by_tu_fp =
 870                                 drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
 871
 872                         tu->valid_lower_boundary_link =
 873                                 tu->valid_boundary_link - 1;
 874
 875                         temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
 876                         temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
 877                         temp2_fp = drm_fixp_div(temp1_fp,
 878                                                 tu->resulting_valid_fp);
 879                         tu->n_tus = drm_fixp2int(temp2_fp);
 880
 881                         tu->tu_size_minus1 = tu->tu_size_desired - 1;
 882                         tu->even_distribution_BF = 1;
 883
 884                         temp1_fp =
 885                                 drm_fixp_from_fraction(tu->tu_size_desired, 1);
 886                         temp2_fp =
 887                                 drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
 888                         tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
 889                 }
 890         }
 891
 892         temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp);
 893
 894         if (temp2_fp)
 895                 temp = drm_fixp2int_ceil(temp2_fp);
 896         else
 897                 temp = 0;
 898
 899         temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
 900         temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
 901         temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
 902         temp2_fp = drm_fixp_div(temp1_fp, temp2_fp);
 903         temp1_fp = drm_fixp_from_fraction(temp, 1);
 904         temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
 905         temp = drm_fixp2int(temp2_fp);
 906
 907         if (tu->async_en)
 908                 tu->delay_start_link += (int)temp;
 909
 910         temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
 911         tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
 912
 913         /* OUTPUTS */
 914         tu_table->valid_boundary_link       = tu->valid_boundary_link;
 915         tu_table->delay_start_link          = tu->delay_start_link;
 916         tu_table->boundary_moderation_en    = tu->boundary_moderation_en;
 917         tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link;
 918         tu_table->upper_boundary_count      = tu->upper_boundary_count;
 919         tu_table->lower_boundary_count      = tu->lower_boundary_count;
 920         tu_table->tu_size_minus1            = tu->tu_size_minus1;
 921
 922         drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n",
 923                                 tu_table->valid_boundary_link);
 924         drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n",
 925                                 tu_table->delay_start_link);
 926         drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n",
 927                         tu_table->boundary_moderation_en);
 928         drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n",
 929                         tu_table->valid_lower_boundary_link);
 930         drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n",
 931                         tu_table->upper_boundary_count);
 932         drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n",
 933                         tu_table->lower_boundary_count);
 934         drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n",
 935                         tu_table->tu_size_minus1);
 936
 937         kfree(tu);
 938 }
 939
 940 static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl,
 941                 struct dp_vc_tu_mapping_table *tu_table)
 942 {
 943         struct dp_tu_calc_input in;
 944         struct drm_display_mode *drm_mode;
 945
 946         drm_mode = &ctrl->panel->dp_mode.drm_mode;
 947
 948         in.lclk = ctrl->link->link_params.rate / 1000;
 949         in.pclk_khz = drm_mode->clock;
 950         in.hactive = drm_mode->hdisplay;
 951         in.hporch = drm_mode->htotal - drm_mode->hdisplay;
 952         in.nlanes = ctrl->link->link_params.num_lanes;
 953         in.bpp = ctrl->panel->dp_mode.bpp;
 954         in.pixel_enc = 444;
 955         in.dsc_en = 0;
 956         in.async_en = 0;
 957         in.fec_en = 0;
 958         in.num_of_dsc_slices = 0;
 959         in.compress_ratio = 100;
 960
 961         _dp_ctrl_calc_tu(ctrl, &in, tu_table);
 962 }
 963
 964 static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl)
 965 {
 966         u32 dp_tu = 0x0;
 967         u32 valid_boundary = 0x0;
 968         u32 valid_boundary2 = 0x0;
 969         struct dp_vc_tu_mapping_table tu_calc_table;
 970
 971         dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table);
 972
 973         dp_tu |= tu_calc_table.tu_size_minus1;
 974         valid_boundary |= tu_calc_table.valid_boundary_link;
 975         valid_boundary |= (tu_calc_table.delay_start_link << 16);
 976
 977         valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1);
 978         valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16);
 979         valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20);
 980
 981         if (tu_calc_table.boundary_moderation_en)
 982                 valid_boundary2 |= BIT(0);
 983
 984         pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n",
 985                         dp_tu, valid_boundary, valid_boundary2);
 986
 987         dp_catalog_ctrl_update_transfer_unit(ctrl->catalog,
 988                                 dp_tu, valid_boundary, valid_boundary2);
 989 }
 990
 991 static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl)
 992 {
 993         int ret = 0;
 994
 995         if (!wait_for_completion_timeout(&ctrl->video_comp,
 996                                 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) {
 997                 DRM_ERROR("wait4video timedout\n");
 998                 ret = -ETIMEDOUT;
 999         }
1000         return ret;
1001 }
1002
1003 static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
1004 {
1005         struct dp_link *link = ctrl->link;
1006         int ret = 0, lane, lane_cnt;
1007         u8 buf[4];
1008         u32 max_level_reached = 0;
1009         u32 voltage_swing_level = link->phy_params.v_level;
1010         u32 pre_emphasis_level = link->phy_params.p_level;
1011
1012         drm_dbg_dp(ctrl->drm_dev,
1013                 "voltage level: %d emphasis level: %d\n",
1014                         voltage_swing_level, pre_emphasis_level);
1015         ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1016                 voltage_swing_level, pre_emphasis_level);
1017
1018         if (ret)
1019                 return ret;
1020
1021         if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) {
1022                 drm_dbg_dp(ctrl->drm_dev,
1023                                 "max. voltage swing level reached %d\n",
1024                                 voltage_swing_level);
1025                 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
1026         }
1027
1028         if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) {
1029                 drm_dbg_dp(ctrl->drm_dev,
1030                                 "max. pre-emphasis level reached %d\n",
1031                                 pre_emphasis_level);
1032                 max_level_reached  |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1033         }
1034
1035         pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;
1036
1037         lane_cnt = ctrl->link->link_params.num_lanes;
1038         for (lane = 0; lane < lane_cnt; lane++)
1039                 buf[lane] = voltage_swing_level | pre_emphasis_level
1040                                 | max_level_reached;
1041
1042         drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n",
1043                         voltage_swing_level | pre_emphasis_level);
1044         ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET,
1045                                         buf, lane_cnt);
1046         if (ret == lane_cnt)
1047                 ret = 0;
1048
1049         return ret;
1050 }
1051
1052 static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl,
1053                 u8 pattern)
1054 {
1055         u8 buf;
1056         int ret = 0;
1057
1058         drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern);
1059
1060         buf = pattern;
1061
1062         if (pattern && pattern != DP_TRAINING_PATTERN_4)
1063                 buf |= DP_LINK_SCRAMBLING_DISABLE;
1064
1065         ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf);
1066         return ret == 1;
1067 }
1068
1069 static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,
1070                                     u8 *link_status)
1071 {
1072         int ret = 0, len;
1073
1074         len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1075         if (len != DP_LINK_STATUS_SIZE) {
1076                 DRM_ERROR("DP link status read failed, err: %d\n", len);
1077                 ret = -EINVAL;
1078         }
1079
1080         return ret;
1081 }
1082
1083 static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,
1084                         int *training_step)
1085 {
1086         int tries, old_v_level, ret = 0;
1087         u8 link_status[DP_LINK_STATUS_SIZE];
1088         int const maximum_retries = 4;
1089
1090         dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1091
1092         *training_step = DP_TRAINING_1;
1093
1094         ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1);
1095         if (ret)
1096                 return ret;
1097         dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
1098                 DP_LINK_SCRAMBLING_DISABLE);
1099
1100         ret = dp_ctrl_update_vx_px(ctrl);
1101         if (ret)
1102                 return ret;
1103
1104         tries = 0;
1105         old_v_level = ctrl->link->phy_params.v_level;
1106         for (tries = 0; tries < maximum_retries; tries++) {
1107                 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd);
1108
1109                 ret = dp_ctrl_read_link_status(ctrl, link_status);
1110                 if (ret)
1111                         return ret;
1112
1113                 if (drm_dp_clock_recovery_ok(link_status,
1114                         ctrl->link->link_params.num_lanes)) {
1115                         return 0;
1116                 }
1117
1118                 if (ctrl->link->phy_params.v_level >=
1119                         DP_TRAIN_VOLTAGE_SWING_MAX) {
1120                         DRM_ERROR_RATELIMITED("max v_level reached\n");
1121                         return -EAGAIN;
1122                 }
1123
1124                 if (old_v_level != ctrl->link->phy_params.v_level) {
1125                         tries = 0;
1126                         old_v_level = ctrl->link->phy_params.v_level;
1127                 }
1128
1129                 dp_link_adjust_levels(ctrl->link, link_status);
1130                 ret = dp_ctrl_update_vx_px(ctrl);
1131                 if (ret)
1132                         return ret;
1133         }
1134
1135         DRM_ERROR("max tries reached\n");
1136         return -ETIMEDOUT;
1137 }
1138
1139 static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl)
1140 {
1141         int ret = 0;
1142
1143         switch (ctrl->link->link_params.rate) {
1144         case 810000:
1145                 ctrl->link->link_params.rate = 540000;
1146                 break;
1147         case 540000:
1148                 ctrl->link->link_params.rate = 270000;
1149                 break;
1150         case 270000:
1151                 ctrl->link->link_params.rate = 162000;
1152                 break;
1153         case 162000:
1154         default:
1155                 ret = -EINVAL;
1156                 break;
1157         }
1158
1159         if (!ret) {
1160                 drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n",
1161                                 ctrl->link->link_params.rate);
1162         }
1163
1164         return ret;
1165 }
1166
1167 static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl)
1168 {
1169
1170         if (ctrl->link->link_params.num_lanes == 1)
1171                 return -1;
1172
1173         ctrl->link->link_params.num_lanes /= 2;
1174         ctrl->link->link_params.rate = ctrl->panel->link_info.rate;
1175
1176         ctrl->link->phy_params.p_level = 0;
1177         ctrl->link->phy_params.v_level = 0;
1178
1179         return 0;
1180 }
1181
1182 static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
1183 {
1184         dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE);
1185         drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1186 }
1187
1188 static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl,
1189                         int *training_step)
1190 {
1191         int tries = 0, ret = 0;
1192         u8 pattern;
1193         u32 state_ctrl_bit;
1194         int const maximum_retries = 5;
1195         u8 link_status[DP_LINK_STATUS_SIZE];
1196
1197         dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1198
1199         *training_step = DP_TRAINING_2;
1200
1201         if (drm_dp_tps4_supported(ctrl->panel->dpcd)) {
1202                 pattern = DP_TRAINING_PATTERN_4;
1203                 state_ctrl_bit = 4;
1204         } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) {
1205                 pattern = DP_TRAINING_PATTERN_3;
1206                 state_ctrl_bit = 3;
1207         } else {
1208                 pattern = DP_TRAINING_PATTERN_2;
1209                 state_ctrl_bit = 2;
1210         }
1211
1212         ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit);
1213         if (ret)
1214                 return ret;
1215
1216         dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN);
1217
1218         for (tries = 0; tries <= maximum_retries; tries++) {
1219                 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1220
1221                 ret = dp_ctrl_read_link_status(ctrl, link_status);
1222                 if (ret)
1223                         return ret;
1224
1225                 if (drm_dp_channel_eq_ok(link_status,
1226                         ctrl->link->link_params.num_lanes)) {
1227                         return 0;
1228                 }
1229
1230                 dp_link_adjust_levels(ctrl->link, link_status);
1231                 ret = dp_ctrl_update_vx_px(ctrl);
1232                 if (ret)
1233                         return ret;
1234
1235         }
1236
1237         return -ETIMEDOUT;
1238 }
1239
1240 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl);
1241
1242 static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
1243                         int *training_step)
1244 {
1245         int ret = 0;
1246         const u8 *dpcd = ctrl->panel->dpcd;
1247         u8 encoding = DP_SET_ANSI_8B10B;
1248         u8 ssc;
1249         u8 assr;
1250         struct dp_link_info link_info = {0};
1251
1252         dp_ctrl_config_ctrl(ctrl);
1253
1254         link_info.num_lanes = ctrl->link->link_params.num_lanes;
1255         link_info.rate = ctrl->link->link_params.rate;
1256         link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
1257
1258         dp_aux_link_configure(ctrl->aux, &link_info);
1259
1260         if (drm_dp_max_downspread(dpcd)) {
1261                 ssc = DP_SPREAD_AMP_0_5;
1262                 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1);
1263         }
1264
1265         drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
1266                                 &encoding, 1);
1267
1268         if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
1269                 assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
1270                 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,
1271                                 &assr, 1);
1272         }
1273
1274         ret = dp_ctrl_link_train_1(ctrl, training_step);
1275         if (ret) {
1276                 DRM_ERROR("link training #1 failed. ret=%d\n", ret);
1277                 goto end;
1278         }
1279
1280         /* print success info as this is a result of user initiated action */
1281         drm_dbg_dp(ctrl->drm_dev, "link training #1 successful\n");
1282
1283         ret = dp_ctrl_link_train_2(ctrl, training_step);
1284         if (ret) {
1285                 DRM_ERROR("link training #2 failed. ret=%d\n", ret);
1286                 goto end;
1287         }
1288
1289         /* print success info as this is a result of user initiated action */
1290         drm_dbg_dp(ctrl->drm_dev, "link training #2 successful\n");
1291
1292 end:
1293         dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1294
1295         return ret;
1296 }
1297
1298 static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl,
1299                         int *training_step)
1300 {
1301         int ret = 0;
1302
1303         dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
1304
1305         if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1306                 return ret;
1307
1308         /*
1309          * As part of previous calls, DP controller state might have
1310          * transitioned to PUSH_IDLE. In order to start transmitting
1311          * a link training pattern, we have to first do soft reset.
1312          */
1313
1314         ret = dp_ctrl_link_train(ctrl, training_step);
1315
1316         return ret;
1317 }
1318
1319 static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
1320                         enum dp_pm_type module, char *name, unsigned long rate)
1321 {
1322         u32 num = ctrl->parser->mp[module].num_clk;
1323         struct dss_clk *cfg = ctrl->parser->mp[module].clk_config;
1324
1325         while (num && strcmp(cfg->clk_name, name)) {
1326                 num--;
1327                 cfg++;
1328         }
1329
1330         drm_dbg_dp(ctrl->drm_dev, "setting rate=%lu on clk=%s\n",
1331                                                 rate, name);
1332
1333         if (num)
1334                 cfg->rate = rate;
1335         else
1336                 DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
1337                                 name, rate);
1338 }
1339
1340 static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
1341 {
1342         int ret = 0;
1343         struct dp_io *dp_io = &ctrl->parser->io;
1344         struct phy *phy = dp_io->phy;
1345         struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1346         const u8 *dpcd = ctrl->panel->dpcd;
1347
1348         opts_dp->lanes = ctrl->link->link_params.num_lanes;
1349         opts_dp->link_rate = ctrl->link->link_params.rate / 100;
1350         opts_dp->ssc = drm_dp_max_downspread(dpcd);
1351         dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link",
1352                                         ctrl->link->link_params.rate * 1000);
1353
1354         phy_configure(phy, &dp_io->phy_opts);
1355         phy_power_on(phy);
1356
1357         ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
1358         if (ret)
1359                 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
1360
1361         drm_dbg_dp(ctrl->drm_dev, "link rate=%d pixel_clk=%d\n",
1362                 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
1363
1364         return ret;
1365 }
1366
1367 static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
1368 {
1369         int ret = 0;
1370
1371         dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel",
1372                                         ctrl->dp_ctrl.pixel_rate * 1000);
1373
1374         ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
1375         if (ret)
1376                 DRM_ERROR("Unabled to start pixel clocks. ret=%d\n", ret);
1377
1378         drm_dbg_dp(ctrl->drm_dev, "link rate=%d pixel_clk=%d\n",
1379                         ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
1380
1381         return ret;
1382 }
1383
1384 void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable)
1385 {
1386         struct dp_ctrl_private *ctrl;
1387
1388         ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1389
1390         dp_catalog_ctrl_reset(ctrl->catalog);
1391
1392         /*
1393          * all dp controller programmable registers will not
1394          * be reset to default value after DP_SW_RESET
1395          * therefore interrupt mask bits have to be updated
1396          * to enable/disable interrupts
1397          */
1398         dp_catalog_ctrl_enable_irq(ctrl->catalog, enable);
1399 }
1400
1401 void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl)
1402 {
1403         struct dp_ctrl_private *ctrl;
1404         struct dp_io *dp_io;
1405         struct phy *phy;
1406
1407         ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1408         dp_io = &ctrl->parser->io;
1409         phy = dp_io->phy;
1410
1411         dp_catalog_ctrl_phy_reset(ctrl->catalog);
1412         phy_init(phy);
1413
1414         drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1415                         phy, phy->init_count, phy->power_count);
1416 }
1417
1418 void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl)
1419 {
1420         struct dp_ctrl_private *ctrl;
1421         struct dp_io *dp_io;
1422         struct phy *phy;
1423
1424         ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1425         dp_io = &ctrl->parser->io;
1426         phy = dp_io->phy;
1427
1428         dp_catalog_ctrl_phy_reset(ctrl->catalog);
1429         phy_exit(phy);
1430         drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1431                         phy, phy->init_count, phy->power_count);
1432 }
1433
1434 static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
1435 {
1436         const u8 *dpcd = ctrl->panel->dpcd;
1437
1438         /*
1439          * For better interop experience, used a fixed NVID=0x8000
1440          * whenever connected to a VGA dongle downstream.
1441          */
1442         if (drm_dp_is_branch(dpcd))
1443                 return (drm_dp_has_quirk(&ctrl->panel->desc,
1444                                          DP_DPCD_QUIRK_CONSTANT_N));
1445
1446         return false;
1447 }
1448
1449 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
1450 {
1451         int ret = 0;
1452         struct dp_io *dp_io = &ctrl->parser->io;
1453         struct phy *phy = dp_io->phy;
1454         struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1455
1456         dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1457         opts_dp->lanes = ctrl->link->link_params.num_lanes;
1458         phy_configure(phy, &dp_io->phy_opts);
1459         /*
1460          * Disable and re-enable the mainlink clock since the
1461          * link clock might have been adjusted as part of the
1462          * link maintenance.
1463          */
1464         ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1465         if (ret) {
1466                 DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
1467                 return ret;
1468         }
1469         phy_power_off(phy);
1470         /* hw recommended delay before re-enabling clocks */
1471         msleep(20);
1472
1473         ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1474         if (ret) {
1475                 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret);
1476                 return ret;
1477         }
1478
1479         return ret;
1480 }
1481
1482 static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl)
1483 {
1484         struct dp_io *dp_io;
1485         struct phy *phy;
1486         int ret;
1487
1488         dp_io = &ctrl->parser->io;
1489         phy = dp_io->phy;
1490
1491         dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1492
1493         dp_catalog_ctrl_reset(ctrl->catalog);
1494
1495         ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1496         if (ret) {
1497                 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1498         }
1499
1500         phy_power_off(phy);
1501
1502         /* aux channel down, reinit phy */
1503         phy_exit(phy);
1504         phy_init(phy);
1505
1506         drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1507                         phy, phy->init_count, phy->power_count);
1508         return 0;
1509 }
1510
1511 static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl)
1512 {
1513         int ret = 0;
1514         int training_step = DP_TRAINING_NONE;
1515
1516         dp_ctrl_push_idle(&ctrl->dp_ctrl);
1517
1518         ctrl->link->phy_params.p_level = 0;
1519         ctrl->link->phy_params.v_level = 0;
1520
1521         ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1522
1523         ret = dp_ctrl_setup_main_link(ctrl, &training_step);
1524         if (ret)
1525                 goto end;
1526
1527         dp_ctrl_clear_training_pattern(ctrl);
1528
1529         dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1530
1531         ret = dp_ctrl_wait4video_ready(ctrl);
1532 end:
1533         return ret;
1534 }
1535
1536 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
1537 {
1538         int ret = 0;
1539
1540         if (!ctrl->link->phy_params.phy_test_pattern_sel) {
1541                 drm_dbg_dp(ctrl->drm_dev,
1542                         "no test pattern selected by sink\n");
1543                 return ret;
1544         }
1545
1546         /*
1547          * The global reset will need DP link related clocks to be
1548          * running. Add the global reset just before disabling the
1549          * link clocks and core clocks.
1550          */
1551         ret = dp_ctrl_off(&ctrl->dp_ctrl);
1552         if (ret) {
1553                 DRM_ERROR("failed to disable DP controller\n");
1554                 return ret;
1555         }
1556
1557         ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
1558         if (!ret)
1559                 ret = dp_ctrl_on_stream(&ctrl->dp_ctrl);
1560         else
1561                 DRM_ERROR("failed to enable DP link controller\n");
1562
1563         return ret;
1564 }
1565
1566 static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl)
1567 {
1568         bool success = false;
1569         u32 pattern_sent = 0x0;
1570         u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
1571
1572         drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested);
1573
1574         if (dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1575                         ctrl->link->phy_params.v_level,
1576                         ctrl->link->phy_params.p_level)) {
1577                 DRM_ERROR("Failed to set v/p levels\n");
1578                 return false;
1579         }
1580         dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested);
1581         dp_ctrl_update_vx_px(ctrl);
1582         dp_link_send_test_response(ctrl->link);
1583
1584         pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog);
1585
1586         switch (pattern_sent) {
1587         case MR_LINK_TRAINING1:
1588                 success = (pattern_requested ==
1589                                 DP_PHY_TEST_PATTERN_D10_2);
1590                 break;
1591         case MR_LINK_SYMBOL_ERM:
1592                 success = ((pattern_requested ==
1593                         DP_PHY_TEST_PATTERN_ERROR_COUNT) ||
1594                                 (pattern_requested ==
1595                                 DP_PHY_TEST_PATTERN_CP2520));
1596                 break;
1597         case MR_LINK_PRBS7:
1598                 success = (pattern_requested ==
1599                                 DP_PHY_TEST_PATTERN_PRBS7);
1600                 break;
1601         case MR_LINK_CUSTOM80:
1602                 success = (pattern_requested ==
1603                                 DP_PHY_TEST_PATTERN_80BIT_CUSTOM);
1604                 break;
1605         case MR_LINK_TRAINING4:
1606                 success = (pattern_requested ==
1607                                 DP_PHY_TEST_PATTERN_SEL_MASK);
1608                 break;
1609         default:
1610                 success = false;
1611         }
1612
1613         drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n",
1614                 success ? "success" : "failed", pattern_requested);
1615         return success;
1616 }
1617
1618 void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl)
1619 {
1620         struct dp_ctrl_private *ctrl;
1621         u32 sink_request = 0x0;
1622
1623         if (!dp_ctrl) {
1624                 DRM_ERROR("invalid input\n");
1625                 return;
1626         }
1627
1628         ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1629         sink_request = ctrl->link->sink_request;
1630
1631         if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1632                 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n");
1633                 if (dp_ctrl_process_phy_test_request(ctrl)) {
1634                         DRM_ERROR("process phy_test_req failed\n");
1635                         return;
1636                 }
1637         }
1638
1639         if (sink_request & DP_LINK_STATUS_UPDATED) {
1640                 if (dp_ctrl_link_maintenance(ctrl)) {
1641                         DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1642                         return;
1643                 }
1644         }
1645
1646         if (sink_request & DP_TEST_LINK_TRAINING) {
1647                 dp_link_send_test_response(ctrl->link);
1648                 if (dp_ctrl_link_maintenance(ctrl)) {
1649                         DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1650                         return;
1651                 }
1652         }
1653 }
1654
1655 static bool dp_ctrl_clock_recovery_any_ok(
1656                         const u8 link_status[DP_LINK_STATUS_SIZE],
1657                         int lane_count)
1658 {
1659         int reduced_cnt;
1660
1661         if (lane_count <= 1)
1662                 return false;
1663
1664         /*
1665          * only interested in the lane number after reduced
1666          * lane_count = 4, then only interested in 2 lanes
1667          * lane_count = 2, then only interested in 1 lane
1668          */
1669         reduced_cnt = lane_count >> 1;
1670
1671         return drm_dp_clock_recovery_ok(link_status, reduced_cnt);
1672 }
1673
1674 static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl)
1675 {
1676         u8 link_status[DP_LINK_STATUS_SIZE];
1677         int num_lanes = ctrl->link->link_params.num_lanes;
1678
1679         dp_ctrl_read_link_status(ctrl, link_status);
1680
1681         return drm_dp_channel_eq_ok(link_status, num_lanes);
1682 }
1683
1684 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
1685 {
1686         int rc = 0;
1687         struct dp_ctrl_private *ctrl;
1688         u32 rate = 0;
1689         int link_train_max_retries = 5;
1690         u32 const phy_cts_pixel_clk_khz = 148500;
1691         u8 link_status[DP_LINK_STATUS_SIZE];
1692         unsigned int training_step;
1693
1694         if (!dp_ctrl)
1695                 return -EINVAL;
1696
1697         ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1698
1699         rate = ctrl->panel->link_info.rate;
1700
1701         dp_power_clk_enable(ctrl->power, DP_CORE_PM, true);
1702
1703         if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1704                 drm_dbg_dp(ctrl->drm_dev,
1705                                 "using phy test link parameters\n");
1706                 if (!ctrl->panel->dp_mode.drm_mode.clock)
1707                         ctrl->dp_ctrl.pixel_rate = phy_cts_pixel_clk_khz;
1708         } else {
1709                 ctrl->link->link_params.rate = rate;
1710                 ctrl->link->link_params.num_lanes =
1711                         ctrl->panel->link_info.num_lanes;
1712                 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1713         }
1714
1715         drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%d\n",
1716                 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes,
1717                 ctrl->dp_ctrl.pixel_rate);
1718
1719
1720         rc = dp_ctrl_enable_mainlink_clocks(ctrl);
1721         if (rc)
1722                 return rc;
1723
1724         while (--link_train_max_retries) {
1725                 rc = dp_ctrl_reinitialize_mainlink(ctrl);
1726                 if (rc) {
1727                         DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n",
1728                                         rc);
1729                         break;
1730                 }
1731
1732                 training_step = DP_TRAINING_NONE;
1733                 rc = dp_ctrl_setup_main_link(ctrl, &training_step);
1734                 if (rc == 0) {
1735                         /* training completed successfully */
1736                         break;
1737                 } else if (training_step == DP_TRAINING_1) {
1738                         /* link train_1 failed */
1739                         if (!dp_catalog_link_is_connected(ctrl->catalog))
1740                                 break;
1741
1742                         dp_ctrl_read_link_status(ctrl, link_status);
1743
1744                         rc = dp_ctrl_link_rate_down_shift(ctrl);
1745                         if (rc < 0) { /* already in RBR = 1.6G */
1746                                 if (dp_ctrl_clock_recovery_any_ok(link_status,
1747                                         ctrl->link->link_params.num_lanes)) {
1748                                         /*
1749                                          * some lanes are ready,
1750                                          * reduce lane number
1751                                          */
1752                                         rc = dp_ctrl_link_lane_down_shift(ctrl);
1753                                         if (rc < 0) { /* lane == 1 already */
1754                                                 /* end with failure */
1755                                                 break;
1756                                         }
1757                                 } else {
1758                                         /* end with failure */
1759                                         break; /* lane == 1 already */
1760                                 }
1761                         }
1762                 } else if (training_step == DP_TRAINING_2) {
1763                         /* link train_2 failed */
1764                         if (!dp_catalog_link_is_connected(ctrl->catalog))
1765                                 break;
1766
1767                         dp_ctrl_read_link_status(ctrl, link_status);
1768
1769                         if (!drm_dp_clock_recovery_ok(link_status,
1770                                         ctrl->link->link_params.num_lanes))
1771                                 rc = dp_ctrl_link_rate_down_shift(ctrl);
1772                         else
1773                                 rc = dp_ctrl_link_lane_down_shift(ctrl);
1774
1775                         if (rc < 0) {
1776                                 /* end with failure */
1777                                 break; /* lane == 1 already */
1778                         }
1779
1780                         /* stop link training before start re training  */
1781                         dp_ctrl_clear_training_pattern(ctrl);
1782                 }
1783         }
1784
1785         if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1786                 return rc;
1787
1788         if (rc == 0) {  /* link train successfully */
1789                 /*
1790                  * do not stop train pattern here
1791                  * stop link training at on_stream
1792                  * to pass compliance test
1793                  */
1794         } else  {
1795                 /*
1796                  * link training failed
1797                  * end txing train pattern here
1798                  */
1799                 dp_ctrl_clear_training_pattern(ctrl);
1800
1801                 dp_ctrl_deinitialize_mainlink(ctrl);
1802                 rc = -ECONNRESET;
1803         }
1804
1805         return rc;
1806 }
1807
1808 static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl)
1809 {
1810         int training_step = DP_TRAINING_NONE;
1811
1812         return dp_ctrl_setup_main_link(ctrl, &training_step);
1813 }
1814
1815 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
1816 {
1817         int ret = 0;
1818         bool mainlink_ready = false;
1819         struct dp_ctrl_private *ctrl;
1820         unsigned long pixel_rate_orig;
1821
1822         if (!dp_ctrl)
1823                 return -EINVAL;
1824
1825         ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1826
1827         ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1828
1829         pixel_rate_orig = ctrl->dp_ctrl.pixel_rate;
1830         if (dp_ctrl->wide_bus_en)
1831                 ctrl->dp_ctrl.pixel_rate >>= 1;
1832
1833         drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%d\n",
1834                 ctrl->link->link_params.rate,
1835                 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
1836
1837         if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */
1838                 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1839                 if (ret) {
1840                         DRM_ERROR("Failed to start link clocks. ret=%d\n", ret);
1841                         goto end;
1842                 }
1843         }
1844
1845         ret = dp_ctrl_enable_stream_clocks(ctrl);
1846         if (ret) {
1847                 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
1848                 goto end;
1849         }
1850
1851         if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1852                 dp_ctrl_send_phy_test_pattern(ctrl);
1853                 return 0;
1854         }
1855
1856         if (!dp_ctrl_channel_eq_ok(ctrl))
1857                 dp_ctrl_link_retrain(ctrl);
1858
1859         /* stop txing train pattern to end link training */
1860         dp_ctrl_clear_training_pattern(ctrl);
1861
1862         /*
1863          * Set up transfer unit values and set controller state to send
1864          * video.
1865          */
1866         reinit_completion(&ctrl->video_comp);
1867
1868         dp_ctrl_configure_source_params(ctrl);
1869
1870         dp_catalog_ctrl_config_msa(ctrl->catalog,
1871                 ctrl->link->link_params.rate,
1872                 pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl));
1873
1874         dp_ctrl_setup_tr_unit(ctrl);
1875
1876         dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1877
1878         ret = dp_ctrl_wait4video_ready(ctrl);
1879         if (ret)
1880                 return ret;
1881
1882         mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog);
1883         drm_dbg_dp(ctrl->drm_dev,
1884                 "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY");
1885
1886 end:
1887         return ret;
1888 }
1889
1890 int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
1891 {
1892         struct dp_ctrl_private *ctrl;
1893         struct dp_io *dp_io;
1894         struct phy *phy;
1895         int ret;
1896
1897         ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1898         dp_io = &ctrl->parser->io;
1899         phy = dp_io->phy;
1900
1901         /* set dongle to D3 (power off) mode */
1902         dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
1903
1904         dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1905
1906         if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) {
1907                 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1908                 if (ret) {
1909                         DRM_ERROR("Failed to disable pclk. ret=%d\n", ret);
1910                         return ret;
1911                 }
1912         }
1913
1914         ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1915         if (ret) {
1916                 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1917                 return ret;
1918         }
1919
1920         phy_power_off(phy);
1921
1922         /* aux channel down, reinit phy */
1923         phy_exit(phy);
1924         phy_init(phy);
1925
1926         drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1927                         phy, phy->init_count, phy->power_count);
1928         return ret;
1929 }
1930
1931 int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl)
1932 {
1933         struct dp_ctrl_private *ctrl;
1934         struct dp_io *dp_io;
1935         struct phy *phy;
1936         int ret;
1937
1938         ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1939         dp_io = &ctrl->parser->io;
1940         phy = dp_io->phy;
1941
1942         dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1943
1944         ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1945         if (ret) {
1946                 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1947         }
1948
1949         DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n",
1950                 phy, phy->init_count, phy->power_count);
1951
1952         phy_power_off(phy);
1953
1954         DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n",
1955                 phy, phy->init_count, phy->power_count);
1956
1957         return ret;
1958 }
1959
1960 int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
1961 {
1962         struct dp_ctrl_private *ctrl;
1963         struct dp_io *dp_io;
1964         struct phy *phy;
1965         int ret = 0;
1966
1967         if (!dp_ctrl)
1968                 return -EINVAL;
1969
1970         ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1971         dp_io = &ctrl->parser->io;
1972         phy = dp_io->phy;
1973
1974         dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1975
1976         dp_catalog_ctrl_reset(ctrl->catalog);
1977
1978         ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1979         if (ret)
1980                 DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret);
1981
1982         ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1983         if (ret) {
1984                 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1985         }
1986
1987         phy_power_off(phy);
1988         drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1989                         phy, phy->init_count, phy->power_count);
1990
1991         return ret;
1992 }
1993
1994 void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
1995 {
1996         struct dp_ctrl_private *ctrl;
1997         u32 isr;
1998
1999         if (!dp_ctrl)
2000                 return;
2001
2002         ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
2003
2004         isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
2005
2006         if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
2007                 drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n");
2008                 complete(&ctrl->video_comp);
2009         }
2010
2011         if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) {
2012                 drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n");
2013                 complete(&ctrl->idle_comp);
2014         }
2015 }
2016
2017 struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
2018                         struct dp_panel *panel, struct drm_dp_aux *aux,
2019                         struct dp_power *power, struct dp_catalog *catalog,
2020                         struct dp_parser *parser)
2021 {
2022         struct dp_ctrl_private *ctrl;
2023         int ret;
2024
2025         if (!dev || !panel || !aux ||
2026             !link || !catalog) {
2027                 DRM_ERROR("invalid input\n");
2028                 return ERR_PTR(-EINVAL);
2029         }
2030
2031         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2032         if (!ctrl) {
2033                 DRM_ERROR("Mem allocation failure\n");
2034                 return ERR_PTR(-ENOMEM);
2035         }
2036
2037         ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
2038         if (ret) {
2039                 dev_err(dev, "invalid DP OPP table in device tree\n");
2040                 /* caller do PTR_ERR(opp_table) */
2041                 return (struct dp_ctrl *)ERR_PTR(ret);
2042         }
2043
2044         /* OPP table is optional */
2045         ret = devm_pm_opp_of_add_table(dev);
2046         if (ret)
2047                 dev_err(dev, "failed to add DP OPP table\n");
2048
2049         init_completion(&ctrl->idle_comp);
2050         init_completion(&ctrl->video_comp);
2051
2052         /* in parameters */
2053         ctrl->parser   = parser;
2054         ctrl->panel    = panel;
2055         ctrl->power    = power;
2056         ctrl->aux      = aux;
2057         ctrl->link     = link;
2058         ctrl->catalog  = catalog;
2059         ctrl->dev      = dev;
2060
2061         return &ctrl->dp_ctrl;
2062 }