1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/delay.h>
9 #include <linux/interconnect.h>
10 #include <linux/of_irq.h>
12 #include <drm/drm_debugfs.h>
13 #include <drm/drm_drv.h>
14 #include <drm/drm_file.h>
15 #include <drm/drm_vblank.h>
22 static int mdp5_hw_init(struct msm_kms *kms)
24 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
25 struct device *dev = &mdp5_kms->pdev->dev;
28 pm_runtime_get_sync(dev);
30 /* Magic unknown register writes:
32 * W VBIF:0x004 00000001 (mdss_mdp.c:839)
33 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839)
34 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839)
35 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839)
36 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839)
37 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839)
38 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839)
39 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839)
40 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839)
42 * Downstream fbdev driver gets these register offsets/values
43 * from DT.. not really sure what these registers are or if
44 * different values for different boards/SoC's, etc. I guess
45 * they are the golden registers.
47 * Not setting these does not seem to cause any problem. But
48 * we may be getting lucky with the bootloader initializing
49 * them for us. OTOH, if we can always count on the bootloader
50 * setting the golden registers, then perhaps we don't need to
54 spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
55 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
56 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
58 mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
60 pm_runtime_put_sync(dev);
65 /* Global/shared object state funcs */
68 * This is a helper that returns the private state currently in operation.
69 * Note that this would return the "old_state" if called in the atomic check
70 * path, and the "new_state" after the atomic swap has been done.
72 struct mdp5_global_state *
73 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms)
75 return to_mdp5_global_state(mdp5_kms->glob_state.state);
79 * This acquires the modeset lock set aside for global state, creates
80 * a new duplicated private object state.
82 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s)
84 struct msm_drm_private *priv = s->dev->dev_private;
85 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
86 struct drm_private_state *priv_state;
89 ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx);
93 priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state);
94 if (IS_ERR(priv_state))
95 return ERR_CAST(priv_state);
97 return to_mdp5_global_state(priv_state);
100 static struct drm_private_state *
101 mdp5_global_duplicate_state(struct drm_private_obj *obj)
103 struct mdp5_global_state *state;
105 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
109 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
114 static void mdp5_global_destroy_state(struct drm_private_obj *obj,
115 struct drm_private_state *state)
117 struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state);
122 static const struct drm_private_state_funcs mdp5_global_state_funcs = {
123 .atomic_duplicate_state = mdp5_global_duplicate_state,
124 .atomic_destroy_state = mdp5_global_destroy_state,
127 static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms)
129 struct mdp5_global_state *state;
131 drm_modeset_lock_init(&mdp5_kms->glob_state_lock);
133 state = kzalloc(sizeof(*state), GFP_KERNEL);
137 state->mdp5_kms = mdp5_kms;
139 drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state,
141 &mdp5_global_state_funcs);
145 static void mdp5_enable_commit(struct msm_kms *kms)
147 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
148 pm_runtime_get_sync(&mdp5_kms->pdev->dev);
151 static void mdp5_disable_commit(struct msm_kms *kms)
153 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
154 pm_runtime_put_sync(&mdp5_kms->pdev->dev);
157 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
159 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
160 struct mdp5_global_state *global_state;
162 global_state = mdp5_get_existing_global_state(mdp5_kms);
165 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp);
168 static void mdp5_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
173 static void mdp5_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
175 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
176 struct drm_crtc *crtc;
178 for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask)
179 mdp5_crtc_wait_for_commit_done(crtc);
182 static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
184 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
185 struct mdp5_global_state *global_state;
187 global_state = mdp5_get_existing_global_state(mdp5_kms);
190 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp);
193 static int mdp5_set_split_display(struct msm_kms *kms,
194 struct drm_encoder *encoder,
195 struct drm_encoder *slave_encoder,
199 return mdp5_cmd_encoder_set_split_display(encoder,
202 return mdp5_vid_encoder_set_split_display(encoder,
206 static void mdp5_destroy(struct mdp5_kms *mdp5_kms);
208 static void mdp5_kms_destroy(struct msm_kms *kms)
210 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
211 struct msm_gem_address_space *aspace = kms->aspace;
214 for (i = 0; i < mdp5_kms->num_hwmixers; i++)
215 mdp5_mixer_destroy(mdp5_kms->hwmixers[i]);
217 for (i = 0; i < mdp5_kms->num_hwpipes; i++)
218 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]);
221 aspace->mmu->funcs->detach(aspace->mmu);
222 msm_gem_address_space_put(aspace);
225 mdp_kms_destroy(&mdp5_kms->base);
226 mdp5_destroy(mdp5_kms);
229 #ifdef CONFIG_DEBUG_FS
230 static int smp_show(struct seq_file *m, void *arg)
232 struct drm_info_node *node = m->private;
233 struct drm_device *dev = node->minor->dev;
234 struct msm_drm_private *priv = dev->dev_private;
235 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
236 struct drm_printer p = drm_seq_file_printer(m);
238 if (!mdp5_kms->smp) {
239 drm_printf(&p, "no SMP pool\n");
243 mdp5_smp_dump(mdp5_kms->smp, &p);
248 static struct drm_info_list mdp5_debugfs_list[] = {
252 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
254 drm_debugfs_create_files(mdp5_debugfs_list,
255 ARRAY_SIZE(mdp5_debugfs_list),
256 minor->debugfs_root, minor);
262 static const struct mdp_kms_funcs kms_funcs = {
264 .hw_init = mdp5_hw_init,
265 .irq_preinstall = mdp5_irq_preinstall,
266 .irq_postinstall = mdp5_irq_postinstall,
267 .irq_uninstall = mdp5_irq_uninstall,
269 .enable_vblank = mdp5_enable_vblank,
270 .disable_vblank = mdp5_disable_vblank,
271 .flush_commit = mdp5_flush_commit,
272 .enable_commit = mdp5_enable_commit,
273 .disable_commit = mdp5_disable_commit,
274 .prepare_commit = mdp5_prepare_commit,
275 .wait_flush = mdp5_wait_flush,
276 .complete_commit = mdp5_complete_commit,
277 .get_format = mdp_get_format,
278 .set_split_display = mdp5_set_split_display,
279 .destroy = mdp5_kms_destroy,
280 #ifdef CONFIG_DEBUG_FS
281 .debugfs_init = mdp5_kms_debugfs_init,
284 .set_irqmask = mdp5_set_irqmask,
287 static int mdp5_disable(struct mdp5_kms *mdp5_kms)
291 mdp5_kms->enable_count--;
292 WARN_ON(mdp5_kms->enable_count < 0);
294 clk_disable_unprepare(mdp5_kms->tbu_rt_clk);
295 clk_disable_unprepare(mdp5_kms->tbu_clk);
296 clk_disable_unprepare(mdp5_kms->ahb_clk);
297 clk_disable_unprepare(mdp5_kms->axi_clk);
298 clk_disable_unprepare(mdp5_kms->core_clk);
299 clk_disable_unprepare(mdp5_kms->lut_clk);
304 static int mdp5_enable(struct mdp5_kms *mdp5_kms)
308 mdp5_kms->enable_count++;
310 clk_prepare_enable(mdp5_kms->ahb_clk);
311 clk_prepare_enable(mdp5_kms->axi_clk);
312 clk_prepare_enable(mdp5_kms->core_clk);
313 clk_prepare_enable(mdp5_kms->lut_clk);
314 clk_prepare_enable(mdp5_kms->tbu_clk);
315 clk_prepare_enable(mdp5_kms->tbu_rt_clk);
320 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
321 struct mdp5_interface *intf,
322 struct mdp5_ctl *ctl)
324 struct drm_device *dev = mdp5_kms->dev;
325 struct drm_encoder *encoder;
327 encoder = mdp5_encoder_init(dev, intf, ctl);
328 if (IS_ERR(encoder)) {
329 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n");
336 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
338 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
339 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
342 for (i = 0; i < intf_cnt; i++) {
343 if (intfs[i] == INTF_DSI) {
354 static int modeset_init_intf(struct mdp5_kms *mdp5_kms,
355 struct mdp5_interface *intf)
357 struct drm_device *dev = mdp5_kms->dev;
358 struct msm_drm_private *priv = dev->dev_private;
359 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm;
360 struct mdp5_ctl *ctl;
361 struct drm_encoder *encoder;
364 switch (intf->type) {
366 DRM_DEV_INFO(dev->dev, "Skipping eDP interface %d\n", intf->num);
372 ctl = mdp5_ctlm_request(ctlm, intf->num);
378 encoder = construct_encoder(mdp5_kms, intf, ctl);
379 if (IS_ERR(encoder)) {
380 ret = PTR_ERR(encoder);
384 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
388 const struct mdp5_cfg_hw *hw_cfg =
389 mdp5_cfg_get_hw_config(mdp5_kms->cfg);
390 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num);
392 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) {
393 DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n",
399 if (!priv->dsi[dsi_id])
402 ctl = mdp5_ctlm_request(ctlm, intf->num);
408 encoder = construct_encoder(mdp5_kms, intf, ctl);
409 if (IS_ERR(encoder)) {
410 ret = PTR_ERR(encoder);
414 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
416 mdp5_encoder_set_intf_mode(encoder, msm_dsi_is_cmd_mode(priv->dsi[dsi_id]));
421 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type);
429 static int modeset_init(struct mdp5_kms *mdp5_kms)
431 struct drm_device *dev = mdp5_kms->dev;
432 struct msm_drm_private *priv = dev->dev_private;
433 unsigned int num_crtcs;
434 int i, ret, pi = 0, ci = 0;
435 struct drm_plane *primary[MAX_BASES] = { NULL };
436 struct drm_plane *cursor[MAX_BASES] = { NULL };
437 struct drm_encoder *encoder;
438 unsigned int num_encoders;
441 * Construct encoders and modeset initialize connector devices
442 * for each external display interface.
444 for (i = 0; i < mdp5_kms->num_intfs; i++) {
445 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]);
451 drm_for_each_encoder(encoder, dev)
455 * We should ideally have less number of encoders (set up by parsing
456 * the MDP5 interfaces) than the number of layer mixers present in HW,
457 * but let's be safe here anyway
459 num_crtcs = min(num_encoders, mdp5_kms->num_hwmixers);
462 * Construct planes equaling the number of hw pipes, and CRTCs for the
463 * N encoders set up by the driver. The first N planes become primary
464 * planes for the CRTCs, with the remainder as overlay planes:
466 for (i = 0; i < mdp5_kms->num_hwpipes; i++) {
467 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i];
468 struct drm_plane *plane;
469 enum drm_plane_type type;
472 type = DRM_PLANE_TYPE_PRIMARY;
473 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR)
474 type = DRM_PLANE_TYPE_CURSOR;
476 type = DRM_PLANE_TYPE_OVERLAY;
478 plane = mdp5_plane_init(dev, type);
480 ret = PTR_ERR(plane);
481 DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret);
485 if (type == DRM_PLANE_TYPE_PRIMARY)
486 primary[pi++] = plane;
487 if (type == DRM_PLANE_TYPE_CURSOR)
488 cursor[ci++] = plane;
491 for (i = 0; i < num_crtcs; i++) {
492 struct drm_crtc *crtc;
494 crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i);
497 DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret);
504 * Now that we know the number of crtcs we've created, set the possible
505 * crtcs for the encoders
507 drm_for_each_encoder(encoder, dev)
508 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
516 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms,
517 u32 *major, u32 *minor)
519 struct device *dev = &mdp5_kms->pdev->dev;
522 pm_runtime_get_sync(dev);
523 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION);
524 pm_runtime_put_sync(dev);
526 *major = FIELD(version, MDP5_HW_VERSION_MAJOR);
527 *minor = FIELD(version, MDP5_HW_VERSION_MINOR);
529 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor);
532 static int get_clk(struct platform_device *pdev, struct clk **clkp,
533 const char *name, bool mandatory)
535 struct device *dev = &pdev->dev;
536 struct clk *clk = msm_clk_get(pdev, name);
537 if (IS_ERR(clk) && mandatory) {
538 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
542 DBG("skipping %s", name);
549 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev);
551 static int mdp5_kms_init(struct drm_device *dev)
553 struct msm_drm_private *priv = dev->dev_private;
554 struct platform_device *pdev;
555 struct mdp5_kms *mdp5_kms;
556 struct mdp5_cfg *config;
558 struct msm_gem_address_space *aspace;
561 ret = mdp5_init(to_platform_device(dev->dev), dev);
565 /* priv->kms would have been populated by the MDP5 driver */
570 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
571 pdev = mdp5_kms->pdev;
573 ret = mdp_kms_init(&mdp5_kms->base, &kms_funcs);
575 DRM_DEV_ERROR(&pdev->dev, "failed to init kms\n");
579 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
582 DRM_DEV_ERROR(&pdev->dev, "failed to get irq\n");
588 config = mdp5_cfg_get_config(mdp5_kms->cfg);
590 /* make sure things are off before attaching iommu (bootloader could
591 * have left things on, in which case we'll start getting faults if
594 pm_runtime_get_sync(&pdev->dev);
595 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
596 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||
597 !config->hw->intf.base[i])
599 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
601 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3);
605 aspace = msm_kms_init_aspace(mdp5_kms->dev);
606 if (IS_ERR(aspace)) {
607 ret = PTR_ERR(aspace);
611 kms->aspace = aspace;
613 pm_runtime_put_sync(&pdev->dev);
615 ret = modeset_init(mdp5_kms);
617 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret);
621 dev->mode_config.min_width = 0;
622 dev->mode_config.min_height = 0;
623 dev->mode_config.max_width = 0xffff;
624 dev->mode_config.max_height = 0xffff;
626 dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */
627 dev->vblank_disable_immediate = true;
632 mdp5_kms_destroy(kms);
637 static void mdp5_destroy(struct mdp5_kms *mdp5_kms)
642 mdp5_ctlm_destroy(mdp5_kms->ctlm);
644 mdp5_smp_destroy(mdp5_kms->smp);
646 mdp5_cfg_destroy(mdp5_kms->cfg);
648 for (i = 0; i < mdp5_kms->num_intfs; i++)
649 kfree(mdp5_kms->intfs[i]);
651 if (mdp5_kms->rpm_enabled)
652 pm_runtime_disable(&mdp5_kms->pdev->dev);
654 drm_atomic_private_obj_fini(&mdp5_kms->glob_state);
655 drm_modeset_lock_fini(&mdp5_kms->glob_state_lock);
658 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
659 const enum mdp5_pipe *pipes, const uint32_t *offsets,
662 struct drm_device *dev = mdp5_kms->dev;
665 for (i = 0; i < cnt; i++) {
666 struct mdp5_hw_pipe *hwpipe;
668 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps);
669 if (IS_ERR(hwpipe)) {
670 ret = PTR_ERR(hwpipe);
671 DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n",
672 pipe2name(pipes[i]), ret);
675 hwpipe->idx = mdp5_kms->num_hwpipes;
676 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe;
682 static int hwpipe_init(struct mdp5_kms *mdp5_kms)
684 static const enum mdp5_pipe rgb_planes[] = {
685 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
687 static const enum mdp5_pipe vig_planes[] = {
688 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
690 static const enum mdp5_pipe dma_planes[] = {
691 SSPP_DMA0, SSPP_DMA1,
693 static const enum mdp5_pipe cursor_planes[] = {
694 SSPP_CURSOR0, SSPP_CURSOR1,
696 const struct mdp5_cfg_hw *hw_cfg;
699 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
701 /* Construct RGB pipes: */
702 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes,
703 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps);
707 /* Construct video (VIG) pipes: */
708 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes,
709 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps);
713 /* Construct DMA pipes: */
714 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes,
715 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps);
719 /* Construct cursor pipes: */
720 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count,
721 cursor_planes, hw_cfg->pipe_cursor.base,
722 hw_cfg->pipe_cursor.caps);
729 static int hwmixer_init(struct mdp5_kms *mdp5_kms)
731 struct drm_device *dev = mdp5_kms->dev;
732 const struct mdp5_cfg_hw *hw_cfg;
735 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
737 for (i = 0; i < hw_cfg->lm.count; i++) {
738 struct mdp5_hw_mixer *mixer;
740 mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]);
742 ret = PTR_ERR(mixer);
743 DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n",
748 mixer->idx = mdp5_kms->num_hwmixers;
749 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer;
755 static int interface_init(struct mdp5_kms *mdp5_kms)
757 struct drm_device *dev = mdp5_kms->dev;
758 const struct mdp5_cfg_hw *hw_cfg;
759 const enum mdp5_intf_type *intf_types;
762 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
763 intf_types = hw_cfg->intf.connect;
765 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
766 struct mdp5_interface *intf;
768 if (intf_types[i] == INTF_DISABLED)
771 intf = kzalloc(sizeof(*intf), GFP_KERNEL);
773 DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i);
778 intf->type = intf_types[i];
779 intf->mode = MDP5_INTF_MODE_NONE;
780 intf->idx = mdp5_kms->num_intfs;
781 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf;
787 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
789 struct msm_drm_private *priv = dev->dev_private;
790 struct mdp5_kms *mdp5_kms;
791 struct mdp5_cfg *config;
795 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL);
801 spin_lock_init(&mdp5_kms->resource_lock);
804 mdp5_kms->pdev = pdev;
806 ret = mdp5_global_obj_init(mdp5_kms);
810 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys");
811 if (IS_ERR(mdp5_kms->mmio)) {
812 ret = PTR_ERR(mdp5_kms->mmio);
816 /* mandatory clocks: */
817 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true);
820 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true);
823 ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true);
826 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true);
830 /* optional clocks: */
831 get_clk(pdev, &mdp5_kms->lut_clk, "lut", false);
832 get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false);
833 get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false);
835 /* we need to set a default rate before enabling. Set a safe
836 * rate first, then figure out hw revision, and then set a
839 clk_set_rate(mdp5_kms->core_clk, 200000000);
841 /* set uninit-ed kms */
842 priv->kms = &mdp5_kms->base.base;
844 pm_runtime_enable(&pdev->dev);
845 mdp5_kms->rpm_enabled = true;
847 read_mdp_hw_revision(mdp5_kms, &major, &minor);
849 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
850 if (IS_ERR(mdp5_kms->cfg)) {
851 ret = PTR_ERR(mdp5_kms->cfg);
852 mdp5_kms->cfg = NULL;
856 config = mdp5_cfg_get_config(mdp5_kms->cfg);
857 mdp5_kms->caps = config->hw->mdp.caps;
859 /* TODO: compute core clock rate at runtime */
860 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);
863 * Some chipsets have a Shared Memory Pool (SMP), while others
864 * have dedicated latency buffering per source pipe instead;
865 * this section initializes the SMP:
867 if (mdp5_kms->caps & MDP_CAP_SMP) {
868 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp);
869 if (IS_ERR(mdp5_kms->smp)) {
870 ret = PTR_ERR(mdp5_kms->smp);
871 mdp5_kms->smp = NULL;
876 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);
877 if (IS_ERR(mdp5_kms->ctlm)) {
878 ret = PTR_ERR(mdp5_kms->ctlm);
879 mdp5_kms->ctlm = NULL;
883 ret = hwpipe_init(mdp5_kms);
887 ret = hwmixer_init(mdp5_kms);
891 ret = interface_init(mdp5_kms);
898 mdp5_destroy(mdp5_kms);
902 static int mdp5_setup_interconnect(struct platform_device *pdev)
904 struct icc_path *path0 = msm_icc_get(&pdev->dev, "mdp0-mem");
905 struct icc_path *path1 = msm_icc_get(&pdev->dev, "mdp1-mem");
906 struct icc_path *path_rot = msm_icc_get(&pdev->dev, "rotator-mem");
909 return PTR_ERR(path0);
912 /* no interconnect support is not necessarily a fatal
913 * condition, the platform may simply not have an
914 * interconnect driver yet. But warn about it in case
915 * bootloader didn't setup bus clocks high enough for
918 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n");
922 icc_set_bw(path0, 0, MBps_to_icc(6400));
924 if (!IS_ERR_OR_NULL(path1))
925 icc_set_bw(path1, 0, MBps_to_icc(6400));
926 if (!IS_ERR_OR_NULL(path_rot))
927 icc_set_bw(path_rot, 0, MBps_to_icc(6400));
932 static int mdp5_dev_probe(struct platform_device *pdev)
938 ret = mdp5_setup_interconnect(pdev);
942 return msm_drv_probe(&pdev->dev, mdp5_kms_init);
945 static int mdp5_dev_remove(struct platform_device *pdev)
948 component_master_del(&pdev->dev, &msm_drm_ops);
952 static __maybe_unused int mdp5_runtime_suspend(struct device *dev)
954 struct platform_device *pdev = to_platform_device(dev);
955 struct msm_drm_private *priv = platform_get_drvdata(pdev);
956 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
960 return mdp5_disable(mdp5_kms);
963 static __maybe_unused int mdp5_runtime_resume(struct device *dev)
965 struct platform_device *pdev = to_platform_device(dev);
966 struct msm_drm_private *priv = platform_get_drvdata(pdev);
967 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
971 return mdp5_enable(mdp5_kms);
974 static const struct dev_pm_ops mdp5_pm_ops = {
975 SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL)
976 .prepare = msm_pm_prepare,
977 .complete = msm_pm_complete,
980 static const struct of_device_id mdp5_dt_match[] = {
981 { .compatible = "qcom,mdp5", },
982 /* to support downstream DT files */
983 { .compatible = "qcom,mdss_mdp", },
986 MODULE_DEVICE_TABLE(of, mdp5_dt_match);
988 static struct platform_driver mdp5_driver = {
989 .probe = mdp5_dev_probe,
990 .remove = mdp5_dev_remove,
991 .shutdown = msm_drv_shutdown,
994 .of_match_table = mdp5_dt_match,
999 void __init msm_mdp_register(void)
1002 platform_driver_register(&mdp5_driver);
1005 void __exit msm_mdp_unregister(void)
1008 platform_driver_unregister(&mdp5_driver);