1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
7 #include <linux/delay.h>
9 #include <drm/drm_vblank.h>
16 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
18 static int mdp4_hw_init(struct msm_kms *kms)
20 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
21 struct drm_device *dev = mdp4_kms->dev;
25 pm_runtime_get_sync(dev->dev);
27 if (mdp4_kms->rev > 1) {
28 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
29 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
32 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
34 /* max read pending cmd config, 3 pending requests: */
35 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
37 clk = clk_get_rate(mdp4_kms->clk);
39 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
40 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */
41 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */
43 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */
44 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */
47 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
49 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
50 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
52 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
53 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
54 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
55 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
57 if (mdp4_kms->rev >= 2)
58 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
59 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
61 /* disable CSC matrix / YUV by default: */
62 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
63 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
64 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
65 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
66 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
67 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
69 if (mdp4_kms->rev > 1)
70 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
72 pm_runtime_put_sync(dev->dev);
77 static void mdp4_enable_commit(struct msm_kms *kms)
79 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
80 mdp4_enable(mdp4_kms);
83 static void mdp4_disable_commit(struct msm_kms *kms)
85 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
86 mdp4_disable(mdp4_kms);
89 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
93 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
98 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
100 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
101 struct drm_crtc *crtc;
103 for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)
104 mdp4_crtc_wait_for_commit_done(crtc);
107 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
111 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
112 struct drm_encoder *encoder)
114 /* if we had >1 encoder, we'd need something more clever: */
115 switch (encoder->encoder_type) {
116 case DRM_MODE_ENCODER_TMDS:
117 return mdp4_dtv_round_pixclk(encoder, rate);
118 case DRM_MODE_ENCODER_LVDS:
119 case DRM_MODE_ENCODER_DSI:
125 static void mdp4_destroy(struct msm_kms *kms)
127 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
128 struct device *dev = mdp4_kms->dev->dev;
129 struct msm_gem_address_space *aspace = kms->aspace;
131 if (mdp4_kms->blank_cursor_iova)
132 msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
133 drm_gem_object_put(mdp4_kms->blank_cursor_bo);
136 aspace->mmu->funcs->detach(aspace->mmu);
137 msm_gem_address_space_put(aspace);
140 if (mdp4_kms->rpm_enabled)
141 pm_runtime_disable(dev);
143 mdp_kms_destroy(&mdp4_kms->base);
148 static const struct mdp_kms_funcs kms_funcs = {
150 .hw_init = mdp4_hw_init,
151 .irq_preinstall = mdp4_irq_preinstall,
152 .irq_postinstall = mdp4_irq_postinstall,
153 .irq_uninstall = mdp4_irq_uninstall,
155 .enable_vblank = mdp4_enable_vblank,
156 .disable_vblank = mdp4_disable_vblank,
157 .enable_commit = mdp4_enable_commit,
158 .disable_commit = mdp4_disable_commit,
159 .prepare_commit = mdp4_prepare_commit,
160 .flush_commit = mdp4_flush_commit,
161 .wait_flush = mdp4_wait_flush,
162 .complete_commit = mdp4_complete_commit,
163 .get_format = mdp_get_format,
164 .round_pixclk = mdp4_round_pixclk,
165 .destroy = mdp4_destroy,
167 .set_irqmask = mdp4_set_irqmask,
170 int mdp4_disable(struct mdp4_kms *mdp4_kms)
174 clk_disable_unprepare(mdp4_kms->clk);
175 clk_disable_unprepare(mdp4_kms->pclk);
176 clk_disable_unprepare(mdp4_kms->lut_clk);
177 clk_disable_unprepare(mdp4_kms->axi_clk);
182 int mdp4_enable(struct mdp4_kms *mdp4_kms)
186 clk_prepare_enable(mdp4_kms->clk);
187 clk_prepare_enable(mdp4_kms->pclk);
188 clk_prepare_enable(mdp4_kms->lut_clk);
189 clk_prepare_enable(mdp4_kms->axi_clk);
195 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
198 struct drm_device *dev = mdp4_kms->dev;
199 struct msm_drm_private *priv = dev->dev_private;
200 struct drm_encoder *encoder;
201 struct drm_connector *connector;
202 struct device_node *panel_node;
207 case DRM_MODE_ENCODER_LVDS:
209 * bail out early if there is no panel node (no need to
210 * initialize LCDC encoder and LVDS connector)
212 panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0);
216 encoder = mdp4_lcdc_encoder_init(dev, panel_node);
217 if (IS_ERR(encoder)) {
218 DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");
219 return PTR_ERR(encoder);
222 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
223 encoder->possible_crtcs = 1 << DMA_P;
225 connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
226 if (IS_ERR(connector)) {
227 DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");
228 return PTR_ERR(connector);
232 case DRM_MODE_ENCODER_TMDS:
233 encoder = mdp4_dtv_encoder_init(dev);
234 if (IS_ERR(encoder)) {
235 DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n");
236 return PTR_ERR(encoder);
239 /* DTV can be hooked to DMA_E: */
240 encoder->possible_crtcs = 1 << 1;
243 /* Construct bridge/connector for HDMI: */
244 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
246 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret);
252 case DRM_MODE_ENCODER_DSI:
253 /* only DSI1 supported for now */
256 if (!priv->dsi[dsi_id])
259 encoder = mdp4_dsi_encoder_init(dev);
260 if (IS_ERR(encoder)) {
261 ret = PTR_ERR(encoder);
262 DRM_DEV_ERROR(dev->dev,
263 "failed to construct DSI encoder: %d\n", ret);
267 /* TODO: Add DMA_S later? */
268 encoder->possible_crtcs = 1 << DMA_P;
270 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
272 DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n",
279 DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n");
286 static int modeset_init(struct mdp4_kms *mdp4_kms)
288 struct drm_device *dev = mdp4_kms->dev;
289 struct msm_drm_private *priv = dev->dev_private;
290 struct drm_plane *plane;
291 struct drm_crtc *crtc;
293 static const enum mdp4_pipe rgb_planes[] = {
296 static const enum mdp4_pipe vg_planes[] = {
299 static const enum mdp4_dma mdp4_crtcs[] = {
302 static const char * const mdp4_crtc_names[] = {
305 static const int mdp4_intfs[] = {
306 DRM_MODE_ENCODER_LVDS,
307 DRM_MODE_ENCODER_DSI,
308 DRM_MODE_ENCODER_TMDS,
311 /* construct non-private planes: */
312 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
313 plane = mdp4_plane_init(dev, vg_planes[i], false);
315 DRM_DEV_ERROR(dev->dev,
316 "failed to construct plane for VG%d\n", i + 1);
317 ret = PTR_ERR(plane);
322 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
323 plane = mdp4_plane_init(dev, rgb_planes[i], true);
325 DRM_DEV_ERROR(dev->dev,
326 "failed to construct plane for RGB%d\n", i + 1);
327 ret = PTR_ERR(plane);
331 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
334 DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n",
340 priv->crtcs[priv->num_crtcs++] = crtc;
344 * we currently set up two relatively fixed paths:
346 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
348 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
350 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
353 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
354 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
356 DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n",
368 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms,
369 u32 *major, u32 *minor)
371 struct drm_device *dev = mdp4_kms->dev;
374 mdp4_enable(mdp4_kms);
375 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
376 mdp4_disable(mdp4_kms);
378 *major = FIELD(version, MDP4_VERSION_MAJOR);
379 *minor = FIELD(version, MDP4_VERSION_MINOR);
381 DRM_DEV_INFO(dev->dev, "MDP4 version v%d.%d", *major, *minor);
384 static int mdp4_kms_init(struct drm_device *dev)
386 struct platform_device *pdev = to_platform_device(dev->dev);
387 struct mdp4_platform_config *config = mdp4_get_config(pdev);
388 struct msm_drm_private *priv = dev->dev_private;
389 struct mdp4_kms *mdp4_kms;
390 struct msm_kms *kms = NULL;
391 struct msm_gem_address_space *aspace;
395 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
397 DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n");
401 ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs);
403 DRM_DEV_ERROR(dev->dev, "failed to init kms\n");
407 priv->kms = &mdp4_kms->base.base;
412 mdp4_kms->mmio = msm_ioremap(pdev, NULL);
413 if (IS_ERR(mdp4_kms->mmio)) {
414 ret = PTR_ERR(mdp4_kms->mmio);
418 irq = platform_get_irq(pdev, 0);
421 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret);
427 /* NOTE: driver for this regulator still missing upstream.. use
428 * _get_exclusive() and ignore the error if it does not exist
429 * (and hope that the bootloader left it on for us)
431 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
432 if (IS_ERR(mdp4_kms->vdd))
433 mdp4_kms->vdd = NULL;
436 ret = regulator_enable(mdp4_kms->vdd);
438 DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret);
443 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
444 if (IS_ERR(mdp4_kms->clk)) {
445 DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n");
446 ret = PTR_ERR(mdp4_kms->clk);
450 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
451 if (IS_ERR(mdp4_kms->pclk))
452 mdp4_kms->pclk = NULL;
454 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
455 if (IS_ERR(mdp4_kms->axi_clk)) {
456 DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n");
457 ret = PTR_ERR(mdp4_kms->axi_clk);
461 clk_set_rate(mdp4_kms->clk, config->max_clk);
463 read_mdp_hw_revision(mdp4_kms, &major, &minor);
466 DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n",
472 mdp4_kms->rev = minor;
474 if (mdp4_kms->rev >= 2) {
475 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
476 if (IS_ERR(mdp4_kms->lut_clk)) {
477 DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n");
478 ret = PTR_ERR(mdp4_kms->lut_clk);
481 clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
484 pm_runtime_enable(dev->dev);
485 mdp4_kms->rpm_enabled = true;
487 /* make sure things are off before attaching iommu (bootloader could
488 * have left things on, in which case we'll start getting faults if
491 mdp4_enable(mdp4_kms);
492 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
493 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
494 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
495 mdp4_disable(mdp4_kms);
499 struct msm_mmu *mmu = msm_iommu_new(&pdev->dev,
502 aspace = msm_gem_address_space_create(mmu,
503 "mdp4", 0x1000, 0x100000000 - 0x1000);
505 if (IS_ERR(aspace)) {
507 mmu->funcs->destroy(mmu);
508 ret = PTR_ERR(aspace);
512 kms->aspace = aspace;
514 DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
515 "contig buffers for scanout\n");
519 ret = modeset_init(mdp4_kms);
521 DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret);
525 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT);
526 if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
527 ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
528 DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
529 mdp4_kms->blank_cursor_bo = NULL;
533 ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
534 &mdp4_kms->blank_cursor_iova);
536 DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
540 dev->mode_config.min_width = 0;
541 dev->mode_config.min_height = 0;
542 dev->mode_config.max_width = 2048;
543 dev->mode_config.max_height = 2048;
554 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
556 static struct mdp4_platform_config config = {};
558 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
559 config.max_clk = 266667000;
560 config.iommu = iommu_domain_alloc(&platform_bus_type);
565 static const struct dev_pm_ops mdp4_pm_ops = {
566 .prepare = msm_pm_prepare,
567 .complete = msm_pm_complete,
570 static int mdp4_probe(struct platform_device *pdev)
572 return msm_drv_probe(&pdev->dev, mdp4_kms_init);
575 static int mdp4_remove(struct platform_device *pdev)
577 component_master_del(&pdev->dev, &msm_drm_ops);
582 static const struct of_device_id mdp4_dt_match[] = {
583 { .compatible = "qcom,mdp4" },
586 MODULE_DEVICE_TABLE(of, mdp4_dt_match);
588 static struct platform_driver mdp4_platform_driver = {
590 .remove = mdp4_remove,
591 .shutdown = msm_drv_shutdown,
594 .of_match_table = mdp4_dt_match,
599 void __init msm_mdp4_register(void)
601 platform_driver_register(&mdp4_platform_driver);
604 void __exit msm_mdp4_unregister(void)
606 platform_driver_unregister(&mdp4_platform_driver);