drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include "dpu_hwio.h"
   6 #include "dpu_hw_catalog.h"
   7 #include "dpu_hw_top.h"
   8 #include "dpu_kms.h"
   9
  10 #define FLD_SPLIT_DISPLAY_CMD             BIT(1)
  11 #define FLD_SMART_PANEL_FREE_RUN          BIT(2)
  12 #define FLD_INTF_1_SW_TRG_MUX             BIT(4)
  13 #define FLD_INTF_2_SW_TRG_MUX             BIT(8)
  14 #define FLD_TE_LINE_INTER_WATERLEVEL_MASK 0xFFFF
  15
  16 #define TRAFFIC_SHAPER_EN                 BIT(31)
  17 #define TRAFFIC_SHAPER_RD_CLIENT(num)     (0x030 + (num * 4))
  18 #define TRAFFIC_SHAPER_WR_CLIENT(num)     (0x060 + (num * 4))
  19 #define TRAFFIC_SHAPER_FIXPOINT_FACTOR    4
  20
  21 #define MDP_TICK_COUNT                    16
  22 #define XO_CLK_RATE                       19200
  23 #define MS_TICKS_IN_SEC                   1000
  24
  25 #define CALCULATE_WD_LOAD_VALUE(fps) \
  26         ((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps)))
  27
  28 static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
  29                 struct split_pipe_cfg *cfg)
  30 {
  31         struct dpu_hw_blk_reg_map *c;
  32         u32 upper_pipe = 0;
  33         u32 lower_pipe = 0;
  34
  35         if (!mdp || !cfg)
  36                 return;
  37
  38         c = &mdp->hw;
  39
  40         if (cfg->en) {
  41                 if (cfg->mode == INTF_MODE_CMD) {
  42                         lower_pipe = FLD_SPLIT_DISPLAY_CMD;
  43                         /* interface controlling sw trigger */
  44                         if (cfg->intf == INTF_2)
  45                                 lower_pipe |= FLD_INTF_1_SW_TRG_MUX;
  46                         else
  47                                 lower_pipe |= FLD_INTF_2_SW_TRG_MUX;
  48                         upper_pipe = lower_pipe;
  49                 } else {
  50                         if (cfg->intf == INTF_2) {
  51                                 lower_pipe = FLD_INTF_1_SW_TRG_MUX;
  52                                 upper_pipe = FLD_INTF_2_SW_TRG_MUX;
  53                         } else {
  54                                 lower_pipe = FLD_INTF_2_SW_TRG_MUX;
  55                                 upper_pipe = FLD_INTF_1_SW_TRG_MUX;
  56                         }
  57                 }
  58         }
  59
  60         DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0);
  61         DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe);
  62         DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe);
  63         DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
  64 }
  65
  66 static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp,
  67                 enum dpu_clk_ctrl_type clk_ctrl, bool enable)
  68 {
  69         struct dpu_hw_blk_reg_map *c;
  70         u32 reg_off, bit_off;
  71         u32 reg_val, new_val;
  72         bool clk_forced_on;
  73
  74         if (!mdp)
  75                 return false;
  76
  77         c = &mdp->hw;
  78
  79         if (clk_ctrl <= DPU_CLK_CTRL_NONE || clk_ctrl >= DPU_CLK_CTRL_MAX)
  80                 return false;
  81
  82         reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off;
  83         bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off;
  84
  85         reg_val = DPU_REG_READ(c, reg_off);
  86
  87         if (enable)
  88                 new_val = reg_val | BIT(bit_off);
  89         else
  90                 new_val = reg_val & ~BIT(bit_off);
  91
  92         DPU_REG_WRITE(c, reg_off, new_val);
  93
  94         clk_forced_on = !(reg_val & BIT(bit_off));
  95
  96         return clk_forced_on;
  97 }
  98
  99
 100 static void dpu_hw_get_danger_status(struct dpu_hw_mdp *mdp,
 101                 struct dpu_danger_safe_status *status)
 102 {
 103         struct dpu_hw_blk_reg_map *c;
 104         u32 value;
 105
 106         if (!mdp || !status)
 107                 return;
 108
 109         c = &mdp->hw;
 110
 111         value = DPU_REG_READ(c, DANGER_STATUS);
 112         status->mdp = (value >> 0) & 0x3;
 113         status->sspp[SSPP_VIG0] = (value >> 4) & 0x3;
 114         status->sspp[SSPP_VIG1] = (value >> 6) & 0x3;
 115         status->sspp[SSPP_VIG2] = (value >> 8) & 0x3;
 116         status->sspp[SSPP_VIG3] = (value >> 10) & 0x3;
 117         status->sspp[SSPP_RGB0] = (value >> 12) & 0x3;
 118         status->sspp[SSPP_RGB1] = (value >> 14) & 0x3;
 119         status->sspp[SSPP_RGB2] = (value >> 16) & 0x3;
 120         status->sspp[SSPP_RGB3] = (value >> 18) & 0x3;
 121         status->sspp[SSPP_DMA0] = (value >> 20) & 0x3;
 122         status->sspp[SSPP_DMA1] = (value >> 22) & 0x3;
 123         status->sspp[SSPP_DMA2] = (value >> 28) & 0x3;
 124         status->sspp[SSPP_DMA3] = (value >> 30) & 0x3;
 125         status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x3;
 126         status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x3;
 127 }
 128
 129 static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp,
 130                 struct dpu_vsync_source_cfg *cfg)
 131 {
 132         struct dpu_hw_blk_reg_map *c;
 133         u32 reg, wd_load_value, wd_ctl, wd_ctl2;
 134
 135         if (!mdp || !cfg)
 136                 return;
 137
 138         c = &mdp->hw;
 139
 140         if (cfg->vsync_source >= DPU_VSYNC_SOURCE_WD_TIMER_4 &&
 141                         cfg->vsync_source <= DPU_VSYNC_SOURCE_WD_TIMER_0) {
 142                 switch (cfg->vsync_source) {
 143                 case DPU_VSYNC_SOURCE_WD_TIMER_4:
 144                         wd_load_value = MDP_WD_TIMER_4_LOAD_VALUE;
 145                         wd_ctl = MDP_WD_TIMER_4_CTL;
 146                         wd_ctl2 = MDP_WD_TIMER_4_CTL2;
 147                         break;
 148                 case DPU_VSYNC_SOURCE_WD_TIMER_3:
 149                         wd_load_value = MDP_WD_TIMER_3_LOAD_VALUE;
 150                         wd_ctl = MDP_WD_TIMER_3_CTL;
 151                         wd_ctl2 = MDP_WD_TIMER_3_CTL2;
 152                         break;
 153                 case DPU_VSYNC_SOURCE_WD_TIMER_2:
 154                         wd_load_value = MDP_WD_TIMER_2_LOAD_VALUE;
 155                         wd_ctl = MDP_WD_TIMER_2_CTL;
 156                         wd_ctl2 = MDP_WD_TIMER_2_CTL2;
 157                         break;
 158                 case DPU_VSYNC_SOURCE_WD_TIMER_1:
 159                         wd_load_value = MDP_WD_TIMER_1_LOAD_VALUE;
 160                         wd_ctl = MDP_WD_TIMER_1_CTL;
 161                         wd_ctl2 = MDP_WD_TIMER_1_CTL2;
 162                         break;
 163                 case DPU_VSYNC_SOURCE_WD_TIMER_0:
 164                 default:
 165                         wd_load_value = MDP_WD_TIMER_0_LOAD_VALUE;
 166                         wd_ctl = MDP_WD_TIMER_0_CTL;
 167                         wd_ctl2 = MDP_WD_TIMER_0_CTL2;
 168                         break;
 169                 }
 170
 171                 DPU_REG_WRITE(c, wd_load_value,
 172                         CALCULATE_WD_LOAD_VALUE(cfg->frame_rate));
 173
 174                 DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */
 175                 reg = DPU_REG_READ(c, wd_ctl2);
 176                 reg |= BIT(8);          /* enable heartbeat timer */
 177                 reg |= BIT(0);          /* enable WD timer */
 178                 DPU_REG_WRITE(c, wd_ctl2, reg);
 179
 180                 /* make sure that timers are enabled/disabled for vsync state */
 181                 wmb();
 182         }
 183 }
 184
 185 static void dpu_hw_setup_vsync_source_and_vsync_sel(struct dpu_hw_mdp *mdp,
 186                 struct dpu_vsync_source_cfg *cfg)
 187 {
 188         struct dpu_hw_blk_reg_map *c;
 189         u32 reg, i;
 190         static const u32 pp_offset[PINGPONG_MAX] = {0xC, 0x8, 0x4, 0x13, 0x18};
 191
 192         if (!mdp || !cfg || (cfg->pp_count > ARRAY_SIZE(cfg->ppnumber)))
 193                 return;
 194
 195         c = &mdp->hw;
 196
 197         reg = DPU_REG_READ(c, MDP_VSYNC_SEL);
 198         for (i = 0; i < cfg->pp_count; i++) {
 199                 int pp_idx = cfg->ppnumber[i] - PINGPONG_0;
 200
 201                 if (pp_idx >= ARRAY_SIZE(pp_offset))
 202                         continue;
 203
 204                 reg &= ~(0xf << pp_offset[pp_idx]);
 205                 reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx];
 206         }
 207         DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg);
 208
 209         dpu_hw_setup_vsync_source(mdp, cfg);
 210 }
 211
 212 static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp,
 213                 struct dpu_danger_safe_status *status)
 214 {
 215         struct dpu_hw_blk_reg_map *c;
 216         u32 value;
 217
 218         if (!mdp || !status)
 219                 return;
 220
 221         c = &mdp->hw;
 222
 223         value = DPU_REG_READ(c, SAFE_STATUS);
 224         status->mdp = (value >> 0) & 0x1;
 225         status->sspp[SSPP_VIG0] = (value >> 4) & 0x1;
 226         status->sspp[SSPP_VIG1] = (value >> 6) & 0x1;
 227         status->sspp[SSPP_VIG2] = (value >> 8) & 0x1;
 228         status->sspp[SSPP_VIG3] = (value >> 10) & 0x1;
 229         status->sspp[SSPP_RGB0] = (value >> 12) & 0x1;
 230         status->sspp[SSPP_RGB1] = (value >> 14) & 0x1;
 231         status->sspp[SSPP_RGB2] = (value >> 16) & 0x1;
 232         status->sspp[SSPP_RGB3] = (value >> 18) & 0x1;
 233         status->sspp[SSPP_DMA0] = (value >> 20) & 0x1;
 234         status->sspp[SSPP_DMA1] = (value >> 22) & 0x1;
 235         status->sspp[SSPP_DMA2] = (value >> 28) & 0x1;
 236         status->sspp[SSPP_DMA3] = (value >> 30) & 0x1;
 237         status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x1;
 238         status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1;
 239 }
 240
 241 static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp)
 242 {
 243         struct dpu_hw_blk_reg_map *c;
 244
 245         if (!mdp)
 246                 return;
 247
 248         c = &mdp->hw;
 249
 250         DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1);
 251 }
 252
 253 static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
 254                 unsigned long cap)
 255 {
 256         ops->setup_split_pipe = dpu_hw_setup_split_pipe;
 257         ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
 258         ops->get_danger_status = dpu_hw_get_danger_status;
 259
 260         if (cap & BIT(DPU_MDP_VSYNC_SEL))
 261                 ops->setup_vsync_source = dpu_hw_setup_vsync_source_and_vsync_sel;
 262         else
 263                 ops->setup_vsync_source = dpu_hw_setup_vsync_source;
 264
 265         ops->get_safe_status = dpu_hw_get_safe_status;
 266
 267         if (cap & BIT(DPU_MDP_AUDIO_SELECT))
 268                 ops->intf_audio_select = dpu_hw_intf_audio_select;
 269 }
 270
 271 struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,
 272                 void __iomem *addr,
 273                 const struct dpu_mdss_cfg *m)
 274 {
 275         struct dpu_hw_mdp *mdp;
 276
 277         if (!addr)
 278                 return ERR_PTR(-EINVAL);
 279
 280         mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
 281         if (!mdp)
 282                 return ERR_PTR(-ENOMEM);
 283
 284         mdp->hw.blk_addr = addr + cfg->base;
 285         mdp->hw.log_mask = DPU_DBG_MASK_TOP;
 286
 287         /*
 288          * Assign ops
 289          */
 290         mdp->caps = cfg;
 291         _setup_mdp_ops(&mdp->ops, mdp->caps->features);
 292
 293         return mdp;
 294 }
 295
 296 void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp)
 297 {
 298         kfree(mdp);
 299 }
 300