drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   3  * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
   4  */
   5
   6 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
   7 #include <linux/slab.h>
   8 #include <linux/of_address.h>
   9 #include <linux/platform_device.h>
  10 #include "dpu_hw_mdss.h"
  11 #include "dpu_hw_interrupts.h"
  12 #include "dpu_hw_catalog.h"
  13 #include "dpu_kms.h"
  14
  15 #define VIG_BASE_MASK \
  16         (BIT(DPU_SSPP_QOS) |\
  17         BIT(DPU_SSPP_CDP) |\
  18         BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
  19
  20 #define VIG_MASK \
  21         (VIG_BASE_MASK | \
  22         BIT(DPU_SSPP_CSC_10BIT))
  23
  24 #define VIG_MSM8998_MASK \
  25         (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
  26
  27 #define VIG_SDM845_MASK \
  28         (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3))
  29
  30 #define VIG_SDM845_MASK_SDMA \
  31         (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
  32
  33 #define VIG_SC7180_MASK \
  34         (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
  35
  36 #define VIG_SC7180_MASK_SDMA \
  37         (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
  38
  39 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
  40
  41 #define DMA_MSM8998_MASK \
  42         (BIT(DPU_SSPP_QOS) |\
  43         BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
  44         BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
  45
  46 #define VIG_SC7280_MASK \
  47         (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
  48
  49 #define VIG_SC7280_MASK_SDMA \
  50         (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
  51
  52 #define DMA_SDM845_MASK \
  53         (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
  54         BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
  55         BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
  56
  57 #define DMA_CURSOR_SDM845_MASK \
  58         (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
  59
  60 #define DMA_SDM845_MASK_SDMA \
  61         (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
  62
  63 #define DMA_CURSOR_SDM845_MASK_SDMA \
  64         (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
  65
  66 #define DMA_CURSOR_MSM8998_MASK \
  67         (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
  68
  69 #define MIXER_MSM8998_MASK \
  70         (BIT(DPU_MIXER_SOURCESPLIT))
  71
  72 #define MIXER_SDM845_MASK \
  73         (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
  74
  75 #define MIXER_QCM2290_MASK \
  76         (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
  77
  78 #define PINGPONG_SDM845_MASK \
  79         (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_TE) | BIT(DPU_PINGPONG_DSC))
  80
  81 #define PINGPONG_SDM845_TE2_MASK \
  82         (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
  83
  84 #define PINGPONG_SM8150_MASK \
  85         (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
  86
  87 #define CTL_SC7280_MASK \
  88         (BIT(DPU_CTL_ACTIVE_CFG) | \
  89          BIT(DPU_CTL_FETCH_ACTIVE) | \
  90          BIT(DPU_CTL_VM_CFG) | \
  91          BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
  92
  93 #define CTL_SM8550_MASK \
  94         (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
  95
  96 #define MERGE_3D_SM8150_MASK (0)
  97
  98 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
  99
 100 #define INTF_SDM845_MASK (0)
 101
 102 #define INTF_SC7180_MASK \
 103         (BIT(DPU_INTF_INPUT_CTRL) | \
 104          BIT(DPU_INTF_TE) | \
 105          BIT(DPU_INTF_STATUS_SUPPORTED) | \
 106          BIT(DPU_DATA_HCTL_EN))
 107
 108 #define INTF_SC7280_MASK (INTF_SC7180_MASK | BIT(DPU_INTF_DATA_COMPRESS))
 109
 110 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
 111                          BIT(DPU_WB_UBWC) | \
 112                          BIT(DPU_WB_YUV_CONFIG) | \
 113                          BIT(DPU_WB_PIPE_ALPHA) | \
 114                          BIT(DPU_WB_XY_ROI_OFFSET) | \
 115                          BIT(DPU_WB_QOS) | \
 116                          BIT(DPU_WB_QOS_8LVL) | \
 117                          BIT(DPU_WB_CDP) | \
 118                          BIT(DPU_WB_INPUT_CTRL))
 119
 120 #define DEFAULT_PIXEL_RAM_SIZE          (50 * 1024)
 121 #define DEFAULT_DPU_LINE_WIDTH          2048
 122 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH   2560
 123
 124 #define MAX_HORZ_DECIMATION     4
 125 #define MAX_VERT_DECIMATION     4
 126
 127 #define MAX_UPSCALE_RATIO       20
 128 #define MAX_DOWNSCALE_RATIO     4
 129 #define SSPP_UNITY_SCALE        1
 130
 131 #define STRCAT(X, Y) (X Y)
 132
 133 static const uint32_t plane_formats[] = {
 134         DRM_FORMAT_ARGB8888,
 135         DRM_FORMAT_ABGR8888,
 136         DRM_FORMAT_RGBA8888,
 137         DRM_FORMAT_BGRA8888,
 138         DRM_FORMAT_XRGB8888,
 139         DRM_FORMAT_RGBX8888,
 140         DRM_FORMAT_BGRX8888,
 141         DRM_FORMAT_XBGR8888,
 142         DRM_FORMAT_ARGB2101010,
 143         DRM_FORMAT_XRGB2101010,
 144         DRM_FORMAT_RGB888,
 145         DRM_FORMAT_BGR888,
 146         DRM_FORMAT_RGB565,
 147         DRM_FORMAT_BGR565,
 148         DRM_FORMAT_ARGB1555,
 149         DRM_FORMAT_ABGR1555,
 150         DRM_FORMAT_RGBA5551,
 151         DRM_FORMAT_BGRA5551,
 152         DRM_FORMAT_XRGB1555,
 153         DRM_FORMAT_XBGR1555,
 154         DRM_FORMAT_RGBX5551,
 155         DRM_FORMAT_BGRX5551,
 156         DRM_FORMAT_ARGB4444,
 157         DRM_FORMAT_ABGR4444,
 158         DRM_FORMAT_RGBA4444,
 159         DRM_FORMAT_BGRA4444,
 160         DRM_FORMAT_XRGB4444,
 161         DRM_FORMAT_XBGR4444,
 162         DRM_FORMAT_RGBX4444,
 163         DRM_FORMAT_BGRX4444,
 164 };
 165
 166 static const uint32_t plane_formats_yuv[] = {
 167         DRM_FORMAT_ARGB8888,
 168         DRM_FORMAT_ABGR8888,
 169         DRM_FORMAT_RGBA8888,
 170         DRM_FORMAT_BGRX8888,
 171         DRM_FORMAT_BGRA8888,
 172         DRM_FORMAT_ARGB2101010,
 173         DRM_FORMAT_XRGB2101010,
 174         DRM_FORMAT_XRGB8888,
 175         DRM_FORMAT_XBGR8888,
 176         DRM_FORMAT_RGBX8888,
 177         DRM_FORMAT_RGB888,
 178         DRM_FORMAT_BGR888,
 179         DRM_FORMAT_RGB565,
 180         DRM_FORMAT_BGR565,
 181         DRM_FORMAT_ARGB1555,
 182         DRM_FORMAT_ABGR1555,
 183         DRM_FORMAT_RGBA5551,
 184         DRM_FORMAT_BGRA5551,
 185         DRM_FORMAT_XRGB1555,
 186         DRM_FORMAT_XBGR1555,
 187         DRM_FORMAT_RGBX5551,
 188         DRM_FORMAT_BGRX5551,
 189         DRM_FORMAT_ARGB4444,
 190         DRM_FORMAT_ABGR4444,
 191         DRM_FORMAT_RGBA4444,
 192         DRM_FORMAT_BGRA4444,
 193         DRM_FORMAT_XRGB4444,
 194         DRM_FORMAT_XBGR4444,
 195         DRM_FORMAT_RGBX4444,
 196         DRM_FORMAT_BGRX4444,
 197
 198         DRM_FORMAT_P010,
 199         DRM_FORMAT_NV12,
 200         DRM_FORMAT_NV21,
 201         DRM_FORMAT_NV16,
 202         DRM_FORMAT_NV61,
 203         DRM_FORMAT_VYUY,
 204         DRM_FORMAT_UYVY,
 205         DRM_FORMAT_YUYV,
 206         DRM_FORMAT_YVYU,
 207         DRM_FORMAT_YUV420,
 208         DRM_FORMAT_YVU420,
 209 };
 210
 211 static const u32 rotation_v2_formats[] = {
 212         DRM_FORMAT_NV12,
 213         /* TODO add formats after validation */
 214 };
 215
 216 static const uint32_t wb2_formats[] = {
 217         DRM_FORMAT_RGB565,
 218         DRM_FORMAT_BGR565,
 219         DRM_FORMAT_RGB888,
 220         DRM_FORMAT_ARGB8888,
 221         DRM_FORMAT_RGBA8888,
 222         DRM_FORMAT_ABGR8888,
 223         DRM_FORMAT_XRGB8888,
 224         DRM_FORMAT_RGBX8888,
 225         DRM_FORMAT_XBGR8888,
 226         DRM_FORMAT_ARGB1555,
 227         DRM_FORMAT_RGBA5551,
 228         DRM_FORMAT_XRGB1555,
 229         DRM_FORMAT_RGBX5551,
 230         DRM_FORMAT_ARGB4444,
 231         DRM_FORMAT_RGBA4444,
 232         DRM_FORMAT_RGBX4444,
 233         DRM_FORMAT_XRGB4444,
 234         DRM_FORMAT_BGR565,
 235         DRM_FORMAT_BGR888,
 236         DRM_FORMAT_ABGR8888,
 237         DRM_FORMAT_BGRA8888,
 238         DRM_FORMAT_BGRX8888,
 239         DRM_FORMAT_XBGR8888,
 240         DRM_FORMAT_ABGR1555,
 241         DRM_FORMAT_BGRA5551,
 242         DRM_FORMAT_XBGR1555,
 243         DRM_FORMAT_BGRX5551,
 244         DRM_FORMAT_ABGR4444,
 245         DRM_FORMAT_BGRA4444,
 246         DRM_FORMAT_BGRX4444,
 247         DRM_FORMAT_XBGR4444,
 248 };
 249
 250 /*************************************************************
 251  * SSPP sub blocks config
 252  *************************************************************/
 253
 254 /* SSPP common configuration */
 255 #define _VIG_SBLK(num, sdma_pri, qseed_ver) \
 256         { \
 257         .maxdwnscale = MAX_DOWNSCALE_RATIO, \
 258         .maxupscale = MAX_UPSCALE_RATIO, \
 259         .smart_dma_priority = sdma_pri, \
 260         .scaler_blk = {.name = STRCAT("sspp_scaler", num), \
 261                 .id = qseed_ver, \
 262                 .base = 0xa00, .len = 0xa0,}, \
 263         .csc_blk = {.name = STRCAT("sspp_csc", num), \
 264                 .id = DPU_SSPP_CSC_10BIT, \
 265                 .base = 0x1a00, .len = 0x100,}, \
 266         .format_list = plane_formats_yuv, \
 267         .num_formats = ARRAY_SIZE(plane_formats_yuv), \
 268         .virt_format_list = plane_formats, \
 269         .virt_num_formats = ARRAY_SIZE(plane_formats), \
 270         .rotation_cfg = NULL, \
 271         }
 272
 273 #define _VIG_SBLK_ROT(num, sdma_pri, qseed_ver, rot_cfg) \
 274         { \
 275         .maxdwnscale = MAX_DOWNSCALE_RATIO, \
 276         .maxupscale = MAX_UPSCALE_RATIO, \
 277         .smart_dma_priority = sdma_pri, \
 278         .scaler_blk = {.name = STRCAT("sspp_scaler", num), \
 279                 .id = qseed_ver, \
 280                 .base = 0xa00, .len = 0xa0,}, \
 281         .csc_blk = {.name = STRCAT("sspp_csc", num), \
 282                 .id = DPU_SSPP_CSC_10BIT, \
 283                 .base = 0x1a00, .len = 0x100,}, \
 284         .format_list = plane_formats_yuv, \
 285         .num_formats = ARRAY_SIZE(plane_formats_yuv), \
 286         .virt_format_list = plane_formats, \
 287         .virt_num_formats = ARRAY_SIZE(plane_formats), \
 288         .rotation_cfg = rot_cfg, \
 289         }
 290
 291 #define _DMA_SBLK(num, sdma_pri) \
 292         { \
 293         .maxdwnscale = SSPP_UNITY_SCALE, \
 294         .maxupscale = SSPP_UNITY_SCALE, \
 295         .smart_dma_priority = sdma_pri, \
 296         .format_list = plane_formats, \
 297         .num_formats = ARRAY_SIZE(plane_formats), \
 298         .virt_format_list = plane_formats, \
 299         .virt_num_formats = ARRAY_SIZE(plane_formats), \
 300         }
 301
 302 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 =
 303                                 _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3);
 304 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 =
 305                                 _VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3);
 306 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 =
 307                                 _VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3);
 308 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 =
 309                                 _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3);
 310
 311 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
 312         .rot_maxheight = 1088,
 313         .rot_num_formats = ARRAY_SIZE(rotation_v2_formats),
 314         .rot_format_list = rotation_v2_formats,
 315 };
 316
 317 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
 318                                 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
 319 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
 320                                 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
 321 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
 322                                 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
 323 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
 324                                 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
 325
 326 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
 327 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
 328 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
 329 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
 330
 331 #define SSPP_BLK(_name, _id, _base, _len, _features, \
 332                 _sblk, _xinid, _type, _clkctrl) \
 333         { \
 334         .name = _name, .id = _id, \
 335         .base = _base, .len = _len, \
 336         .features = _features, \
 337         .sblk = &_sblk, \
 338         .xin_id = _xinid, \
 339         .type = _type, \
 340         .clk_ctrl = _clkctrl \
 341         }
 342
 343 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
 344                                 _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
 345
 346 static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
 347                         _VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2);
 348
 349 static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
 350                                 _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4);
 351
 352 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
 353                                 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);
 354 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
 355                                 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED4);
 356 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
 357                                 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED4);
 358 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
 359                                 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4);
 360
 361 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =
 362                                 _VIG_SBLK("0", 7, DPU_SSPP_SCALER_QSEED4);
 363 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 =
 364                                 _VIG_SBLK("1", 8, DPU_SSPP_SCALER_QSEED4);
 365 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 =
 366                                 _VIG_SBLK("2", 9, DPU_SSPP_SCALER_QSEED4);
 367 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 =
 368                                 _VIG_SBLK("3", 10, DPU_SSPP_SCALER_QSEED4);
 369 static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5);
 370 static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6);
 371
 372 #define _VIG_SBLK_NOSCALE(num, sdma_pri) \
 373         { \
 374         .maxdwnscale = SSPP_UNITY_SCALE, \
 375         .maxupscale = SSPP_UNITY_SCALE, \
 376         .smart_dma_priority = sdma_pri, \
 377         .format_list = plane_formats_yuv, \
 378         .num_formats = ARRAY_SIZE(plane_formats_yuv), \
 379         .virt_format_list = plane_formats, \
 380         .virt_num_formats = ARRAY_SIZE(plane_formats), \
 381         }
 382
 383 static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2);
 384 static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
 385
 386 /*************************************************************
 387  * MIXER sub blocks config
 388  *************************************************************/
 389
 390 #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \
 391         { \
 392         .name = _name, .id = _id, \
 393         .base = _base, .len = 0x320, \
 394         .features = _fmask, \
 395         .sblk = _sblk, \
 396         .pingpong = _pp, \
 397         .lm_pair_mask = (1 << _lmpair), \
 398         .dspp = _dspp \
 399         }
 400
 401 /* MSM8998 */
 402
 403 static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
 404         .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 405         .maxblendstages = 7, /* excluding base layer */
 406         .blendstage_base = { /* offsets relative to mixer base */
 407                 0x20, 0x50, 0x80, 0xb0, 0x230,
 408                 0x260, 0x290
 409         },
 410 };
 411
 412 /* SDM845 */
 413
 414 static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
 415         .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 416         .maxblendstages = 11, /* excluding base layer */
 417         .blendstage_base = { /* offsets relative to mixer base */
 418                 0x20, 0x38, 0x50, 0x68, 0x80, 0x98,
 419                 0xb0, 0xc8, 0xe0, 0xf8, 0x110
 420         },
 421 };
 422
 423 /* SC7180 */
 424
 425 static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
 426         .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 427         .maxblendstages = 7, /* excluding base layer */
 428         .blendstage_base = { /* offsets relative to mixer base */
 429                 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0
 430         },
 431 };
 432
 433 /* QCM2290 */
 434
 435 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
 436         .maxwidth = DEFAULT_DPU_LINE_WIDTH,
 437         .maxblendstages = 4, /* excluding base layer */
 438         .blendstage_base = { /* offsets relative to mixer base */
 439                 0x20, 0x38, 0x50, 0x68
 440         },
 441 };
 442
 443 /*************************************************************
 444  * DSPP sub blocks config
 445  *************************************************************/
 446 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = {
 447         .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
 448                 .len = 0x90, .version = 0x10007},
 449 };
 450
 451 static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = {
 452         .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
 453                 .len = 0x90, .version = 0x40000},
 454 };
 455
 456 #define DSPP_BLK(_name, _id, _base, _mask, _sblk) \
 457                 {\
 458                 .name = _name, .id = _id, \
 459                 .base = _base, .len = 0x1800, \
 460                 .features = _mask, \
 461                 .sblk = _sblk \
 462                 }
 463
 464 /*************************************************************
 465  * PINGPONG sub blocks config
 466  *************************************************************/
 467 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = {
 468         .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0,
 469                 .version = 0x1},
 470         .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
 471                 .len = 0x20, .version = 0x10000},
 472 };
 473
 474 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = {
 475         .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
 476                 .len = 0x20, .version = 0x10000},
 477 };
 478
 479 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
 480         .dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0,
 481         .len = 0x20, .version = 0x20000},
 482 };
 483
 484 #define PP_BLK_DITHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
 485         {\
 486         .name = _name, .id = _id, \
 487         .base = _base, .len = 0, \
 488         .features = BIT(DPU_PINGPONG_DITHER), \
 489         .merge_3d = _merge_3d, \
 490         .sblk = &_sblk, \
 491         .intr_done = _done, \
 492         .intr_rdptr = _rdptr, \
 493         }
 494 #define PP_BLK(_name, _id, _base, _features, _merge_3d, _sblk, _done, _rdptr) \
 495         {\
 496         .name = _name, .id = _id, \
 497         .base = _base, .len = 0xd4, \
 498         .features = _features, \
 499         .merge_3d = _merge_3d, \
 500         .sblk = &_sblk, \
 501         .intr_done = _done, \
 502         .intr_rdptr = _rdptr, \
 503         }
 504
 505 /*************************************************************
 506  * MERGE_3D sub blocks config
 507  *************************************************************/
 508 #define MERGE_3D_BLK(_name, _id, _base) \
 509         {\
 510         .name = _name, .id = _id, \
 511         .base = _base, .len = 0x8, \
 512         .features = MERGE_3D_SM8150_MASK, \
 513         .sblk = NULL \
 514         }
 515
 516 /*************************************************************
 517  * DSC sub blocks config
 518  *************************************************************/
 519 static const struct dpu_dsc_sub_blks dsc_sblk_0 = {
 520         .enc = {.base = 0x100, .len = 0x100},
 521         .ctl = {.base = 0xF00, .len = 0x10},
 522 };
 523
 524 static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
 525         .enc = {.base = 0x200, .len = 0x100},
 526         .ctl = {.base = 0xF80, .len = 0x10},
 527 };
 528
 529 #define DSC_BLK(_name, _id, _base, _features) \
 530         {\
 531         .name = _name, .id = _id, \
 532         .base = _base, .len = 0x140, \
 533         .features = _features, \
 534         }
 535
 536 #define DSC_BLK_1_2(_name, _id, _base, _len, _features, _sblk) \
 537         {\
 538         .name = _name, .id = _id, \
 539         .base = _base, .len = _len, \
 540         .features = BIT(DPU_DSC_HW_REV_1_2) | _features, \
 541         .sblk = &_sblk, \
 542         }
 543
 544 /*************************************************************
 545  * INTF sub blocks config
 546  *************************************************************/
 547 #define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _underrun, _vsync) \
 548         {\
 549         .name = _name, .id = _id, \
 550         .base = _base, .len = _len, \
 551         .features = _features, \
 552         .type = _type, \
 553         .controller_id = _ctrl_id, \
 554         .prog_fetch_lines_worst_case = _progfetch, \
 555         .intr_underrun = _underrun, \
 556         .intr_vsync = _vsync, \
 557         .intr_tear_rd_ptr = -1, \
 558         }
 559
 560 /* DSI Interface sub-block with TEAR registers (since DPU 5.0.0) */
 561 #define INTF_BLK_DSI_TE(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _underrun, _vsync, _tear_rd_ptr) \
 562         {\
 563         .name = _name, .id = _id, \
 564         .base = _base, .len = _len, \
 565         .features = _features, \
 566         .type = _type, \
 567         .controller_id = _ctrl_id, \
 568         .prog_fetch_lines_worst_case = _progfetch, \
 569         .intr_underrun = _underrun, \
 570         .intr_vsync = _vsync, \
 571         .intr_tear_rd_ptr = _tear_rd_ptr, \
 572         }
 573
 574 /*************************************************************
 575  * Writeback blocks config
 576  *************************************************************/
 577 #define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \
 578                 __xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \
 579         { \
 580         .name = _name, .id = _id, \
 581         .base = _base, .len = 0x2c8, \
 582         .features = _features, \
 583         .format_list = wb2_formats, \
 584         .num_formats = ARRAY_SIZE(wb2_formats), \
 585         .clk_ctrl = _clk_ctrl, \
 586         .xin_id = __xin_id, \
 587         .vbif_idx = vbif_id, \
 588         .maxlinewidth = _max_linewidth, \
 589         .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
 590         }
 591
 592 /*************************************************************
 593  * VBIF sub blocks config
 594  *************************************************************/
 595 /* VBIF QOS remap */
 596 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2};
 597 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1};
 598 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};
 599 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};
 600
 601 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = {
 602         {
 603                 .pps = 1920 * 1080 * 30,
 604                 .ot_limit = 2,
 605         },
 606         {
 607                 .pps = 1920 * 1080 * 60,
 608                 .ot_limit = 4,
 609         },
 610         {
 611                 .pps = 3840 * 2160 * 30,
 612                 .ot_limit = 16,
 613         },
 614 };
 615
 616 static const struct dpu_vbif_cfg msm8998_vbif[] = {
 617         {
 618         .name = "vbif_rt", .id = VBIF_RT,
 619         .base = 0, .len = 0x1040,
 620         .default_ot_rd_limit = 32,
 621         .default_ot_wr_limit = 32,
 622         .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM),
 623         .xin_halt_timeout = 0x4000,
 624         .qos_rp_remap_size = 0x20,
 625         .dynamic_ot_rd_tbl = {
 626                 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
 627                 .cfg = msm8998_ot_rdwr_cfg,
 628                 },
 629         .dynamic_ot_wr_tbl = {
 630                 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
 631                 .cfg = msm8998_ot_rdwr_cfg,
 632                 },
 633         .qos_rt_tbl = {
 634                 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl),
 635                 .priority_lvl = msm8998_rt_pri_lvl,
 636                 },
 637         .qos_nrt_tbl = {
 638                 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl),
 639                 .priority_lvl = msm8998_nrt_pri_lvl,
 640                 },
 641         .memtype_count = 14,
 642         .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
 643         },
 644 };
 645
 646 static const struct dpu_vbif_cfg sdm845_vbif[] = {
 647         {
 648         .name = "vbif_rt", .id = VBIF_RT,
 649         .base = 0, .len = 0x1040,
 650         .features = BIT(DPU_VBIF_QOS_REMAP),
 651         .xin_halt_timeout = 0x4000,
 652         .qos_rp_remap_size = 0x40,
 653         .qos_rt_tbl = {
 654                 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
 655                 .priority_lvl = sdm845_rt_pri_lvl,
 656                 },
 657         .qos_nrt_tbl = {
 658                 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
 659                 .priority_lvl = sdm845_nrt_pri_lvl,
 660                 },
 661         .memtype_count = 14,
 662         .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
 663         },
 664 };
 665
 666 /*************************************************************
 667  * PERF data config
 668  *************************************************************/
 669
 670 /* SSPP QOS LUTs */
 671 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = {
 672         {.fl = 4,  .lut = 0x1b},
 673         {.fl = 5,  .lut = 0x5b},
 674         {.fl = 6,  .lut = 0x15b},
 675         {.fl = 7,  .lut = 0x55b},
 676         {.fl = 8,  .lut = 0x155b},
 677         {.fl = 9,  .lut = 0x555b},
 678         {.fl = 10, .lut = 0x1555b},
 679         {.fl = 11, .lut = 0x5555b},
 680         {.fl = 12, .lut = 0x15555b},
 681         {.fl = 0,  .lut = 0x55555b}
 682 };
 683
 684 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = {
 685         {.fl = 4, .lut = 0x357},
 686         {.fl = 5, .lut = 0x3357},
 687         {.fl = 6, .lut = 0x23357},
 688         {.fl = 7, .lut = 0x223357},
 689         {.fl = 8, .lut = 0x2223357},
 690         {.fl = 9, .lut = 0x22223357},
 691         {.fl = 10, .lut = 0x222223357},
 692         {.fl = 11, .lut = 0x2222223357},
 693         {.fl = 12, .lut = 0x22222223357},
 694         {.fl = 13, .lut = 0x222222223357},
 695         {.fl = 14, .lut = 0x1222222223357},
 696         {.fl = 0, .lut = 0x11222222223357}
 697 };
 698
 699 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = {
 700         {.fl = 10, .lut = 0x1aaff},
 701         {.fl = 11, .lut = 0x5aaff},
 702         {.fl = 12, .lut = 0x15aaff},
 703         {.fl = 0,  .lut = 0x55aaff},
 704 };
 705
 706 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
 707         {.fl = 0, .lut = 0x0011222222335777},
 708 };
 709
 710 static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
 711         {.fl = 0, .lut = 0x0011223445566777 },
 712 };
 713
 714 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
 715         {.fl = 0, .lut = 0x0011222222223357 },
 716 };
 717
 718 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = {
 719         {.fl = 4, .lut = 0x0000000000000357 },
 720 };
 721
 722 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = {
 723         {.fl = 0, .lut = 0x0011222222335777},
 724 };
 725
 726 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
 727         {.fl = 10, .lut = 0x344556677},
 728         {.fl = 11, .lut = 0x3344556677},
 729         {.fl = 12, .lut = 0x23344556677},
 730         {.fl = 13, .lut = 0x223344556677},
 731         {.fl = 14, .lut = 0x1223344556677},
 732         {.fl = 0, .lut = 0x112233344556677},
 733 };
 734
 735 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
 736         {.fl = 0, .lut = 0x0011223344556677},
 737 };
 738
 739 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = {
 740         {.fl = 10, .lut = 0x0000000344556677},
 741 };
 742
 743 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = {
 744         {.fl = 0, .lut = 0x0},
 745 };
 746
 747 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = {
 748         {.fl = 0, .lut = 0x0},
 749 };
 750
 751 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
 752         {.fl = 0, .lut = 0x0},
 753 };
 754
 755 /*************************************************************
 756  * Hardware catalog
 757  *************************************************************/
 758
 759 #include "catalog/dpu_3_0_msm8998.h"
 760
 761 #include "catalog/dpu_4_0_sdm845.h"
 762
 763 #include "catalog/dpu_5_0_sm8150.h"
 764 #include "catalog/dpu_5_1_sc8180x.h"
 765
 766 #include "catalog/dpu_6_0_sm8250.h"
 767 #include "catalog/dpu_6_2_sc7180.h"
 768 #include "catalog/dpu_6_3_sm6115.h"
 769 #include "catalog/dpu_6_4_sm6350.h"
 770 #include "catalog/dpu_6_5_qcm2290.h"
 771 #include "catalog/dpu_6_9_sm6375.h"
 772
 773 #include "catalog/dpu_7_0_sm8350.h"
 774 #include "catalog/dpu_7_2_sc7280.h"
 775
 776 #include "catalog/dpu_8_0_sc8280xp.h"
 777 #include "catalog/dpu_8_1_sm8450.h"
 778
 779 #include "catalog/dpu_9_0_sm8550.h"