drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
   4  */
   5
   6 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
   7
   8 #include <linux/debugfs.h>
   9
  10 #include <drm/drm_framebuffer.h>
  11
  12 #include "dpu_encoder_phys.h"
  13 #include "dpu_formats.h"
  14 #include "dpu_hw_top.h"
  15 #include "dpu_hw_wb.h"
  16 #include "dpu_hw_lm.h"
  17 #include "dpu_hw_merge3d.h"
  18 #include "dpu_hw_interrupts.h"
  19 #include "dpu_core_irq.h"
  20 #include "dpu_vbif.h"
  21 #include "dpu_crtc.h"
  22 #include "disp/msm_disp_snapshot.h"
  23
  24 #define to_dpu_encoder_phys_wb(x) \
  25         container_of(x, struct dpu_encoder_phys_wb, base)
  26
  27 /**
  28  * dpu_encoder_phys_wb_is_master - report wb always as master encoder
  29  */
  30 static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)
  31 {
  32         /* there is only one physical enc for dpu_writeback */
  33         return true;
  34 }
  35
  36 /**
  37  * dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
  38  * @phys_enc:   Pointer to physical encoder
  39  */
  40 static void dpu_encoder_phys_wb_set_ot_limit(
  41                 struct dpu_encoder_phys *phys_enc)
  42 {
  43         struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
  44         struct dpu_vbif_set_ot_params ot_params;
  45
  46         memset(&ot_params, 0, sizeof(ot_params));
  47         ot_params.xin_id = hw_wb->caps->xin_id;
  48         ot_params.num = hw_wb->idx - WB_0;
  49         ot_params.width = phys_enc->cached_mode.hdisplay;
  50         ot_params.height = phys_enc->cached_mode.vdisplay;
  51         ot_params.is_wfd = true;
  52         ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
  53         ot_params.vbif_idx = hw_wb->caps->vbif_idx;
  54         ot_params.clk_ctrl = hw_wb->caps->clk_ctrl;
  55         ot_params.rd = false;
  56
  57         dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params);
  58 }
  59
  60 /**
  61  * dpu_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
  62  * @phys_enc:   Pointer to physical encoder
  63  */
  64 static void dpu_encoder_phys_wb_set_qos_remap(
  65                 struct dpu_encoder_phys *phys_enc)
  66 {
  67         struct dpu_hw_wb *hw_wb;
  68         struct dpu_vbif_set_qos_params qos_params;
  69
  70         if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
  71                 DPU_ERROR("invalid arguments\n");
  72                 return;
  73         }
  74
  75         if (!phys_enc->hw_wb || !phys_enc->hw_wb->caps) {
  76                 DPU_ERROR("invalid writeback hardware\n");
  77                 return;
  78         }
  79
  80         hw_wb = phys_enc->hw_wb;
  81
  82         memset(&qos_params, 0, sizeof(qos_params));
  83         qos_params.vbif_idx = hw_wb->caps->vbif_idx;
  84         qos_params.xin_id = hw_wb->caps->xin_id;
  85         qos_params.clk_ctrl = hw_wb->caps->clk_ctrl;
  86         qos_params.num = hw_wb->idx - WB_0;
  87         qos_params.is_rt = false;
  88
  89         DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n",
  90                         qos_params.num,
  91                         qos_params.vbif_idx,
  92                         qos_params.xin_id, qos_params.is_rt);
  93
  94         dpu_vbif_set_qos_remap(phys_enc->dpu_kms, &qos_params);
  95 }
  96
  97 /**
  98  * dpu_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback
  99  * @phys_enc:   Pointer to physical encoder
 100  */
 101 static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc)
 102 {
 103         struct dpu_hw_wb *hw_wb;
 104         struct dpu_hw_wb_qos_cfg qos_cfg;
 105         const struct dpu_mdss_cfg *catalog;
 106         const struct dpu_qos_lut_tbl *qos_lut_tb;
 107
 108         if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
 109                 DPU_ERROR("invalid parameter(s)\n");
 110                 return;
 111         }
 112
 113         catalog = phys_enc->dpu_kms->catalog;
 114
 115         hw_wb = phys_enc->hw_wb;
 116
 117         memset(&qos_cfg, 0, sizeof(struct dpu_hw_wb_qos_cfg));
 118         qos_cfg.danger_safe_en = true;
 119         qos_cfg.danger_lut =
 120                 catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
 121
 122         qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
 123
 124         qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
 125         qos_cfg.creq_lut = _dpu_hw_get_qos_lut(qos_lut_tb, 0);
 126
 127         if (hw_wb->ops.setup_qos_lut)
 128                 hw_wb->ops.setup_qos_lut(hw_wb, &qos_cfg);
 129 }
 130
 131 /**
 132  * dpu_encoder_phys_wb_setup_fb - setup output framebuffer
 133  * @phys_enc:   Pointer to physical encoder
 134  * @fb:         Pointer to output framebuffer
 135  * @wb_roi:     Pointer to output region of interest
 136  */
 137 static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
 138                 struct drm_framebuffer *fb)
 139 {
 140         struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
 141         struct dpu_hw_wb *hw_wb;
 142         struct dpu_hw_wb_cfg *wb_cfg;
 143         struct dpu_hw_cdp_cfg cdp_cfg;
 144
 145         if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
 146                 DPU_ERROR("invalid encoder\n");
 147                 return;
 148         }
 149
 150         hw_wb = phys_enc->hw_wb;
 151         wb_cfg = &wb_enc->wb_cfg;
 152
 153         wb_cfg->intf_mode = phys_enc->intf_mode;
 154         wb_cfg->roi.x1 = 0;
 155         wb_cfg->roi.x2 = phys_enc->cached_mode.hdisplay;
 156         wb_cfg->roi.y1 = 0;
 157         wb_cfg->roi.y2 = phys_enc->cached_mode.vdisplay;
 158
 159         if (hw_wb->ops.setup_roi)
 160                 hw_wb->ops.setup_roi(hw_wb, wb_cfg);
 161
 162         if (hw_wb->ops.setup_outformat)
 163                 hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
 164
 165         if (hw_wb->ops.setup_cdp) {
 166                 memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
 167
 168                 cdp_cfg.enable = phys_enc->dpu_kms->catalog->perf->cdp_cfg
 169                                 [DPU_PERF_CDP_USAGE_NRT].wr_enable;
 170                 cdp_cfg.ubwc_meta_enable =
 171                                 DPU_FORMAT_IS_UBWC(wb_cfg->dest.format);
 172                 cdp_cfg.tile_amortize_enable =
 173                                 DPU_FORMAT_IS_UBWC(wb_cfg->dest.format) ||
 174                                 DPU_FORMAT_IS_TILE(wb_cfg->dest.format);
 175                 cdp_cfg.preload_ahead = DPU_WB_CDP_PRELOAD_AHEAD_64;
 176
 177                 hw_wb->ops.setup_cdp(hw_wb, &cdp_cfg);
 178         }
 179
 180         if (hw_wb->ops.setup_outaddress)
 181                 hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
 182 }
 183
 184 /**
 185  * dpu_encoder_phys_wb_setup_cdp - setup chroma down prefetch block
 186  * @phys_enc:Pointer to physical encoder
 187  */
 188 static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc)
 189 {
 190         struct dpu_hw_wb *hw_wb;
 191         struct dpu_hw_ctl *ctl;
 192
 193         if (!phys_enc) {
 194                 DPU_ERROR("invalid encoder\n");
 195                 return;
 196         }
 197
 198         hw_wb = phys_enc->hw_wb;
 199         ctl = phys_enc->hw_ctl;
 200
 201         if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) &&
 202                 (phys_enc->hw_ctl &&
 203                  phys_enc->hw_ctl->ops.setup_intf_cfg)) {
 204                 struct dpu_hw_intf_cfg intf_cfg = {0};
 205                 struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp;
 206                 enum dpu_3d_blend_mode mode_3d;
 207
 208                 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
 209
 210                 intf_cfg.intf = DPU_NONE;
 211                 intf_cfg.wb = hw_wb->idx;
 212
 213                 if (mode_3d && hw_pp && hw_pp->merge_3d)
 214                         intf_cfg.merge_3d = hw_pp->merge_3d->idx;
 215
 216                 if (phys_enc->hw_pp->merge_3d && phys_enc->hw_pp->merge_3d->ops.setup_3d_mode)
 217                         phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
 218                                         mode_3d);
 219
 220                 /* setup which pp blk will connect to this wb */
 221                 if (hw_pp && phys_enc->hw_wb->ops.bind_pingpong_blk)
 222                         phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, true,
 223                                         phys_enc->hw_pp->idx);
 224
 225                 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
 226         } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {
 227                 struct dpu_hw_intf_cfg intf_cfg = {0};
 228
 229                 intf_cfg.intf = DPU_NONE;
 230                 intf_cfg.wb = hw_wb->idx;
 231                 intf_cfg.mode_3d =
 232                         dpu_encoder_helper_get_3d_blend_mode(phys_enc);
 233                 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
 234         }
 235 }
 236
 237 /**
 238  * dpu_encoder_phys_wb_atomic_check - verify and fixup given atomic states
 239  * @phys_enc:   Pointer to physical encoder
 240  * @crtc_state: Pointer to CRTC atomic state
 241  * @conn_state: Pointer to connector atomic state
 242  */
 243 static int dpu_encoder_phys_wb_atomic_check(
 244                 struct dpu_encoder_phys *phys_enc,
 245                 struct drm_crtc_state *crtc_state,
 246                 struct drm_connector_state *conn_state)
 247 {
 248         struct drm_framebuffer *fb;
 249         const struct drm_display_mode *mode = &crtc_state->mode;
 250
 251         DPU_DEBUG("[atomic_check:%d, \"%s\",%d,%d]\n",
 252                         phys_enc->wb_idx, mode->name, mode->hdisplay, mode->vdisplay);
 253
 254         if (!conn_state || !conn_state->connector) {
 255                 DPU_ERROR("invalid connector state\n");
 256                 return -EINVAL;
 257         } else if (conn_state->connector->status !=
 258                         connector_status_connected) {
 259                 DPU_ERROR("connector not connected %d\n",
 260                                 conn_state->connector->status);
 261                 return -EINVAL;
 262         }
 263
 264         if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
 265                 return 0;
 266
 267         fb = conn_state->writeback_job->fb;
 268
 269         DPU_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
 270                         fb->width, fb->height);
 271
 272         if (fb->width != mode->hdisplay) {
 273                 DPU_ERROR("invalid fb w=%d, mode w=%d\n", fb->width,
 274                                 mode->hdisplay);
 275                 return -EINVAL;
 276         } else if (fb->height != mode->vdisplay) {
 277                 DPU_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
 278                                   mode->vdisplay);
 279                 return -EINVAL;
 280         } else if (fb->width > phys_enc->hw_wb->caps->maxlinewidth) {
 281                 DPU_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
 282                                   fb->width, phys_enc->hw_wb->caps->maxlinewidth);
 283                 return -EINVAL;
 284         }
 285
 286         return 0;
 287 }
 288
 289
 290 /**
 291  * _dpu_encoder_phys_wb_update_flush - flush hardware update
 292  * @phys_enc:   Pointer to physical encoder
 293  */
 294 static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)
 295 {
 296         struct dpu_hw_wb *hw_wb;
 297         struct dpu_hw_ctl *hw_ctl;
 298         struct dpu_hw_pingpong *hw_pp;
 299         u32 pending_flush = 0;
 300
 301         if (!phys_enc)
 302                 return;
 303
 304         hw_wb = phys_enc->hw_wb;
 305         hw_pp = phys_enc->hw_pp;
 306         hw_ctl = phys_enc->hw_ctl;
 307
 308         DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
 309
 310         if (!hw_ctl) {
 311                 DPU_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
 312                 return;
 313         }
 314
 315         if (hw_ctl->ops.update_pending_flush_wb)
 316                 hw_ctl->ops.update_pending_flush_wb(hw_ctl, hw_wb->idx);
 317
 318         if (hw_ctl->ops.update_pending_flush_merge_3d && hw_pp && hw_pp->merge_3d)
 319                 hw_ctl->ops.update_pending_flush_merge_3d(hw_ctl,
 320                                 hw_pp->merge_3d->idx);
 321
 322         if (hw_ctl->ops.get_pending_flush)
 323                 pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl);
 324
 325         DPU_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",
 326                         hw_ctl->idx - CTL_0, pending_flush,
 327                         hw_wb->idx - WB_0);
 328 }
 329
 330 /**
 331  * dpu_encoder_phys_wb_setup - setup writeback encoder
 332  * @phys_enc:   Pointer to physical encoder
 333  */
 334 static void dpu_encoder_phys_wb_setup(
 335                 struct dpu_encoder_phys *phys_enc)
 336 {
 337         struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
 338         struct drm_display_mode mode = phys_enc->cached_mode;
 339         struct drm_framebuffer *fb = NULL;
 340
 341         DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
 342                         hw_wb->idx - WB_0, mode.name,
 343                         mode.hdisplay, mode.vdisplay);
 344
 345         dpu_encoder_phys_wb_set_ot_limit(phys_enc);
 346
 347         dpu_encoder_phys_wb_set_qos_remap(phys_enc);
 348
 349         dpu_encoder_phys_wb_set_qos(phys_enc);
 350
 351         dpu_encoder_phys_wb_setup_fb(phys_enc, fb);
 352
 353         dpu_encoder_phys_wb_setup_cdp(phys_enc);
 354
 355 }
 356
 357 static void _dpu_encoder_phys_wb_frame_done_helper(void *arg)
 358 {
 359         struct dpu_encoder_phys *phys_enc = arg;
 360         struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
 361
 362         struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
 363         unsigned long lock_flags;
 364         u32 event = DPU_ENCODER_FRAME_EVENT_DONE;
 365
 366         DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
 367
 368         if (phys_enc->parent_ops->handle_frame_done)
 369                 phys_enc->parent_ops->handle_frame_done(phys_enc->parent,
 370                                 phys_enc, event);
 371
 372         if (phys_enc->parent_ops->handle_vblank_virt)
 373                 phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent,
 374                                 phys_enc);
 375
 376         spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
 377         atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
 378         spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 379
 380         if (wb_enc->wb_conn)
 381                 drm_writeback_signal_completion(wb_enc->wb_conn, 0);
 382
 383         /* Signal any waiting atomic commit thread */
 384         wake_up_all(&phys_enc->pending_kickoff_wq);
 385 }
 386
 387 /**
 388  * dpu_encoder_phys_wb_done_irq - writeback interrupt handler
 389  * @arg:        Pointer to writeback encoder
 390  * @irq_idx:    interrupt index
 391  */
 392 static void dpu_encoder_phys_wb_done_irq(void *arg, int irq_idx)
 393 {
 394         _dpu_encoder_phys_wb_frame_done_helper(arg);
 395 }
 396
 397 /**
 398  * dpu_encoder_phys_wb_irq_ctrl - irq control of WB
 399  * @phys:       Pointer to physical encoder
 400  * @enable:     indicates enable or disable interrupts
 401  */
 402 static void dpu_encoder_phys_wb_irq_ctrl(
 403                 struct dpu_encoder_phys *phys, bool enable)
 404 {
 405
 406         struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);
 407
 408         if (enable && atomic_inc_return(&wb_enc->wbirq_refcount) == 1)
 409                 dpu_core_irq_register_callback(phys->dpu_kms,
 410                                 phys->irq[INTR_IDX_WB_DONE], dpu_encoder_phys_wb_done_irq, phys);
 411         else if (!enable &&
 412                         atomic_dec_return(&wb_enc->wbirq_refcount) == 0)
 413                 dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);
 414 }
 415
 416 static void dpu_encoder_phys_wb_atomic_mode_set(
 417                 struct dpu_encoder_phys *phys_enc,
 418                 struct drm_crtc_state *crtc_state,
 419                 struct drm_connector_state *conn_state)
 420 {
 421
 422         phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
 423 }
 424
 425 static void _dpu_encoder_phys_wb_handle_wbdone_timeout(
 426                 struct dpu_encoder_phys *phys_enc)
 427 {
 428         struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
 429         u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
 430
 431         wb_enc->wb_done_timeout_cnt++;
 432
 433         if (wb_enc->wb_done_timeout_cnt == 1)
 434                 msm_disp_snapshot_state(phys_enc->parent->dev);
 435
 436         atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
 437
 438         /* request a ctl reset before the next kickoff */
 439         phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET;
 440
 441         if (wb_enc->wb_conn)
 442                 drm_writeback_signal_completion(wb_enc->wb_conn, 0);
 443
 444         if (phys_enc->parent_ops->handle_frame_done)
 445                 phys_enc->parent_ops->handle_frame_done(
 446                                 phys_enc->parent, phys_enc, frame_event);
 447 }
 448
 449 /**
 450  * dpu_encoder_phys_wb_wait_for_commit_done - wait until request is committed
 451  * @phys_enc:   Pointer to physical encoder
 452  */
 453 static int dpu_encoder_phys_wb_wait_for_commit_done(
 454                 struct dpu_encoder_phys *phys_enc)
 455 {
 456         unsigned long ret;
 457         struct dpu_encoder_wait_info wait_info;
 458         struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
 459
 460         wait_info.wq = &phys_enc->pending_kickoff_wq;
 461         wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
 462         wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
 463
 464         ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_WB_DONE,
 465                         dpu_encoder_phys_wb_done_irq, &wait_info);
 466         if (ret == -ETIMEDOUT)
 467                 _dpu_encoder_phys_wb_handle_wbdone_timeout(phys_enc);
 468         else if (!ret)
 469                 wb_enc->wb_done_timeout_cnt = 0;
 470
 471         return ret;
 472 }
 473
 474 /**
 475  * dpu_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
 476  * @phys_enc:   Pointer to physical encoder
 477  * Returns:     Zero on success
 478  */
 479 static void dpu_encoder_phys_wb_prepare_for_kickoff(
 480                 struct dpu_encoder_phys *phys_enc)
 481 {
 482         struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
 483         struct drm_connector *drm_conn;
 484         struct drm_connector_state *state;
 485
 486         DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
 487
 488         if (!wb_enc->wb_conn || !wb_enc->wb_job) {
 489                 DPU_ERROR("invalid wb_conn or wb_job\n");
 490                 return;
 491         }
 492
 493         drm_conn = &wb_enc->wb_conn->base;
 494         state = drm_conn->state;
 495
 496         if (wb_enc->wb_conn && wb_enc->wb_job)
 497                 drm_writeback_queue_job(wb_enc->wb_conn, state);
 498
 499         dpu_encoder_phys_wb_setup(phys_enc);
 500
 501         _dpu_encoder_phys_wb_update_flush(phys_enc);
 502 }
 503
 504 /**
 505  * dpu_encoder_phys_wb_needs_single_flush - trigger flush processing
 506  * @phys_enc:   Pointer to physical encoder
 507  */
 508 static bool dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys *phys_enc)
 509 {
 510         DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
 511         return false;
 512 }
 513
 514 /**
 515  * dpu_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
 516  * @phys_enc:   Pointer to physical encoder
 517  */
 518 static void dpu_encoder_phys_wb_handle_post_kickoff(
 519                 struct dpu_encoder_phys *phys_enc)
 520 {
 521         DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
 522
 523 }
 524
 525 /**
 526  * dpu_encoder_phys_wb_enable - enable writeback encoder
 527  * @phys_enc:   Pointer to physical encoder
 528  */
 529 static void dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc)
 530 {
 531         DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
 532         phys_enc->enable_state = DPU_ENC_ENABLED;
 533 }
 534 /**
 535  * dpu_encoder_phys_wb_disable - disable writeback encoder
 536  * @phys_enc:   Pointer to physical encoder
 537  */
 538 static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
 539 {
 540         struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
 541         struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
 542
 543         DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
 544
 545         if (phys_enc->enable_state == DPU_ENC_DISABLED) {
 546                 DPU_ERROR("encoder is already disabled\n");
 547                 return;
 548         }
 549
 550         /* reset h/w before final flush */
 551         if (phys_enc->hw_ctl->ops.clear_pending_flush)
 552                 phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
 553
 554         /*
 555          * New CTL reset sequence from 5.0 MDP onwards.
 556          * If has_3d_merge_reset is not set, legacy reset
 557          * sequence is executed.
 558          *
 559          * Legacy reset sequence has not been implemented yet.
 560          * Any target earlier than SM8150 will need it and when
 561          * WB support is added to those targets will need to add
 562          * the legacy teardown sequence as well.
 563          */
 564         if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG))
 565                 dpu_encoder_helper_phys_cleanup(phys_enc);
 566
 567         phys_enc->enable_state = DPU_ENC_DISABLED;
 568 }
 569
 570 /**
 571  * dpu_encoder_phys_wb_destroy - destroy writeback encoder
 572  * @phys_enc:   Pointer to physical encoder
 573  */
 574 static void dpu_encoder_phys_wb_destroy(struct dpu_encoder_phys *phys_enc)
 575 {
 576         if (!phys_enc)
 577                 return;
 578
 579         DPU_DEBUG("[wb:%d]\n", phys_enc->wb_idx - WB_0);
 580
 581         kfree(phys_enc);
 582 }
 583
 584 static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc,
 585                 struct drm_writeback_job *job)
 586 {
 587         const struct msm_format *format;
 588         struct msm_gem_address_space *aspace;
 589         struct dpu_hw_wb_cfg *wb_cfg;
 590         int ret;
 591         struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
 592
 593         if (!job->fb)
 594                 return;
 595
 596         wb_enc->wb_job = job;
 597         wb_enc->wb_conn = job->connector;
 598         aspace = phys_enc->dpu_kms->base.aspace;
 599
 600         wb_cfg = &wb_enc->wb_cfg;
 601
 602         memset(wb_cfg, 0, sizeof(struct dpu_hw_wb_cfg));
 603
 604         ret = msm_framebuffer_prepare(job->fb, aspace, false);
 605         if (ret) {
 606                 DPU_ERROR("prep fb failed, %d\n", ret);
 607                 return;
 608         }
 609
 610         format = msm_framebuffer_format(job->fb);
 611
 612         wb_cfg->dest.format = dpu_get_dpu_format_ext(
 613                         format->pixel_format, job->fb->modifier);
 614         if (!wb_cfg->dest.format) {
 615                 /* this error should be detected during atomic_check */
 616                 DPU_ERROR("failed to get format %x\n", format->pixel_format);
 617                 return;
 618         }
 619
 620         ret = dpu_format_populate_layout(aspace, job->fb, &wb_cfg->dest);
 621         if (ret) {
 622                 DPU_DEBUG("failed to populate layout %d\n", ret);
 623                 return;
 624         }
 625
 626         wb_cfg->dest.width = job->fb->width;
 627         wb_cfg->dest.height = job->fb->height;
 628         wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
 629
 630         if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) &&
 631                         (wb_cfg->dest.format->element[0] == C1_B_Cb))
 632                 swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
 633
 634         DPU_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
 635                         wb_cfg->dest.plane_addr[0], wb_cfg->dest.plane_addr[1],
 636                         wb_cfg->dest.plane_addr[2], wb_cfg->dest.plane_addr[3]);
 637
 638         DPU_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
 639                         wb_cfg->dest.plane_pitch[0], wb_cfg->dest.plane_pitch[1],
 640                         wb_cfg->dest.plane_pitch[2], wb_cfg->dest.plane_pitch[3]);
 641 }
 642
 643 static void dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys *phys_enc,
 644                 struct drm_writeback_job *job)
 645 {
 646         struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
 647         struct msm_gem_address_space *aspace;
 648
 649         if (!job->fb)
 650                 return;
 651
 652         aspace = phys_enc->dpu_kms->base.aspace;
 653
 654         msm_framebuffer_cleanup(job->fb, aspace, false);
 655         wb_enc->wb_job = NULL;
 656         wb_enc->wb_conn = NULL;
 657 }
 658
 659 static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phys_enc)
 660 {
 661         struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
 662
 663         if (wb_enc->wb_job)
 664                 return true;
 665         else
 666                 return false;
 667 }
 668
 669 /**
 670  * dpu_encoder_phys_wb_init_ops - initialize writeback operations
 671  * @ops:        Pointer to encoder operation table
 672  */
 673 static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)
 674 {
 675         ops->is_master = dpu_encoder_phys_wb_is_master;
 676         ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set;
 677         ops->enable = dpu_encoder_phys_wb_enable;
 678         ops->disable = dpu_encoder_phys_wb_disable;
 679         ops->destroy = dpu_encoder_phys_wb_destroy;
 680         ops->atomic_check = dpu_encoder_phys_wb_atomic_check;
 681         ops->wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done;
 682         ops->prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff;
 683         ops->handle_post_kickoff = dpu_encoder_phys_wb_handle_post_kickoff;
 684         ops->needs_single_flush = dpu_encoder_phys_wb_needs_single_flush;
 685         ops->trigger_start = dpu_encoder_helper_trigger_start;
 686         ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job;
 687         ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job;
 688         ops->irq_control = dpu_encoder_phys_wb_irq_ctrl;
 689         ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit;
 690
 691 }
 692
 693 /**
 694  * dpu_encoder_phys_wb_init - initialize writeback encoder
 695  * @init:       Pointer to init info structure with initialization params
 696  */
 697 struct dpu_encoder_phys *dpu_encoder_phys_wb_init(
 698                 struct dpu_enc_phys_init_params *p)
 699 {
 700         struct dpu_encoder_phys *phys_enc = NULL;
 701         struct dpu_encoder_phys_wb *wb_enc = NULL;
 702         int ret = 0;
 703         int i;
 704
 705         DPU_DEBUG("\n");
 706
 707         if (!p || !p->parent) {
 708                 DPU_ERROR("invalid params\n");
 709                 ret = -EINVAL;
 710                 goto fail_alloc;
 711         }
 712
 713         wb_enc = kzalloc(sizeof(*wb_enc), GFP_KERNEL);
 714         if (!wb_enc) {
 715                 DPU_ERROR("failed to allocate wb phys_enc enc\n");
 716                 ret = -ENOMEM;
 717                 goto fail_alloc;
 718         }
 719
 720         phys_enc = &wb_enc->base;
 721         phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
 722         phys_enc->wb_idx = p->wb_idx;
 723
 724         dpu_encoder_phys_wb_init_ops(&phys_enc->ops);
 725         phys_enc->parent = p->parent;
 726         phys_enc->parent_ops = p->parent_ops;
 727         phys_enc->dpu_kms = p->dpu_kms;
 728         phys_enc->split_role = p->split_role;
 729         phys_enc->intf_mode = INTF_MODE_WB_LINE;
 730         phys_enc->wb_idx = p->wb_idx;
 731         phys_enc->enc_spinlock = p->enc_spinlock;
 732
 733         atomic_set(&wb_enc->wbirq_refcount, 0);
 734
 735         for (i = 0; i < ARRAY_SIZE(phys_enc->irq); i++)
 736                 phys_enc->irq[i] = -EINVAL;
 737
 738         atomic_set(&phys_enc->pending_kickoff_cnt, 0);
 739         atomic_set(&phys_enc->vblank_refcount, 0);
 740         wb_enc->wb_done_timeout_cnt = 0;
 741
 742         init_waitqueue_head(&phys_enc->pending_kickoff_wq);
 743         phys_enc->enable_state = DPU_ENC_DISABLED;
 744
 745         DPU_DEBUG("Created dpu_encoder_phys for wb %d\n",
 746                         phys_enc->wb_idx);
 747
 748         return phys_enc;
 749
 750 fail_alloc:
 751         return ERR_PTR(ret);
 752 }