drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  */
   7
   8 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
   9 #include <linux/debugfs.h>
  10 #include <linux/kthread.h>
  11 #include <linux/seq_file.h>
  12
  13 #include <drm/drm_crtc.h>
  14 #include <drm/drm_file.h>
  15 #include <drm/drm_probe_helper.h>
  16
  17 #include "msm_drv.h"
  18 #include "dpu_kms.h"
  19 #include "dpu_hwio.h"
  20 #include "dpu_hw_catalog.h"
  21 #include "dpu_hw_intf.h"
  22 #include "dpu_hw_ctl.h"
  23 #include "dpu_formats.h"
  24 #include "dpu_encoder_phys.h"
  25 #include "dpu_crtc.h"
  26 #include "dpu_trace.h"
  27 #include "dpu_core_irq.h"
  28
  29 #define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\
  30                 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  31
  32 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
  33                 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  34
  35 #define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\
  36                 (p) ? (p)->parent->base.id : -1, \
  37                 (p) ? (p)->intf_idx - INTF_0 : -1, \
  38                 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  39                 ##__VA_ARGS__)
  40
  41 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\
  42                 (p) ? (p)->parent->base.id : -1, \
  43                 (p) ? (p)->intf_idx - INTF_0 : -1, \
  44                 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  45                 ##__VA_ARGS__)
  46
  47 /*
  48  * Two to anticipate panels that can do cmd/vid dynamic switching
  49  * plan is to create all possible physical encoder types, and switch between
  50  * them at runtime
  51  */
  52 #define NUM_PHYS_ENCODER_TYPES 2
  53
  54 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
  55         (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
  56
  57 #define MAX_CHANNELS_PER_ENC 2
  58
  59 #define IDLE_SHORT_TIMEOUT      1
  60
  61 #define MAX_VDISPLAY_SPLIT 1080
  62
  63 /* timeout in frames waiting for frame done */
  64 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
  65
  66 /**
  67  * enum dpu_enc_rc_events - events for resource control state machine
  68  * @DPU_ENC_RC_EVENT_KICKOFF:
  69  *      This event happens at NORMAL priority.
  70  *      Event that signals the start of the transfer. When this event is
  71  *      received, enable MDP/DSI core clocks. Regardless of the previous
  72  *      state, the resource should be in ON state at the end of this event.
  73  * @DPU_ENC_RC_EVENT_FRAME_DONE:
  74  *      This event happens at INTERRUPT level.
  75  *      Event signals the end of the data transfer after the PP FRAME_DONE
  76  *      event. At the end of this event, a delayed work is scheduled to go to
  77  *      IDLE_PC state after IDLE_TIMEOUT time.
  78  * @DPU_ENC_RC_EVENT_PRE_STOP:
  79  *      This event happens at NORMAL priority.
  80  *      This event, when received during the ON state, leave the RC STATE
  81  *      in the PRE_OFF state. It should be followed by the STOP event as
  82  *      part of encoder disable.
  83  *      If received during IDLE or OFF states, it will do nothing.
  84  * @DPU_ENC_RC_EVENT_STOP:
  85  *      This event happens at NORMAL priority.
  86  *      When this event is received, disable all the MDP/DSI core clocks, and
  87  *      disable IRQs. It should be called from the PRE_OFF or IDLE states.
  88  *      IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  89  *      PRE_OFF is expected when PRE_STOP was executed during the ON state.
  90  *      Resource state should be in OFF at the end of the event.
  91  * @DPU_ENC_RC_EVENT_ENTER_IDLE:
  92  *      This event happens at NORMAL priority from a work item.
  93  *      Event signals that there were no frame updates for IDLE_TIMEOUT time.
  94  *      This would disable MDP/DSI core clocks and change the resource state
  95  *      to IDLE.
  96  */
  97 enum dpu_enc_rc_events {
  98         DPU_ENC_RC_EVENT_KICKOFF = 1,
  99         DPU_ENC_RC_EVENT_FRAME_DONE,
 100         DPU_ENC_RC_EVENT_PRE_STOP,
 101         DPU_ENC_RC_EVENT_STOP,
 102         DPU_ENC_RC_EVENT_ENTER_IDLE
 103 };
 104
 105 /*
 106  * enum dpu_enc_rc_states - states that the resource control maintains
 107  * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
 108  * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
 109  * @DPU_ENC_RC_STATE_ON: Resource is in ON state
 110  * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
 111  * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
 112  */
 113 enum dpu_enc_rc_states {
 114         DPU_ENC_RC_STATE_OFF,
 115         DPU_ENC_RC_STATE_PRE_OFF,
 116         DPU_ENC_RC_STATE_ON,
 117         DPU_ENC_RC_STATE_IDLE
 118 };
 119
 120 /**
 121  * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
 122  *      encoders. Virtual encoder manages one "logical" display. Physical
 123  *      encoders manage one intf block, tied to a specific panel/sub-panel.
 124  *      Virtual encoder defers as much as possible to the physical encoders.
 125  *      Virtual encoder registers itself with the DRM Framework as the encoder.
 126  * @base:               drm_encoder base class for registration with DRM
 127  * @enc_spinlock:       Virtual-Encoder-Wide Spin Lock for IRQ purposes
 128  * @bus_scaling_client: Client handle to the bus scaling interface
 129  * @enabled:            True if the encoder is active, protected by enc_lock
 130  * @num_phys_encs:      Actual number of physical encoders contained.
 131  * @phys_encs:          Container of physical encoders managed.
 132  * @cur_master:         Pointer to the current master in this mode. Optimization
 133  *                      Only valid after enable. Cleared as disable.
 134  * @hw_pp               Handle to the pingpong blocks used for the display. No.
 135  *                      pingpong blocks can be different than num_phys_encs.
 136  * @intfs_swapped       Whether or not the phys_enc interfaces have been swapped
 137  *                      for partial update right-only cases, such as pingpong
 138  *                      split where virtual pingpong does not generate IRQs
 139  * @crtc:               Pointer to the currently assigned crtc. Normally you
 140  *                      would use crtc->state->encoder_mask to determine the
 141  *                      link between encoder/crtc. However in this case we need
 142  *                      to track crtc in the disable() hook which is called
 143  *                      _after_ encoder_mask is cleared.
 144  * @crtc_kickoff_cb:            Callback into CRTC that will flush & start
 145  *                              all CTL paths
 146  * @crtc_kickoff_cb_data:       Opaque user data given to crtc_kickoff_cb
 147  * @debugfs_root:               Debug file system root file node
 148  * @enc_lock:                   Lock around physical encoder
 149  *                              create/destroy/enable/disable
 150  * @frame_busy_mask:            Bitmask tracking which phys_enc we are still
 151  *                              busy processing current command.
 152  *                              Bit0 = phys_encs[0] etc.
 153  * @crtc_frame_event_cb:        callback handler for frame event
 154  * @crtc_frame_event_cb_data:   callback handler private data
 155  * @frame_done_timeout_ms:      frame done timeout in ms
 156  * @frame_done_timer:           watchdog timer for frame done event
 157  * @vsync_event_timer:          vsync timer
 158  * @disp_info:                  local copy of msm_display_info struct
 159  * @idle_pc_supported:          indicate if idle power collaps is supported
 160  * @rc_lock:                    resource control mutex lock to protect
 161  *                              virt encoder over various state changes
 162  * @rc_state:                   resource controller state
 163  * @delayed_off_work:           delayed worker to schedule disabling of
 164  *                              clks and resources after IDLE_TIMEOUT time.
 165  * @vsync_event_work:           worker to handle vsync event for autorefresh
 166  * @topology:                   topology of the display
 167  * @mode_set_complete:          flag to indicate modeset completion
 168  * @idle_timeout:               idle timeout duration in milliseconds
 169  */
 170 struct dpu_encoder_virt {
 171         struct drm_encoder base;
 172         spinlock_t enc_spinlock;
 173         uint32_t bus_scaling_client;
 174
 175         bool enabled;
 176
 177         unsigned int num_phys_encs;
 178         struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
 179         struct dpu_encoder_phys *cur_master;
 180         struct dpu_encoder_phys *cur_slave;
 181         struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
 182
 183         bool intfs_swapped;
 184
 185         struct drm_crtc *crtc;
 186
 187         struct dentry *debugfs_root;
 188         struct mutex enc_lock;
 189         DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
 190         void (*crtc_frame_event_cb)(void *, u32 event);
 191         void *crtc_frame_event_cb_data;
 192
 193         atomic_t frame_done_timeout_ms;
 194         struct timer_list frame_done_timer;
 195         struct timer_list vsync_event_timer;
 196
 197         struct msm_display_info disp_info;
 198
 199         bool idle_pc_supported;
 200         struct mutex rc_lock;
 201         enum dpu_enc_rc_states rc_state;
 202         struct delayed_work delayed_off_work;
 203         struct kthread_work vsync_event_work;
 204         struct msm_display_topology topology;
 205         bool mode_set_complete;
 206
 207         u32 idle_timeout;
 208 };
 209
 210 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
 211
 212 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
 213                 enum dpu_intr_idx intr_idx)
 214 {
 215         DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
 216                   DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
 217                   phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
 218
 219         if (phys_enc->parent_ops->handle_frame_done)
 220                 phys_enc->parent_ops->handle_frame_done(
 221                                 phys_enc->parent, phys_enc,
 222                                 DPU_ENCODER_FRAME_EVENT_ERROR);
 223 }
 224
 225 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
 226                 int32_t hw_id, struct dpu_encoder_wait_info *info);
 227
 228 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
 229                 enum dpu_intr_idx intr_idx,
 230                 struct dpu_encoder_wait_info *wait_info)
 231 {
 232         struct dpu_encoder_irq *irq;
 233         u32 irq_status;
 234         int ret;
 235
 236         if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
 237                 DPU_ERROR("invalid params\n");
 238                 return -EINVAL;
 239         }
 240         irq = &phys_enc->irq[intr_idx];
 241
 242         /* note: do master / slave checking outside */
 243
 244         /* return EWOULDBLOCK since we know the wait isn't necessary */
 245         if (phys_enc->enable_state == DPU_ENC_DISABLED) {
 246                 DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
 247                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 248                           irq->irq_idx);
 249                 return -EWOULDBLOCK;
 250         }
 251
 252         if (irq->irq_idx < 0) {
 253                 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
 254                               DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 255                               irq->name);
 256                 return 0;
 257         }
 258
 259         DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
 260                       DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 261                       irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
 262                       atomic_read(wait_info->atomic_cnt));
 263
 264         ret = dpu_encoder_helper_wait_event_timeout(
 265                         DRMID(phys_enc->parent),
 266                         irq->hw_idx,
 267                         wait_info);
 268
 269         if (ret <= 0) {
 270                 irq_status = dpu_core_irq_read(phys_enc->dpu_kms,
 271                                 irq->irq_idx, true);
 272                 if (irq_status) {
 273                         unsigned long flags;
 274
 275                         DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
 276                                       "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
 277                                       DRMID(phys_enc->parent), intr_idx,
 278                                       irq->hw_idx, irq->irq_idx,
 279                                       phys_enc->hw_pp->idx - PINGPONG_0,
 280                                       atomic_read(wait_info->atomic_cnt));
 281                         local_irq_save(flags);
 282                         irq->cb.func(phys_enc, irq->irq_idx);
 283                         local_irq_restore(flags);
 284                         ret = 0;
 285                 } else {
 286                         ret = -ETIMEDOUT;
 287                         DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
 288                                       "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
 289                                       DRMID(phys_enc->parent), intr_idx,
 290                                       irq->hw_idx, irq->irq_idx,
 291                                       phys_enc->hw_pp->idx - PINGPONG_0,
 292                                       atomic_read(wait_info->atomic_cnt));
 293                 }
 294         } else {
 295                 ret = 0;
 296                 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
 297                         intr_idx, irq->hw_idx, irq->irq_idx,
 298                         phys_enc->hw_pp->idx - PINGPONG_0,
 299                         atomic_read(wait_info->atomic_cnt));
 300         }
 301
 302         return ret;
 303 }
 304
 305 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
 306                 enum dpu_intr_idx intr_idx)
 307 {
 308         struct dpu_encoder_irq *irq;
 309         int ret = 0;
 310
 311         if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
 312                 DPU_ERROR("invalid params\n");
 313                 return -EINVAL;
 314         }
 315         irq = &phys_enc->irq[intr_idx];
 316
 317         if (irq->irq_idx >= 0) {
 318                 DPU_DEBUG_PHYS(phys_enc,
 319                                 "skipping already registered irq %s type %d\n",
 320                                 irq->name, irq->intr_type);
 321                 return 0;
 322         }
 323
 324         irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms,
 325                         irq->intr_type, irq->hw_idx);
 326         if (irq->irq_idx < 0) {
 327                 DPU_ERROR_PHYS(phys_enc,
 328                         "failed to lookup IRQ index for %s type:%d\n",
 329                         irq->name, irq->intr_type);
 330                 return -EINVAL;
 331         }
 332
 333         ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx,
 334                         &irq->cb);
 335         if (ret) {
 336                 DPU_ERROR_PHYS(phys_enc,
 337                         "failed to register IRQ callback for %s\n",
 338                         irq->name);
 339                 irq->irq_idx = -EINVAL;
 340                 return ret;
 341         }
 342
 343         ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
 344         if (ret) {
 345                 DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
 346                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 347                           irq->irq_idx);
 348                 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
 349                                 irq->irq_idx, &irq->cb);
 350                 irq->irq_idx = -EINVAL;
 351                 return ret;
 352         }
 353
 354         trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
 355                                 irq->hw_idx, irq->irq_idx);
 356
 357         return ret;
 358 }
 359
 360 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
 361                 enum dpu_intr_idx intr_idx)
 362 {
 363         struct dpu_encoder_irq *irq;
 364         int ret;
 365
 366         if (!phys_enc) {
 367                 DPU_ERROR("invalid encoder\n");
 368                 return -EINVAL;
 369         }
 370         irq = &phys_enc->irq[intr_idx];
 371
 372         /* silently skip irqs that weren't registered */
 373         if (irq->irq_idx < 0) {
 374                 DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
 375                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 376                           irq->irq_idx);
 377                 return 0;
 378         }
 379
 380         ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
 381         if (ret) {
 382                 DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
 383                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 384                           irq->irq_idx, ret);
 385         }
 386
 387         ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
 388                         &irq->cb);
 389         if (ret) {
 390                 DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
 391                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 392                           irq->irq_idx, ret);
 393         }
 394
 395         trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
 396                                              irq->hw_idx, irq->irq_idx);
 397
 398         irq->irq_idx = -EINVAL;
 399
 400         return 0;
 401 }
 402
 403 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
 404                                   struct dpu_encoder_hw_resources *hw_res)
 405 {
 406         struct dpu_encoder_virt *dpu_enc = NULL;
 407         int i = 0;
 408
 409         dpu_enc = to_dpu_encoder_virt(drm_enc);
 410         DPU_DEBUG_ENC(dpu_enc, "\n");
 411
 412         /* Query resources used by phys encs, expected to be without overlap */
 413         memset(hw_res, 0, sizeof(*hw_res));
 414
 415         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 416                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 417
 418                 if (phys && phys->ops.get_hw_resources)
 419                         phys->ops.get_hw_resources(phys, hw_res);
 420         }
 421 }
 422
 423 static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
 424 {
 425         struct dpu_encoder_virt *dpu_enc = NULL;
 426         int i = 0;
 427
 428         if (!drm_enc) {
 429                 DPU_ERROR("invalid encoder\n");
 430                 return;
 431         }
 432
 433         dpu_enc = to_dpu_encoder_virt(drm_enc);
 434         DPU_DEBUG_ENC(dpu_enc, "\n");
 435
 436         mutex_lock(&dpu_enc->enc_lock);
 437
 438         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 439                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 440
 441                 if (phys && phys->ops.destroy) {
 442                         phys->ops.destroy(phys);
 443                         --dpu_enc->num_phys_encs;
 444                         dpu_enc->phys_encs[i] = NULL;
 445                 }
 446         }
 447
 448         if (dpu_enc->num_phys_encs)
 449                 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n",
 450                                 dpu_enc->num_phys_encs);
 451         dpu_enc->num_phys_encs = 0;
 452         mutex_unlock(&dpu_enc->enc_lock);
 453
 454         drm_encoder_cleanup(drm_enc);
 455         mutex_destroy(&dpu_enc->enc_lock);
 456 }
 457
 458 void dpu_encoder_helper_split_config(
 459                 struct dpu_encoder_phys *phys_enc,
 460                 enum dpu_intf interface)
 461 {
 462         struct dpu_encoder_virt *dpu_enc;
 463         struct split_pipe_cfg cfg = { 0 };
 464         struct dpu_hw_mdp *hw_mdptop;
 465         struct msm_display_info *disp_info;
 466
 467         if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
 468                 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
 469                 return;
 470         }
 471
 472         dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
 473         hw_mdptop = phys_enc->hw_mdptop;
 474         disp_info = &dpu_enc->disp_info;
 475
 476         if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
 477                 return;
 478
 479         /**
 480          * disable split modes since encoder will be operating in as the only
 481          * encoder, either for the entire use case in the case of, for example,
 482          * single DSI, or for this frame in the case of left/right only partial
 483          * update.
 484          */
 485         if (phys_enc->split_role == ENC_ROLE_SOLO) {
 486                 if (hw_mdptop->ops.setup_split_pipe)
 487                         hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
 488                 return;
 489         }
 490
 491         cfg.en = true;
 492         cfg.mode = phys_enc->intf_mode;
 493         cfg.intf = interface;
 494
 495         if (cfg.en && phys_enc->ops.needs_single_flush &&
 496                         phys_enc->ops.needs_single_flush(phys_enc))
 497                 cfg.split_flush_en = true;
 498
 499         if (phys_enc->split_role == ENC_ROLE_MASTER) {
 500                 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
 501
 502                 if (hw_mdptop->ops.setup_split_pipe)
 503                         hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
 504         }
 505 }
 506
 507 static void _dpu_encoder_adjust_mode(struct drm_connector *connector,
 508                 struct drm_display_mode *adj_mode)
 509 {
 510         struct drm_display_mode *cur_mode;
 511
 512         if (!connector || !adj_mode)
 513                 return;
 514
 515         list_for_each_entry(cur_mode, &connector->modes, head) {
 516                 if (cur_mode->vdisplay == adj_mode->vdisplay &&
 517                     cur_mode->hdisplay == adj_mode->hdisplay &&
 518                     drm_mode_vrefresh(cur_mode) == drm_mode_vrefresh(adj_mode)) {
 519                         adj_mode->private = cur_mode->private;
 520                         adj_mode->private_flags |= cur_mode->private_flags;
 521                 }
 522         }
 523 }
 524
 525 static struct msm_display_topology dpu_encoder_get_topology(
 526                         struct dpu_encoder_virt *dpu_enc,
 527                         struct dpu_kms *dpu_kms,
 528                         struct drm_display_mode *mode)
 529 {
 530         struct msm_display_topology topology;
 531         int i, intf_count = 0;
 532
 533         for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
 534                 if (dpu_enc->phys_encs[i])
 535                         intf_count++;
 536
 537         /* User split topology for width > 1080 */
 538         topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
 539         topology.num_enc = 0;
 540         topology.num_intf = intf_count;
 541
 542         return topology;
 543 }
 544 static int dpu_encoder_virt_atomic_check(
 545                 struct drm_encoder *drm_enc,
 546                 struct drm_crtc_state *crtc_state,
 547                 struct drm_connector_state *conn_state)
 548 {
 549         struct dpu_encoder_virt *dpu_enc;
 550         struct msm_drm_private *priv;
 551         struct dpu_kms *dpu_kms;
 552         const struct drm_display_mode *mode;
 553         struct drm_display_mode *adj_mode;
 554         struct msm_display_topology topology;
 555         int i = 0;
 556         int ret = 0;
 557
 558         if (!drm_enc || !crtc_state || !conn_state) {
 559                 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
 560                                 drm_enc != 0, crtc_state != 0, conn_state != 0);
 561                 return -EINVAL;
 562         }
 563
 564         dpu_enc = to_dpu_encoder_virt(drm_enc);
 565         DPU_DEBUG_ENC(dpu_enc, "\n");
 566
 567         priv = drm_enc->dev->dev_private;
 568         dpu_kms = to_dpu_kms(priv->kms);
 569         mode = &crtc_state->mode;
 570         adj_mode = &crtc_state->adjusted_mode;
 571         trace_dpu_enc_atomic_check(DRMID(drm_enc));
 572
 573         /*
 574          * display drivers may populate private fields of the drm display mode
 575          * structure while registering possible modes of a connector with DRM.
 576          * These private fields are not populated back while DRM invokes
 577          * the mode_set callbacks. This module retrieves and populates the
 578          * private fields of the given mode.
 579          */
 580         _dpu_encoder_adjust_mode(conn_state->connector, adj_mode);
 581
 582         /* perform atomic check on the first physical encoder (master) */
 583         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 584                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 585
 586                 if (phys && phys->ops.atomic_check)
 587                         ret = phys->ops.atomic_check(phys, crtc_state,
 588                                         conn_state);
 589                 else if (phys && phys->ops.mode_fixup)
 590                         if (!phys->ops.mode_fixup(phys, mode, adj_mode))
 591                                 ret = -EINVAL;
 592
 593                 if (ret) {
 594                         DPU_ERROR_ENC(dpu_enc,
 595                                         "mode unsupported, phys idx %d\n", i);
 596                         break;
 597                 }
 598         }
 599
 600         topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
 601
 602         /* Reserve dynamic resources now. Indicating AtomicTest phase */
 603         if (!ret) {
 604                 /*
 605                  * Avoid reserving resources when mode set is pending. Topology
 606                  * info may not be available to complete reservation.
 607                  */
 608                 if (drm_atomic_crtc_needs_modeset(crtc_state)
 609                                 && dpu_enc->mode_set_complete) {
 610                         ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
 611                                              topology, true);
 612                         dpu_enc->mode_set_complete = false;
 613                 }
 614         }
 615
 616         trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags,
 617                         adj_mode->private_flags);
 618
 619         return ret;
 620 }
 621
 622 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
 623                         struct msm_display_info *disp_info)
 624 {
 625         struct dpu_vsync_source_cfg vsync_cfg = { 0 };
 626         struct msm_drm_private *priv;
 627         struct dpu_kms *dpu_kms;
 628         struct dpu_hw_mdp *hw_mdptop;
 629         struct drm_encoder *drm_enc;
 630         int i;
 631
 632         if (!dpu_enc || !disp_info) {
 633                 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
 634                                         dpu_enc != NULL, disp_info != NULL);
 635                 return;
 636         } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
 637                 DPU_ERROR("invalid num phys enc %d/%d\n",
 638                                 dpu_enc->num_phys_encs,
 639                                 (int) ARRAY_SIZE(dpu_enc->hw_pp));
 640                 return;
 641         }
 642
 643         drm_enc = &dpu_enc->base;
 644         /* this pointers are checked in virt_enable_helper */
 645         priv = drm_enc->dev->dev_private;
 646
 647         dpu_kms = to_dpu_kms(priv->kms);
 648         hw_mdptop = dpu_kms->hw_mdp;
 649         if (!hw_mdptop) {
 650                 DPU_ERROR("invalid mdptop\n");
 651                 return;
 652         }
 653
 654         if (hw_mdptop->ops.setup_vsync_source &&
 655                         disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
 656                 for (i = 0; i < dpu_enc->num_phys_encs; i++)
 657                         vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
 658
 659                 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
 660                 if (disp_info->is_te_using_watchdog_timer)
 661                         vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
 662                 else
 663                         vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
 664
 665                 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
 666         }
 667 }
 668
 669 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
 670 {
 671         struct dpu_encoder_virt *dpu_enc;
 672         int i;
 673
 674         if (!drm_enc) {
 675                 DPU_ERROR("invalid encoder\n");
 676                 return;
 677         }
 678
 679         dpu_enc = to_dpu_encoder_virt(drm_enc);
 680
 681         DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
 682         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 683                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 684
 685                 if (phys && phys->ops.irq_control)
 686                         phys->ops.irq_control(phys, enable);
 687         }
 688
 689 }
 690
 691 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
 692                 bool enable)
 693 {
 694         struct msm_drm_private *priv;
 695         struct dpu_kms *dpu_kms;
 696         struct dpu_encoder_virt *dpu_enc;
 697
 698         dpu_enc = to_dpu_encoder_virt(drm_enc);
 699         priv = drm_enc->dev->dev_private;
 700         dpu_kms = to_dpu_kms(priv->kms);
 701
 702         trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
 703
 704         if (!dpu_enc->cur_master) {
 705                 DPU_ERROR("encoder master not set\n");
 706                 return;
 707         }
 708
 709         if (enable) {
 710                 /* enable DPU core clks */
 711                 pm_runtime_get_sync(&dpu_kms->pdev->dev);
 712
 713                 /* enable all the irq */
 714                 _dpu_encoder_irq_control(drm_enc, true);
 715
 716         } else {
 717                 /* disable all the irq */
 718                 _dpu_encoder_irq_control(drm_enc, false);
 719
 720                 /* disable DPU core clks */
 721                 pm_runtime_put_sync(&dpu_kms->pdev->dev);
 722         }
 723
 724 }
 725
 726 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 727                 u32 sw_event)
 728 {
 729         struct dpu_encoder_virt *dpu_enc;
 730         struct msm_drm_private *priv;
 731         bool is_vid_mode = false;
 732
 733         if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
 734                 DPU_ERROR("invalid parameters\n");
 735                 return -EINVAL;
 736         }
 737         dpu_enc = to_dpu_encoder_virt(drm_enc);
 738         priv = drm_enc->dev->dev_private;
 739         is_vid_mode = dpu_enc->disp_info.capabilities &
 740                                                 MSM_DISPLAY_CAP_VID_MODE;
 741
 742         /*
 743          * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
 744          * events and return early for other events (ie wb display).
 745          */
 746         if (!dpu_enc->idle_pc_supported &&
 747                         (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
 748                         sw_event != DPU_ENC_RC_EVENT_STOP &&
 749                         sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
 750                 return 0;
 751
 752         trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
 753                          dpu_enc->rc_state, "begin");
 754
 755         switch (sw_event) {
 756         case DPU_ENC_RC_EVENT_KICKOFF:
 757                 /* cancel delayed off work, if any */
 758                 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
 759                         DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
 760                                         sw_event);
 761
 762                 mutex_lock(&dpu_enc->rc_lock);
 763
 764                 /* return if the resource control is already in ON state */
 765                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
 766                         DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n",
 767                                       DRMID(drm_enc), sw_event);
 768                         mutex_unlock(&dpu_enc->rc_lock);
 769                         return 0;
 770                 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
 771                                 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
 772                         DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n",
 773                                       DRMID(drm_enc), sw_event,
 774                                       dpu_enc->rc_state);
 775                         mutex_unlock(&dpu_enc->rc_lock);
 776                         return -EINVAL;
 777                 }
 778
 779                 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
 780                         _dpu_encoder_irq_control(drm_enc, true);
 781                 else
 782                         _dpu_encoder_resource_control_helper(drm_enc, true);
 783
 784                 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
 785
 786                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 787                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 788                                  "kickoff");
 789
 790                 mutex_unlock(&dpu_enc->rc_lock);
 791                 break;
 792
 793         case DPU_ENC_RC_EVENT_FRAME_DONE:
 794                 /*
 795                  * mutex lock is not used as this event happens at interrupt
 796                  * context. And locking is not required as, the other events
 797                  * like KICKOFF and STOP does a wait-for-idle before executing
 798                  * the resource_control
 799                  */
 800                 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
 801                         DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
 802                                       DRMID(drm_enc), sw_event,
 803                                       dpu_enc->rc_state);
 804                         return -EINVAL;
 805                 }
 806
 807                 /*
 808                  * schedule off work item only when there are no
 809                  * frames pending
 810                  */
 811                 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
 812                         DRM_DEBUG_KMS("id:%d skip schedule work\n",
 813                                       DRMID(drm_enc));
 814                         return 0;
 815                 }
 816
 817                 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
 818                                    msecs_to_jiffies(dpu_enc->idle_timeout));
 819
 820                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 821                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 822                                  "frame done");
 823                 break;
 824
 825         case DPU_ENC_RC_EVENT_PRE_STOP:
 826                 /* cancel delayed off work, if any */
 827                 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
 828                         DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
 829                                         sw_event);
 830
 831                 mutex_lock(&dpu_enc->rc_lock);
 832
 833                 if (is_vid_mode &&
 834                           dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
 835                         _dpu_encoder_irq_control(drm_enc, true);
 836                 }
 837                 /* skip if is already OFF or IDLE, resources are off already */
 838                 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
 839                                 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
 840                         DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
 841                                       DRMID(drm_enc), sw_event,
 842                                       dpu_enc->rc_state);
 843                         mutex_unlock(&dpu_enc->rc_lock);
 844                         return 0;
 845                 }
 846
 847                 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
 848
 849                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 850                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 851                                  "pre stop");
 852
 853                 mutex_unlock(&dpu_enc->rc_lock);
 854                 break;
 855
 856         case DPU_ENC_RC_EVENT_STOP:
 857                 mutex_lock(&dpu_enc->rc_lock);
 858
 859                 /* return if the resource control is already in OFF state */
 860                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
 861                         DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
 862                                       DRMID(drm_enc), sw_event);
 863                         mutex_unlock(&dpu_enc->rc_lock);
 864                         return 0;
 865                 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
 866                         DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
 867                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 868                         mutex_unlock(&dpu_enc->rc_lock);
 869                         return -EINVAL;
 870                 }
 871
 872                 /**
 873                  * expect to arrive here only if in either idle state or pre-off
 874                  * and in IDLE state the resources are already disabled
 875                  */
 876                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
 877                         _dpu_encoder_resource_control_helper(drm_enc, false);
 878
 879                 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
 880
 881                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 882                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 883                                  "stop");
 884
 885                 mutex_unlock(&dpu_enc->rc_lock);
 886                 break;
 887
 888         case DPU_ENC_RC_EVENT_ENTER_IDLE:
 889                 mutex_lock(&dpu_enc->rc_lock);
 890
 891                 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
 892                         DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
 893                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 894                         mutex_unlock(&dpu_enc->rc_lock);
 895                         return 0;
 896                 }
 897
 898                 /*
 899                  * if we are in ON but a frame was just kicked off,
 900                  * ignore the IDLE event, it's probably a stale timer event
 901                  */
 902                 if (dpu_enc->frame_busy_mask[0]) {
 903                         DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
 904                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 905                         mutex_unlock(&dpu_enc->rc_lock);
 906                         return 0;
 907                 }
 908
 909                 if (is_vid_mode)
 910                         _dpu_encoder_irq_control(drm_enc, false);
 911                 else
 912                         _dpu_encoder_resource_control_helper(drm_enc, false);
 913
 914                 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
 915
 916                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 917                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 918                                  "idle");
 919
 920                 mutex_unlock(&dpu_enc->rc_lock);
 921                 break;
 922
 923         default:
 924                 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
 925                           sw_event);
 926                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 927                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 928                                  "error");
 929                 break;
 930         }
 931
 932         trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 933                          dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 934                          "end");
 935         return 0;
 936 }
 937
 938 static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 939                                       struct drm_display_mode *mode,
 940                                       struct drm_display_mode *adj_mode)
 941 {
 942         struct dpu_encoder_virt *dpu_enc;
 943         struct msm_drm_private *priv;
 944         struct dpu_kms *dpu_kms;
 945         struct list_head *connector_list;
 946         struct drm_connector *conn = NULL, *conn_iter;
 947         struct drm_crtc *drm_crtc;
 948         struct dpu_crtc_state *cstate;
 949         struct dpu_rm_hw_iter hw_iter;
 950         struct msm_display_topology topology;
 951         struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
 952         struct dpu_hw_mixer *hw_lm[MAX_CHANNELS_PER_ENC] = { NULL };
 953         int num_lm = 0, num_ctl = 0;
 954         int i, j, ret;
 955
 956         if (!drm_enc) {
 957                 DPU_ERROR("invalid encoder\n");
 958                 return;
 959         }
 960
 961         dpu_enc = to_dpu_encoder_virt(drm_enc);
 962         DPU_DEBUG_ENC(dpu_enc, "\n");
 963
 964         priv = drm_enc->dev->dev_private;
 965         dpu_kms = to_dpu_kms(priv->kms);
 966         connector_list = &dpu_kms->dev->mode_config.connector_list;
 967
 968         trace_dpu_enc_mode_set(DRMID(drm_enc));
 969
 970         list_for_each_entry(conn_iter, connector_list, head)
 971                 if (conn_iter->encoder == drm_enc)
 972                         conn = conn_iter;
 973
 974         if (!conn) {
 975                 DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n");
 976                 return;
 977         } else if (!conn->state) {
 978                 DPU_ERROR_ENC(dpu_enc, "invalid connector state\n");
 979                 return;
 980         }
 981
 982         drm_for_each_crtc(drm_crtc, drm_enc->dev)
 983                 if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc))
 984                         break;
 985
 986         topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
 987
 988         /* Reserve dynamic resources now. Indicating non-AtomicTest phase */
 989         ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, drm_crtc->state,
 990                              topology, false);
 991         if (ret) {
 992                 DPU_ERROR_ENC(dpu_enc,
 993                                 "failed to reserve hw resources, %d\n", ret);
 994                 return;
 995         }
 996
 997         dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_PINGPONG);
 998         for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
 999                 dpu_enc->hw_pp[i] = NULL;
1000                 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1001                         break;
1002                 dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) hw_iter.hw;
1003         }
1004
1005         dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
1006         for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1007                 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1008                         break;
1009                 hw_ctl[i] = (struct dpu_hw_ctl *)hw_iter.hw;
1010                 num_ctl++;
1011         }
1012
1013         dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_LM);
1014         for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1015                 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1016                         break;
1017                 hw_lm[i] = (struct dpu_hw_mixer *)hw_iter.hw;
1018                 num_lm++;
1019         }
1020
1021         cstate = to_dpu_crtc_state(drm_crtc->state);
1022
1023         for (i = 0; i < num_lm; i++) {
1024                 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1025
1026                 cstate->mixers[i].hw_lm = hw_lm[i];
1027                 cstate->mixers[i].lm_ctl = hw_ctl[ctl_idx];
1028         }
1029
1030         cstate->num_mixers = num_lm;
1031
1032         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1033                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1034
1035                 if (phys) {
1036                         if (!dpu_enc->hw_pp[i]) {
1037                                 DPU_ERROR_ENC(dpu_enc, "no pp block assigned"
1038                                              "at idx: %d\n", i);
1039                                 goto error;
1040                         }
1041
1042                         if (!hw_ctl[i]) {
1043                                 DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
1044                                              "at idx: %d\n", i);
1045                                 goto error;
1046                         }
1047
1048                         phys->hw_pp = dpu_enc->hw_pp[i];
1049                         phys->hw_ctl = hw_ctl[i];
1050
1051                         dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id,
1052                                             DPU_HW_BLK_INTF);
1053                         for (j = 0; j < MAX_CHANNELS_PER_ENC; j++) {
1054                                 struct dpu_hw_intf *hw_intf;
1055
1056                                 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1057                                         break;
1058
1059                                 hw_intf = (struct dpu_hw_intf *)hw_iter.hw;
1060                                 if (hw_intf->idx == phys->intf_idx)
1061                                         phys->hw_intf = hw_intf;
1062                         }
1063
1064                         if (!phys->hw_intf) {
1065                                 DPU_ERROR_ENC(dpu_enc,
1066                                               "no intf block assigned at idx: %d\n",
1067                                               i);
1068                                 goto error;
1069                         }
1070
1071                         phys->connector = conn->state->connector;
1072                         if (phys->ops.mode_set)
1073                                 phys->ops.mode_set(phys, mode, adj_mode);
1074                 }
1075         }
1076
1077         dpu_enc->mode_set_complete = true;
1078
1079 error:
1080         dpu_rm_release(&dpu_kms->rm, drm_enc);
1081 }
1082
1083 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1084 {
1085         struct dpu_encoder_virt *dpu_enc = NULL;
1086         struct msm_drm_private *priv;
1087         struct dpu_kms *dpu_kms;
1088
1089         if (!drm_enc || !drm_enc->dev) {
1090                 DPU_ERROR("invalid parameters\n");
1091                 return;
1092         }
1093
1094         priv = drm_enc->dev->dev_private;
1095         dpu_kms = to_dpu_kms(priv->kms);
1096
1097         dpu_enc = to_dpu_encoder_virt(drm_enc);
1098         if (!dpu_enc || !dpu_enc->cur_master) {
1099                 DPU_ERROR("invalid dpu encoder/master\n");
1100                 return;
1101         }
1102
1103         if (dpu_enc->cur_master->hw_mdptop &&
1104                         dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc)
1105                 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc(
1106                                 dpu_enc->cur_master->hw_mdptop,
1107                                 dpu_kms->catalog);
1108
1109         _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1110 }
1111
1112 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1113 {
1114         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1115
1116         mutex_lock(&dpu_enc->enc_lock);
1117
1118         if (!dpu_enc->enabled)
1119                 goto out;
1120
1121         if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1122                 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1123         if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1124                 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1125
1126         _dpu_encoder_virt_enable_helper(drm_enc);
1127
1128 out:
1129         mutex_unlock(&dpu_enc->enc_lock);
1130 }
1131
1132 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
1133 {
1134         struct dpu_encoder_virt *dpu_enc = NULL;
1135         int ret = 0;
1136         struct drm_display_mode *cur_mode = NULL;
1137
1138         if (!drm_enc) {
1139                 DPU_ERROR("invalid encoder\n");
1140                 return;
1141         }
1142         dpu_enc = to_dpu_encoder_virt(drm_enc);
1143
1144         mutex_lock(&dpu_enc->enc_lock);
1145         cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1146
1147         trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1148                              cur_mode->vdisplay);
1149
1150         /* always enable slave encoder before master */
1151         if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1152                 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1153
1154         if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1155                 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1156
1157         ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1158         if (ret) {
1159                 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1160                                 ret);
1161                 goto out;
1162         }
1163
1164         _dpu_encoder_virt_enable_helper(drm_enc);
1165
1166         dpu_enc->enabled = true;
1167
1168 out:
1169         mutex_unlock(&dpu_enc->enc_lock);
1170 }
1171
1172 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
1173 {
1174         struct dpu_encoder_virt *dpu_enc = NULL;
1175         struct msm_drm_private *priv;
1176         struct dpu_kms *dpu_kms;
1177         int i = 0;
1178
1179         if (!drm_enc) {
1180                 DPU_ERROR("invalid encoder\n");
1181                 return;
1182         } else if (!drm_enc->dev) {
1183                 DPU_ERROR("invalid dev\n");
1184                 return;
1185         }
1186
1187         dpu_enc = to_dpu_encoder_virt(drm_enc);
1188         DPU_DEBUG_ENC(dpu_enc, "\n");
1189
1190         mutex_lock(&dpu_enc->enc_lock);
1191         dpu_enc->enabled = false;
1192
1193         priv = drm_enc->dev->dev_private;
1194         dpu_kms = to_dpu_kms(priv->kms);
1195
1196         trace_dpu_enc_disable(DRMID(drm_enc));
1197
1198         /* wait for idle */
1199         dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
1200
1201         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1202
1203         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1204                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1205
1206                 if (phys && phys->ops.disable)
1207                         phys->ops.disable(phys);
1208         }
1209
1210         /* after phys waits for frame-done, should be no more frames pending */
1211         if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1212                 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1213                 del_timer_sync(&dpu_enc->frame_done_timer);
1214         }
1215
1216         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1217
1218         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1219                 if (dpu_enc->phys_encs[i])
1220                         dpu_enc->phys_encs[i]->connector = NULL;
1221         }
1222
1223         DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1224
1225         dpu_rm_release(&dpu_kms->rm, drm_enc);
1226
1227         mutex_unlock(&dpu_enc->enc_lock);
1228 }
1229
1230 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
1231                 enum dpu_intf_type type, u32 controller_id)
1232 {
1233         int i = 0;
1234
1235         for (i = 0; i < catalog->intf_count; i++) {
1236                 if (catalog->intf[i].type == type
1237                     && catalog->intf[i].controller_id == controller_id) {
1238                         return catalog->intf[i].id;
1239                 }
1240         }
1241
1242         return INTF_MAX;
1243 }
1244
1245 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1246                 struct dpu_encoder_phys *phy_enc)
1247 {
1248         struct dpu_encoder_virt *dpu_enc = NULL;
1249         unsigned long lock_flags;
1250
1251         if (!drm_enc || !phy_enc)
1252                 return;
1253
1254         DPU_ATRACE_BEGIN("encoder_vblank_callback");
1255         dpu_enc = to_dpu_encoder_virt(drm_enc);
1256
1257         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1258         if (dpu_enc->crtc)
1259                 dpu_crtc_vblank_callback(dpu_enc->crtc);
1260         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1261
1262         atomic_inc(&phy_enc->vsync_cnt);
1263         DPU_ATRACE_END("encoder_vblank_callback");
1264 }
1265
1266 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1267                 struct dpu_encoder_phys *phy_enc)
1268 {
1269         if (!phy_enc)
1270                 return;
1271
1272         DPU_ATRACE_BEGIN("encoder_underrun_callback");
1273         atomic_inc(&phy_enc->underrun_cnt);
1274         trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1275                                   atomic_read(&phy_enc->underrun_cnt));
1276         DPU_ATRACE_END("encoder_underrun_callback");
1277 }
1278
1279 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1280 {
1281         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1282         unsigned long lock_flags;
1283
1284         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1285         /* crtc should always be cleared before re-assigning */
1286         WARN_ON(crtc && dpu_enc->crtc);
1287         dpu_enc->crtc = crtc;
1288         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1289 }
1290
1291 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1292                                         struct drm_crtc *crtc, bool enable)
1293 {
1294         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1295         unsigned long lock_flags;
1296         int i;
1297
1298         trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1299
1300         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1301         if (dpu_enc->crtc != crtc) {
1302                 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1303                 return;
1304         }
1305         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1306
1307         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1308                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1309
1310                 if (phys && phys->ops.control_vblank_irq)
1311                         phys->ops.control_vblank_irq(phys, enable);
1312         }
1313 }
1314
1315 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
1316                 void (*frame_event_cb)(void *, u32 event),
1317                 void *frame_event_cb_data)
1318 {
1319         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1320         unsigned long lock_flags;
1321         bool enable;
1322
1323         enable = frame_event_cb ? true : false;
1324
1325         if (!drm_enc) {
1326                 DPU_ERROR("invalid encoder\n");
1327                 return;
1328         }
1329         trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable);
1330
1331         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1332         dpu_enc->crtc_frame_event_cb = frame_event_cb;
1333         dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data;
1334         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1335 }
1336
1337 static void dpu_encoder_frame_done_callback(
1338                 struct drm_encoder *drm_enc,
1339                 struct dpu_encoder_phys *ready_phys, u32 event)
1340 {
1341         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1342         unsigned int i;
1343
1344         if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1345                         | DPU_ENCODER_FRAME_EVENT_ERROR
1346                         | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1347
1348                 if (!dpu_enc->frame_busy_mask[0]) {
1349                         /**
1350                          * suppress frame_done without waiter,
1351                          * likely autorefresh
1352                          */
1353                         trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc),
1354                                         event, ready_phys->intf_idx);
1355                         return;
1356                 }
1357
1358                 /* One of the physical encoders has become idle */
1359                 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1360                         if (dpu_enc->phys_encs[i] == ready_phys) {
1361                                 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1362                                                 dpu_enc->frame_busy_mask[0]);
1363                                 clear_bit(i, dpu_enc->frame_busy_mask);
1364                         }
1365                 }
1366
1367                 if (!dpu_enc->frame_busy_mask[0]) {
1368                         atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1369                         del_timer(&dpu_enc->frame_done_timer);
1370
1371                         dpu_encoder_resource_control(drm_enc,
1372                                         DPU_ENC_RC_EVENT_FRAME_DONE);
1373
1374                         if (dpu_enc->crtc_frame_event_cb)
1375                                 dpu_enc->crtc_frame_event_cb(
1376                                         dpu_enc->crtc_frame_event_cb_data,
1377                                         event);
1378                 }
1379         } else {
1380                 if (dpu_enc->crtc_frame_event_cb)
1381                         dpu_enc->crtc_frame_event_cb(
1382                                 dpu_enc->crtc_frame_event_cb_data, event);
1383         }
1384 }
1385
1386 static void dpu_encoder_off_work(struct work_struct *work)
1387 {
1388         struct dpu_encoder_virt *dpu_enc = container_of(work,
1389                         struct dpu_encoder_virt, delayed_off_work.work);
1390
1391         if (!dpu_enc) {
1392                 DPU_ERROR("invalid dpu encoder\n");
1393                 return;
1394         }
1395
1396         dpu_encoder_resource_control(&dpu_enc->base,
1397                                                 DPU_ENC_RC_EVENT_ENTER_IDLE);
1398
1399         dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1400                                 DPU_ENCODER_FRAME_EVENT_IDLE);
1401 }
1402
1403 /**
1404  * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1405  * drm_enc: Pointer to drm encoder structure
1406  * phys: Pointer to physical encoder structure
1407  * extra_flush_bits: Additional bit mask to include in flush trigger
1408  */
1409 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1410                 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1411 {
1412         struct dpu_hw_ctl *ctl;
1413         int pending_kickoff_cnt;
1414         u32 ret = UINT_MAX;
1415
1416         if (!phys->hw_pp) {
1417                 DPU_ERROR("invalid pingpong hw\n");
1418                 return;
1419         }
1420
1421         ctl = phys->hw_ctl;
1422         if (!ctl || !ctl->ops.trigger_flush) {
1423                 DPU_ERROR("missing trigger cb\n");
1424                 return;
1425         }
1426
1427         pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1428
1429         if (extra_flush_bits && ctl->ops.update_pending_flush)
1430                 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1431
1432         ctl->ops.trigger_flush(ctl);
1433
1434         if (ctl->ops.get_pending_flush)
1435                 ret = ctl->ops.get_pending_flush(ctl);
1436
1437         trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
1438                                     pending_kickoff_cnt, ctl->idx,
1439                                     extra_flush_bits, ret);
1440 }
1441
1442 /**
1443  * _dpu_encoder_trigger_start - trigger start for a physical encoder
1444  * phys: Pointer to physical encoder structure
1445  */
1446 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1447 {
1448         if (!phys) {
1449                 DPU_ERROR("invalid argument(s)\n");
1450                 return;
1451         }
1452
1453         if (!phys->hw_pp) {
1454                 DPU_ERROR("invalid pingpong hw\n");
1455                 return;
1456         }
1457
1458         if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1459                 phys->ops.trigger_start(phys);
1460 }
1461
1462 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1463 {
1464         struct dpu_hw_ctl *ctl;
1465
1466         if (!phys_enc) {
1467                 DPU_ERROR("invalid encoder\n");
1468                 return;
1469         }
1470
1471         ctl = phys_enc->hw_ctl;
1472         if (ctl && ctl->ops.trigger_start) {
1473                 ctl->ops.trigger_start(ctl);
1474                 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1475         }
1476 }
1477
1478 static int dpu_encoder_helper_wait_event_timeout(
1479                 int32_t drm_id,
1480                 int32_t hw_id,
1481                 struct dpu_encoder_wait_info *info)
1482 {
1483         int rc = 0;
1484         s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1485         s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1486         s64 time;
1487
1488         do {
1489                 rc = wait_event_timeout(*(info->wq),
1490                                 atomic_read(info->atomic_cnt) == 0, jiffies);
1491                 time = ktime_to_ms(ktime_get());
1492
1493                 trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
1494                                                  expected_time,
1495                                                  atomic_read(info->atomic_cnt));
1496         /* If we timed out, counter is valid and time is less, wait again */
1497         } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1498                         (time < expected_time));
1499
1500         return rc;
1501 }
1502
1503 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1504 {
1505         struct dpu_encoder_virt *dpu_enc;
1506         struct dpu_hw_ctl *ctl;
1507         int rc;
1508
1509         if (!phys_enc) {
1510                 DPU_ERROR("invalid encoder\n");
1511                 return;
1512         }
1513         dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1514         ctl = phys_enc->hw_ctl;
1515
1516         if (!ctl || !ctl->ops.reset)
1517                 return;
1518
1519         DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
1520                       ctl->idx);
1521
1522         rc = ctl->ops.reset(ctl);
1523         if (rc)
1524                 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n",  ctl->idx);
1525
1526         phys_enc->enable_state = DPU_ENC_ENABLED;
1527 }
1528
1529 /**
1530  * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1531  *      Iterate through the physical encoders and perform consolidated flush
1532  *      and/or control start triggering as needed. This is done in the virtual
1533  *      encoder rather than the individual physical ones in order to handle
1534  *      use cases that require visibility into multiple physical encoders at
1535  *      a time.
1536  * dpu_enc: Pointer to virtual encoder structure
1537  */
1538 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1539 {
1540         struct dpu_hw_ctl *ctl;
1541         uint32_t i, pending_flush;
1542         unsigned long lock_flags;
1543
1544         pending_flush = 0x0;
1545
1546         /* update pending counts and trigger kickoff ctl flush atomically */
1547         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1548
1549         /* don't perform flush/start operations for slave encoders */
1550         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1551                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1552
1553                 if (!phys || phys->enable_state == DPU_ENC_DISABLED)
1554                         continue;
1555
1556                 ctl = phys->hw_ctl;
1557                 if (!ctl)
1558                         continue;
1559
1560                 /*
1561                  * This is cleared in frame_done worker, which isn't invoked
1562                  * for async commits. So don't set this for async, since it'll
1563                  * roll over to the next commit.
1564                  */
1565                 if (phys->split_role != ENC_ROLE_SLAVE)
1566                         set_bit(i, dpu_enc->frame_busy_mask);
1567
1568                 if (!phys->ops.needs_single_flush ||
1569                                 !phys->ops.needs_single_flush(phys))
1570                         _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1571                 else if (ctl->ops.get_pending_flush)
1572                         pending_flush |= ctl->ops.get_pending_flush(ctl);
1573         }
1574
1575         /* for split flush, combine pending flush masks and send to master */
1576         if (pending_flush && dpu_enc->cur_master) {
1577                 _dpu_encoder_trigger_flush(
1578                                 &dpu_enc->base,
1579                                 dpu_enc->cur_master,
1580                                 pending_flush);
1581         }
1582
1583         _dpu_encoder_trigger_start(dpu_enc->cur_master);
1584
1585         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1586 }
1587
1588 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1589 {
1590         struct dpu_encoder_virt *dpu_enc;
1591         struct dpu_encoder_phys *phys;
1592         unsigned int i;
1593         struct dpu_hw_ctl *ctl;
1594         struct msm_display_info *disp_info;
1595
1596         if (!drm_enc) {
1597                 DPU_ERROR("invalid encoder\n");
1598                 return;
1599         }
1600         dpu_enc = to_dpu_encoder_virt(drm_enc);
1601         disp_info = &dpu_enc->disp_info;
1602
1603         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1604                 phys = dpu_enc->phys_encs[i];
1605
1606                 if (phys && phys->hw_ctl) {
1607                         ctl = phys->hw_ctl;
1608                         if (ctl->ops.clear_pending_flush)
1609                                 ctl->ops.clear_pending_flush(ctl);
1610
1611                         /* update only for command mode primary ctl */
1612                         if ((phys == dpu_enc->cur_master) &&
1613                            (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
1614                             && ctl->ops.trigger_pending)
1615                                 ctl->ops.trigger_pending(ctl);
1616                 }
1617         }
1618 }
1619
1620 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1621                 struct drm_display_mode *mode)
1622 {
1623         u64 pclk_rate;
1624         u32 pclk_period;
1625         u32 line_time;
1626
1627         /*
1628          * For linetime calculation, only operate on master encoder.
1629          */
1630         if (!dpu_enc->cur_master)
1631                 return 0;
1632
1633         if (!dpu_enc->cur_master->ops.get_line_count) {
1634                 DPU_ERROR("get_line_count function not defined\n");
1635                 return 0;
1636         }
1637
1638         pclk_rate = mode->clock; /* pixel clock in kHz */
1639         if (pclk_rate == 0) {
1640                 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1641                 return 0;
1642         }
1643
1644         pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1645         if (pclk_period == 0) {
1646                 DPU_ERROR("pclk period is 0\n");
1647                 return 0;
1648         }
1649
1650         /*
1651          * Line time calculation based on Pixel clock and HTOTAL.
1652          * Final unit is in ns.
1653          */
1654         line_time = (pclk_period * mode->htotal) / 1000;
1655         if (line_time == 0) {
1656                 DPU_ERROR("line time calculation is 0\n");
1657                 return 0;
1658         }
1659
1660         DPU_DEBUG_ENC(dpu_enc,
1661                         "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1662                         pclk_rate, pclk_period, line_time);
1663
1664         return line_time;
1665 }
1666
1667 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1668 {
1669         struct drm_display_mode *mode;
1670         struct dpu_encoder_virt *dpu_enc;
1671         u32 cur_line;
1672         u32 line_time;
1673         u32 vtotal, time_to_vsync;
1674         ktime_t cur_time;
1675
1676         dpu_enc = to_dpu_encoder_virt(drm_enc);
1677
1678         if (!drm_enc->crtc || !drm_enc->crtc->state) {
1679                 DPU_ERROR("crtc/crtc state object is NULL\n");
1680                 return -EINVAL;
1681         }
1682         mode = &drm_enc->crtc->state->adjusted_mode;
1683
1684         line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1685         if (!line_time)
1686                 return -EINVAL;
1687
1688         cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1689
1690         vtotal = mode->vtotal;
1691         if (cur_line >= vtotal)
1692                 time_to_vsync = line_time * vtotal;
1693         else
1694                 time_to_vsync = line_time * (vtotal - cur_line);
1695
1696         if (time_to_vsync == 0) {
1697                 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1698                                 vtotal);
1699                 return -EINVAL;
1700         }
1701
1702         cur_time = ktime_get();
1703         *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1704
1705         DPU_DEBUG_ENC(dpu_enc,
1706                         "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1707                         cur_line, vtotal, time_to_vsync,
1708                         ktime_to_ms(cur_time),
1709                         ktime_to_ms(*wakeup_time));
1710         return 0;
1711 }
1712
1713 static void dpu_encoder_vsync_event_handler(struct timer_list *t)
1714 {
1715         struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
1716                         vsync_event_timer);
1717         struct drm_encoder *drm_enc = &dpu_enc->base;
1718         struct msm_drm_private *priv;
1719         struct msm_drm_thread *event_thread;
1720
1721         if (!drm_enc->dev || !drm_enc->crtc) {
1722                 DPU_ERROR("invalid parameters\n");
1723                 return;
1724         }
1725
1726         priv = drm_enc->dev->dev_private;
1727
1728         if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
1729                 DPU_ERROR("invalid crtc index\n");
1730                 return;
1731         }
1732         event_thread = &priv->event_thread[drm_enc->crtc->index];
1733         if (!event_thread) {
1734                 DPU_ERROR("event_thread not found for crtc:%d\n",
1735                                 drm_enc->crtc->index);
1736                 return;
1737         }
1738
1739         del_timer(&dpu_enc->vsync_event_timer);
1740 }
1741
1742 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
1743 {
1744         struct dpu_encoder_virt *dpu_enc = container_of(work,
1745                         struct dpu_encoder_virt, vsync_event_work);
1746         ktime_t wakeup_time;
1747
1748         if (!dpu_enc) {
1749                 DPU_ERROR("invalid dpu encoder\n");
1750                 return;
1751         }
1752
1753         if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
1754                 return;
1755
1756         trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
1757         mod_timer(&dpu_enc->vsync_event_timer,
1758                         nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1759 }
1760
1761 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
1762 {
1763         struct dpu_encoder_virt *dpu_enc;
1764         struct dpu_encoder_phys *phys;
1765         bool needs_hw_reset = false;
1766         unsigned int i;
1767
1768         dpu_enc = to_dpu_encoder_virt(drm_enc);
1769
1770         trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
1771
1772         /* prepare for next kickoff, may include waiting on previous kickoff */
1773         DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1774         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1775                 phys = dpu_enc->phys_encs[i];
1776                 if (phys) {
1777                         if (phys->ops.prepare_for_kickoff)
1778                                 phys->ops.prepare_for_kickoff(phys);
1779                         if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1780                                 needs_hw_reset = true;
1781                 }
1782         }
1783         DPU_ATRACE_END("enc_prepare_for_kickoff");
1784
1785         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1786
1787         /* if any phys needs reset, reset all phys, in-order */
1788         if (needs_hw_reset) {
1789                 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1790                 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1791                         dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1792                 }
1793         }
1794 }
1795
1796 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
1797 {
1798         struct dpu_encoder_virt *dpu_enc;
1799         struct dpu_encoder_phys *phys;
1800         ktime_t wakeup_time;
1801         unsigned long timeout_ms;
1802         unsigned int i;
1803
1804         DPU_ATRACE_BEGIN("encoder_kickoff");
1805         dpu_enc = to_dpu_encoder_virt(drm_enc);
1806
1807         trace_dpu_enc_kickoff(DRMID(drm_enc));
1808
1809         timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
1810                         drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
1811
1812         atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
1813         mod_timer(&dpu_enc->frame_done_timer,
1814                         jiffies + msecs_to_jiffies(timeout_ms));
1815
1816         /* All phys encs are ready to go, trigger the kickoff */
1817         _dpu_encoder_kickoff_phys(dpu_enc);
1818
1819         /* allow phys encs to handle any post-kickoff business */
1820         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1821                 phys = dpu_enc->phys_encs[i];
1822                 if (phys && phys->ops.handle_post_kickoff)
1823                         phys->ops.handle_post_kickoff(phys);
1824         }
1825
1826         if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1827                         !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) {
1828                 trace_dpu_enc_early_kickoff(DRMID(drm_enc),
1829                                             ktime_to_ms(wakeup_time));
1830                 mod_timer(&dpu_enc->vsync_event_timer,
1831                                 nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1832         }
1833
1834         DPU_ATRACE_END("encoder_kickoff");
1835 }
1836
1837 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
1838 {
1839         struct dpu_encoder_virt *dpu_enc;
1840         struct dpu_encoder_phys *phys;
1841         int i;
1842
1843         if (!drm_enc) {
1844                 DPU_ERROR("invalid encoder\n");
1845                 return;
1846         }
1847         dpu_enc = to_dpu_encoder_virt(drm_enc);
1848
1849         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1850                 phys = dpu_enc->phys_encs[i];
1851                 if (phys && phys->ops.prepare_commit)
1852                         phys->ops.prepare_commit(phys);
1853         }
1854 }
1855
1856 #ifdef CONFIG_DEBUG_FS
1857 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
1858 {
1859         struct dpu_encoder_virt *dpu_enc = s->private;
1860         int i;
1861
1862         mutex_lock(&dpu_enc->enc_lock);
1863         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1864                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1865
1866                 if (!phys)
1867                         continue;
1868
1869                 seq_printf(s, "intf:%d    vsync:%8d     underrun:%8d    ",
1870                                 phys->intf_idx - INTF_0,
1871                                 atomic_read(&phys->vsync_cnt),
1872                                 atomic_read(&phys->underrun_cnt));
1873
1874                 switch (phys->intf_mode) {
1875                 case INTF_MODE_VIDEO:
1876                         seq_puts(s, "mode: video\n");
1877                         break;
1878                 case INTF_MODE_CMD:
1879                         seq_puts(s, "mode: command\n");
1880                         break;
1881                 default:
1882                         seq_puts(s, "mode: ???\n");
1883                         break;
1884                 }
1885         }
1886         mutex_unlock(&dpu_enc->enc_lock);
1887
1888         return 0;
1889 }
1890
1891 static int _dpu_encoder_debugfs_status_open(struct inode *inode,
1892                 struct file *file)
1893 {
1894         return single_open(file, _dpu_encoder_status_show, inode->i_private);
1895 }
1896
1897 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1898 {
1899         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1900         int i;
1901
1902         static const struct file_operations debugfs_status_fops = {
1903                 .open =         _dpu_encoder_debugfs_status_open,
1904                 .read =         seq_read,
1905                 .llseek =       seq_lseek,
1906                 .release =      single_release,
1907         };
1908
1909         char name[DPU_NAME_SIZE];
1910
1911         if (!drm_enc->dev) {
1912                 DPU_ERROR("invalid encoder or kms\n");
1913                 return -EINVAL;
1914         }
1915
1916         snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id);
1917
1918         /* create overall sub-directory for the encoder */
1919         dpu_enc->debugfs_root = debugfs_create_dir(name,
1920                         drm_enc->dev->primary->debugfs_root);
1921
1922         /* don't error check these */
1923         debugfs_create_file("status", 0600,
1924                 dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops);
1925
1926         for (i = 0; i < dpu_enc->num_phys_encs; i++)
1927                 if (dpu_enc->phys_encs[i] &&
1928                                 dpu_enc->phys_encs[i]->ops.late_register)
1929                         dpu_enc->phys_encs[i]->ops.late_register(
1930                                         dpu_enc->phys_encs[i],
1931                                         dpu_enc->debugfs_root);
1932
1933         return 0;
1934 }
1935 #else
1936 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1937 {
1938         return 0;
1939 }
1940 #endif
1941
1942 static int dpu_encoder_late_register(struct drm_encoder *encoder)
1943 {
1944         return _dpu_encoder_init_debugfs(encoder);
1945 }
1946
1947 static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
1948 {
1949         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
1950
1951         debugfs_remove_recursive(dpu_enc->debugfs_root);
1952 }
1953
1954 static int dpu_encoder_virt_add_phys_encs(
1955                 u32 display_caps,
1956                 struct dpu_encoder_virt *dpu_enc,
1957                 struct dpu_enc_phys_init_params *params)
1958 {
1959         struct dpu_encoder_phys *enc = NULL;
1960
1961         DPU_DEBUG_ENC(dpu_enc, "\n");
1962
1963         /*
1964          * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
1965          * in this function, check up-front.
1966          */
1967         if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
1968                         ARRAY_SIZE(dpu_enc->phys_encs)) {
1969                 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
1970                           dpu_enc->num_phys_encs);
1971                 return -EINVAL;
1972         }
1973
1974         if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
1975                 enc = dpu_encoder_phys_vid_init(params);
1976
1977                 if (IS_ERR_OR_NULL(enc)) {
1978                         DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
1979                                 PTR_ERR(enc));
1980                         return enc == 0 ? -EINVAL : PTR_ERR(enc);
1981                 }
1982
1983                 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
1984                 ++dpu_enc->num_phys_encs;
1985         }
1986
1987         if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
1988                 enc = dpu_encoder_phys_cmd_init(params);
1989
1990                 if (IS_ERR_OR_NULL(enc)) {
1991                         DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
1992                                 PTR_ERR(enc));
1993                         return enc == 0 ? -EINVAL : PTR_ERR(enc);
1994                 }
1995
1996                 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
1997                 ++dpu_enc->num_phys_encs;
1998         }
1999
2000         if (params->split_role == ENC_ROLE_SLAVE)
2001                 dpu_enc->cur_slave = enc;
2002         else
2003                 dpu_enc->cur_master = enc;
2004
2005         return 0;
2006 }
2007
2008 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = {
2009         .handle_vblank_virt = dpu_encoder_vblank_callback,
2010         .handle_underrun_virt = dpu_encoder_underrun_callback,
2011         .handle_frame_done = dpu_encoder_frame_done_callback,
2012 };
2013
2014 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2015                                  struct dpu_kms *dpu_kms,
2016                                  struct msm_display_info *disp_info)
2017 {
2018         int ret = 0;
2019         int i = 0;
2020         enum dpu_intf_type intf_type;
2021         struct dpu_enc_phys_init_params phys_params;
2022
2023         if (!dpu_enc) {
2024                 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != 0);
2025                 return -EINVAL;
2026         }
2027
2028         dpu_enc->cur_master = NULL;
2029
2030         memset(&phys_params, 0, sizeof(phys_params));
2031         phys_params.dpu_kms = dpu_kms;
2032         phys_params.parent = &dpu_enc->base;
2033         phys_params.parent_ops = &dpu_encoder_parent_ops;
2034         phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2035
2036         DPU_DEBUG("\n");
2037
2038         switch (disp_info->intf_type) {
2039         case DRM_MODE_ENCODER_DSI:
2040                 intf_type = INTF_DSI;
2041                 break;
2042         default:
2043                 DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n");
2044                 return -EINVAL;
2045         }
2046
2047         WARN_ON(disp_info->num_of_h_tiles < 1);
2048
2049         DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2050
2051         if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
2052             (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
2053                 dpu_enc->idle_pc_supported =
2054                                 dpu_kms->catalog->caps->has_idle_pc;
2055
2056         mutex_lock(&dpu_enc->enc_lock);
2057         for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2058                 /*
2059                  * Left-most tile is at index 0, content is controller id
2060                  * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2061                  * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2062                  */
2063                 u32 controller_id = disp_info->h_tile_instance[i];
2064
2065                 if (disp_info->num_of_h_tiles > 1) {
2066                         if (i == 0)
2067                                 phys_params.split_role = ENC_ROLE_MASTER;
2068                         else
2069                                 phys_params.split_role = ENC_ROLE_SLAVE;
2070                 } else {
2071                         phys_params.split_role = ENC_ROLE_SOLO;
2072                 }
2073
2074                 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2075                                 i, controller_id, phys_params.split_role);
2076
2077                 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
2078                                                                                                         intf_type,
2079                                                                                                         controller_id);
2080                 if (phys_params.intf_idx == INTF_MAX) {
2081                         DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n",
2082                                                   intf_type, controller_id);
2083                         ret = -EINVAL;
2084                 }
2085
2086                 if (!ret) {
2087                         ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities,
2088                                                                                                  dpu_enc,
2089                                                                                                  &phys_params);
2090                         if (ret)
2091                                 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2092                 }
2093         }
2094
2095         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2096                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2097
2098                 if (phys) {
2099                         atomic_set(&phys->vsync_cnt, 0);
2100                         atomic_set(&phys->underrun_cnt, 0);
2101                 }
2102         }
2103         mutex_unlock(&dpu_enc->enc_lock);
2104
2105         return ret;
2106 }
2107
2108 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2109 {
2110         struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2111                         frame_done_timer);
2112         struct drm_encoder *drm_enc = &dpu_enc->base;
2113         u32 event;
2114
2115         if (!drm_enc->dev) {
2116                 DPU_ERROR("invalid parameters\n");
2117                 return;
2118         }
2119
2120         if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
2121                 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2122                               DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2123                 return;
2124         } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2125                 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2126                 return;
2127         }
2128
2129         DPU_ERROR_ENC(dpu_enc, "frame done timeout\n");
2130
2131         event = DPU_ENCODER_FRAME_EVENT_ERROR;
2132         trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2133         dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
2134 }
2135
2136 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2137         .mode_set = dpu_encoder_virt_mode_set,
2138         .disable = dpu_encoder_virt_disable,
2139         .enable = dpu_kms_encoder_enable,
2140         .atomic_check = dpu_encoder_virt_atomic_check,
2141
2142         /* This is called by dpu_kms_encoder_enable */
2143         .commit = dpu_encoder_virt_enable,
2144 };
2145
2146 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2147                 .destroy = dpu_encoder_destroy,
2148                 .late_register = dpu_encoder_late_register,
2149                 .early_unregister = dpu_encoder_early_unregister,
2150 };
2151
2152 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
2153                 struct msm_display_info *disp_info)
2154 {
2155         struct msm_drm_private *priv = dev->dev_private;
2156         struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2157         struct drm_encoder *drm_enc = NULL;
2158         struct dpu_encoder_virt *dpu_enc = NULL;
2159         int ret = 0;
2160
2161         dpu_enc = to_dpu_encoder_virt(enc);
2162
2163         mutex_init(&dpu_enc->enc_lock);
2164         ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2165         if (ret)
2166                 goto fail;
2167
2168         atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2169         timer_setup(&dpu_enc->frame_done_timer,
2170                         dpu_encoder_frame_done_timeout, 0);
2171
2172         if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
2173                 timer_setup(&dpu_enc->vsync_event_timer,
2174                                 dpu_encoder_vsync_event_handler,
2175                                 0);
2176
2177
2178         mutex_init(&dpu_enc->rc_lock);
2179         INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2180                         dpu_encoder_off_work);
2181         dpu_enc->idle_timeout = IDLE_TIMEOUT;
2182
2183         kthread_init_work(&dpu_enc->vsync_event_work,
2184                         dpu_encoder_vsync_event_work_handler);
2185
2186         memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2187
2188         DPU_DEBUG_ENC(dpu_enc, "created\n");
2189
2190         return ret;
2191
2192 fail:
2193         DPU_ERROR("failed to create encoder\n");
2194         if (drm_enc)
2195                 dpu_encoder_destroy(drm_enc);
2196
2197         return ret;
2198
2199
2200 }
2201
2202 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2203                 int drm_enc_mode)
2204 {
2205         struct dpu_encoder_virt *dpu_enc = NULL;
2206         int rc = 0;
2207
2208         dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL);
2209         if (!dpu_enc)
2210                 return ERR_PTR(ENOMEM);
2211
2212         rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs,
2213                         drm_enc_mode, NULL);
2214         if (rc) {
2215                 devm_kfree(dev->dev, dpu_enc);
2216                 return ERR_PTR(rc);
2217         }
2218
2219         drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2220
2221         spin_lock_init(&dpu_enc->enc_spinlock);
2222         dpu_enc->enabled = false;
2223
2224         return &dpu_enc->base;
2225 }
2226
2227 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
2228         enum msm_event_wait event)
2229 {
2230         int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL;
2231         struct dpu_encoder_virt *dpu_enc = NULL;
2232         int i, ret = 0;
2233
2234         if (!drm_enc) {
2235                 DPU_ERROR("invalid encoder\n");
2236                 return -EINVAL;
2237         }
2238         dpu_enc = to_dpu_encoder_virt(drm_enc);
2239         DPU_DEBUG_ENC(dpu_enc, "\n");
2240
2241         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2242                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2243                 if (!phys)
2244                         continue;
2245
2246                 switch (event) {
2247                 case MSM_ENC_COMMIT_DONE:
2248                         fn_wait = phys->ops.wait_for_commit_done;
2249                         break;
2250                 case MSM_ENC_TX_COMPLETE:
2251                         fn_wait = phys->ops.wait_for_tx_complete;
2252                         break;
2253                 case MSM_ENC_VBLANK:
2254                         fn_wait = phys->ops.wait_for_vblank;
2255                         break;
2256                 default:
2257                         DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
2258                                         event);
2259                         return -EINVAL;
2260                 };
2261
2262                 if (fn_wait) {
2263                         DPU_ATRACE_BEGIN("wait_for_completion_event");
2264                         ret = fn_wait(phys);
2265                         DPU_ATRACE_END("wait_for_completion_event");
2266                         if (ret)
2267                                 return ret;
2268                 }
2269         }
2270
2271         return ret;
2272 }
2273
2274 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2275 {
2276         struct dpu_encoder_virt *dpu_enc = NULL;
2277         int i;
2278
2279         if (!encoder) {
2280                 DPU_ERROR("invalid encoder\n");
2281                 return INTF_MODE_NONE;
2282         }
2283         dpu_enc = to_dpu_encoder_virt(encoder);
2284
2285         if (dpu_enc->cur_master)
2286                 return dpu_enc->cur_master->intf_mode;
2287
2288         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2289                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2290
2291                 if (phys)
2292                         return phys->intf_mode;
2293         }
2294
2295         return INTF_MODE_NONE;
2296 }