drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  */
   7
   8 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
   9 #include <linux/debugfs.h>
  10 #include <linux/kthread.h>
  11 #include <linux/seq_file.h>
  12
  13 #include <drm/drm_crtc.h>
  14 #include <drm/drm_file.h>
  15 #include <drm/drm_probe_helper.h>
  16
  17 #include "msm_drv.h"
  18 #include "dpu_kms.h"
  19 #include "dpu_hwio.h"
  20 #include "dpu_hw_catalog.h"
  21 #include "dpu_hw_intf.h"
  22 #include "dpu_hw_ctl.h"
  23 #include "dpu_formats.h"
  24 #include "dpu_encoder_phys.h"
  25 #include "dpu_crtc.h"
  26 #include "dpu_trace.h"
  27 #include "dpu_core_irq.h"
  28
  29 #define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\
  30                 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  31
  32 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
  33                 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  34
  35 #define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\
  36                 (p) ? (p)->parent->base.id : -1, \
  37                 (p) ? (p)->intf_idx - INTF_0 : -1, \
  38                 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  39                 ##__VA_ARGS__)
  40
  41 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\
  42                 (p) ? (p)->parent->base.id : -1, \
  43                 (p) ? (p)->intf_idx - INTF_0 : -1, \
  44                 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  45                 ##__VA_ARGS__)
  46
  47 /*
  48  * Two to anticipate panels that can do cmd/vid dynamic switching
  49  * plan is to create all possible physical encoder types, and switch between
  50  * them at runtime
  51  */
  52 #define NUM_PHYS_ENCODER_TYPES 2
  53
  54 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
  55         (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
  56
  57 #define MAX_CHANNELS_PER_ENC 2
  58
  59 #define IDLE_SHORT_TIMEOUT      1
  60
  61 #define MAX_VDISPLAY_SPLIT 1080
  62
  63 /* timeout in frames waiting for frame done */
  64 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
  65
  66 /**
  67  * enum dpu_enc_rc_events - events for resource control state machine
  68  * @DPU_ENC_RC_EVENT_KICKOFF:
  69  *      This event happens at NORMAL priority.
  70  *      Event that signals the start of the transfer. When this event is
  71  *      received, enable MDP/DSI core clocks. Regardless of the previous
  72  *      state, the resource should be in ON state at the end of this event.
  73  * @DPU_ENC_RC_EVENT_FRAME_DONE:
  74  *      This event happens at INTERRUPT level.
  75  *      Event signals the end of the data transfer after the PP FRAME_DONE
  76  *      event. At the end of this event, a delayed work is scheduled to go to
  77  *      IDLE_PC state after IDLE_TIMEOUT time.
  78  * @DPU_ENC_RC_EVENT_PRE_STOP:
  79  *      This event happens at NORMAL priority.
  80  *      This event, when received during the ON state, leave the RC STATE
  81  *      in the PRE_OFF state. It should be followed by the STOP event as
  82  *      part of encoder disable.
  83  *      If received during IDLE or OFF states, it will do nothing.
  84  * @DPU_ENC_RC_EVENT_STOP:
  85  *      This event happens at NORMAL priority.
  86  *      When this event is received, disable all the MDP/DSI core clocks, and
  87  *      disable IRQs. It should be called from the PRE_OFF or IDLE states.
  88  *      IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  89  *      PRE_OFF is expected when PRE_STOP was executed during the ON state.
  90  *      Resource state should be in OFF at the end of the event.
  91  * @DPU_ENC_RC_EVENT_ENTER_IDLE:
  92  *      This event happens at NORMAL priority from a work item.
  93  *      Event signals that there were no frame updates for IDLE_TIMEOUT time.
  94  *      This would disable MDP/DSI core clocks and change the resource state
  95  *      to IDLE.
  96  */
  97 enum dpu_enc_rc_events {
  98         DPU_ENC_RC_EVENT_KICKOFF = 1,
  99         DPU_ENC_RC_EVENT_FRAME_DONE,
 100         DPU_ENC_RC_EVENT_PRE_STOP,
 101         DPU_ENC_RC_EVENT_STOP,
 102         DPU_ENC_RC_EVENT_ENTER_IDLE
 103 };
 104
 105 /*
 106  * enum dpu_enc_rc_states - states that the resource control maintains
 107  * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
 108  * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
 109  * @DPU_ENC_RC_STATE_ON: Resource is in ON state
 110  * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
 111  * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
 112  */
 113 enum dpu_enc_rc_states {
 114         DPU_ENC_RC_STATE_OFF,
 115         DPU_ENC_RC_STATE_PRE_OFF,
 116         DPU_ENC_RC_STATE_ON,
 117         DPU_ENC_RC_STATE_IDLE
 118 };
 119
 120 /**
 121  * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
 122  *      encoders. Virtual encoder manages one "logical" display. Physical
 123  *      encoders manage one intf block, tied to a specific panel/sub-panel.
 124  *      Virtual encoder defers as much as possible to the physical encoders.
 125  *      Virtual encoder registers itself with the DRM Framework as the encoder.
 126  * @base:               drm_encoder base class for registration with DRM
 127  * @enc_spinlock:       Virtual-Encoder-Wide Spin Lock for IRQ purposes
 128  * @bus_scaling_client: Client handle to the bus scaling interface
 129  * @enabled:            True if the encoder is active, protected by enc_lock
 130  * @num_phys_encs:      Actual number of physical encoders contained.
 131  * @phys_encs:          Container of physical encoders managed.
 132  * @cur_master:         Pointer to the current master in this mode. Optimization
 133  *                      Only valid after enable. Cleared as disable.
 134  * @hw_pp               Handle to the pingpong blocks used for the display. No.
 135  *                      pingpong blocks can be different than num_phys_encs.
 136  * @intfs_swapped       Whether or not the phys_enc interfaces have been swapped
 137  *                      for partial update right-only cases, such as pingpong
 138  *                      split where virtual pingpong does not generate IRQs
 139  * @crtc:               Pointer to the currently assigned crtc. Normally you
 140  *                      would use crtc->state->encoder_mask to determine the
 141  *                      link between encoder/crtc. However in this case we need
 142  *                      to track crtc in the disable() hook which is called
 143  *                      _after_ encoder_mask is cleared.
 144  * @crtc_kickoff_cb:            Callback into CRTC that will flush & start
 145  *                              all CTL paths
 146  * @crtc_kickoff_cb_data:       Opaque user data given to crtc_kickoff_cb
 147  * @debugfs_root:               Debug file system root file node
 148  * @enc_lock:                   Lock around physical encoder
 149  *                              create/destroy/enable/disable
 150  * @frame_busy_mask:            Bitmask tracking which phys_enc we are still
 151  *                              busy processing current command.
 152  *                              Bit0 = phys_encs[0] etc.
 153  * @crtc_frame_event_cb:        callback handler for frame event
 154  * @crtc_frame_event_cb_data:   callback handler private data
 155  * @frame_done_timeout_ms:      frame done timeout in ms
 156  * @frame_done_timer:           watchdog timer for frame done event
 157  * @vsync_event_timer:          vsync timer
 158  * @disp_info:                  local copy of msm_display_info struct
 159  * @idle_pc_supported:          indicate if idle power collaps is supported
 160  * @rc_lock:                    resource control mutex lock to protect
 161  *                              virt encoder over various state changes
 162  * @rc_state:                   resource controller state
 163  * @delayed_off_work:           delayed worker to schedule disabling of
 164  *                              clks and resources after IDLE_TIMEOUT time.
 165  * @vsync_event_work:           worker to handle vsync event for autorefresh
 166  * @topology:                   topology of the display
 167  * @mode_set_complete:          flag to indicate modeset completion
 168  * @idle_timeout:               idle timeout duration in milliseconds
 169  */
 170 struct dpu_encoder_virt {
 171         struct drm_encoder base;
 172         spinlock_t enc_spinlock;
 173         uint32_t bus_scaling_client;
 174
 175         bool enabled;
 176
 177         unsigned int num_phys_encs;
 178         struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
 179         struct dpu_encoder_phys *cur_master;
 180         struct dpu_encoder_phys *cur_slave;
 181         struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
 182
 183         bool intfs_swapped;
 184
 185         struct drm_crtc *crtc;
 186
 187         struct dentry *debugfs_root;
 188         struct mutex enc_lock;
 189         DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
 190         void (*crtc_frame_event_cb)(void *, u32 event);
 191         void *crtc_frame_event_cb_data;
 192
 193         atomic_t frame_done_timeout_ms;
 194         struct timer_list frame_done_timer;
 195         struct timer_list vsync_event_timer;
 196
 197         struct msm_display_info disp_info;
 198
 199         bool idle_pc_supported;
 200         struct mutex rc_lock;
 201         enum dpu_enc_rc_states rc_state;
 202         struct delayed_work delayed_off_work;
 203         struct kthread_work vsync_event_work;
 204         struct msm_display_topology topology;
 205         bool mode_set_complete;
 206
 207         u32 idle_timeout;
 208 };
 209
 210 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
 211
 212 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
 213                 enum dpu_intr_idx intr_idx)
 214 {
 215         DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
 216                   DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
 217                   phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
 218
 219         if (phys_enc->parent_ops->handle_frame_done)
 220                 phys_enc->parent_ops->handle_frame_done(
 221                                 phys_enc->parent, phys_enc,
 222                                 DPU_ENCODER_FRAME_EVENT_ERROR);
 223 }
 224
 225 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
 226                 int32_t hw_id, struct dpu_encoder_wait_info *info);
 227
 228 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
 229                 enum dpu_intr_idx intr_idx,
 230                 struct dpu_encoder_wait_info *wait_info)
 231 {
 232         struct dpu_encoder_irq *irq;
 233         u32 irq_status;
 234         int ret;
 235
 236         if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
 237                 DPU_ERROR("invalid params\n");
 238                 return -EINVAL;
 239         }
 240         irq = &phys_enc->irq[intr_idx];
 241
 242         /* note: do master / slave checking outside */
 243
 244         /* return EWOULDBLOCK since we know the wait isn't necessary */
 245         if (phys_enc->enable_state == DPU_ENC_DISABLED) {
 246                 DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
 247                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 248                           irq->irq_idx);
 249                 return -EWOULDBLOCK;
 250         }
 251
 252         if (irq->irq_idx < 0) {
 253                 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
 254                               DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 255                               irq->name);
 256                 return 0;
 257         }
 258
 259         DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
 260                       DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 261                       irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
 262                       atomic_read(wait_info->atomic_cnt));
 263
 264         ret = dpu_encoder_helper_wait_event_timeout(
 265                         DRMID(phys_enc->parent),
 266                         irq->hw_idx,
 267                         wait_info);
 268
 269         if (ret <= 0) {
 270                 irq_status = dpu_core_irq_read(phys_enc->dpu_kms,
 271                                 irq->irq_idx, true);
 272                 if (irq_status) {
 273                         unsigned long flags;
 274
 275                         DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
 276                                       "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
 277                                       DRMID(phys_enc->parent), intr_idx,
 278                                       irq->hw_idx, irq->irq_idx,
 279                                       phys_enc->hw_pp->idx - PINGPONG_0,
 280                                       atomic_read(wait_info->atomic_cnt));
 281                         local_irq_save(flags);
 282                         irq->cb.func(phys_enc, irq->irq_idx);
 283                         local_irq_restore(flags);
 284                         ret = 0;
 285                 } else {
 286                         ret = -ETIMEDOUT;
 287                         DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
 288                                       "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
 289                                       DRMID(phys_enc->parent), intr_idx,
 290                                       irq->hw_idx, irq->irq_idx,
 291                                       phys_enc->hw_pp->idx - PINGPONG_0,
 292                                       atomic_read(wait_info->atomic_cnt));
 293                 }
 294         } else {
 295                 ret = 0;
 296                 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
 297                         intr_idx, irq->hw_idx, irq->irq_idx,
 298                         phys_enc->hw_pp->idx - PINGPONG_0,
 299                         atomic_read(wait_info->atomic_cnt));
 300         }
 301
 302         return ret;
 303 }
 304
 305 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
 306                 enum dpu_intr_idx intr_idx)
 307 {
 308         struct dpu_encoder_irq *irq;
 309         int ret = 0;
 310
 311         if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
 312                 DPU_ERROR("invalid params\n");
 313                 return -EINVAL;
 314         }
 315         irq = &phys_enc->irq[intr_idx];
 316
 317         if (irq->irq_idx >= 0) {
 318                 DPU_DEBUG_PHYS(phys_enc,
 319                                 "skipping already registered irq %s type %d\n",
 320                                 irq->name, irq->intr_type);
 321                 return 0;
 322         }
 323
 324         irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms,
 325                         irq->intr_type, irq->hw_idx);
 326         if (irq->irq_idx < 0) {
 327                 DPU_ERROR_PHYS(phys_enc,
 328                         "failed to lookup IRQ index for %s type:%d\n",
 329                         irq->name, irq->intr_type);
 330                 return -EINVAL;
 331         }
 332
 333         ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx,
 334                         &irq->cb);
 335         if (ret) {
 336                 DPU_ERROR_PHYS(phys_enc,
 337                         "failed to register IRQ callback for %s\n",
 338                         irq->name);
 339                 irq->irq_idx = -EINVAL;
 340                 return ret;
 341         }
 342
 343         ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
 344         if (ret) {
 345                 DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
 346                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 347                           irq->irq_idx);
 348                 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
 349                                 irq->irq_idx, &irq->cb);
 350                 irq->irq_idx = -EINVAL;
 351                 return ret;
 352         }
 353
 354         trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
 355                                 irq->hw_idx, irq->irq_idx);
 356
 357         return ret;
 358 }
 359
 360 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
 361                 enum dpu_intr_idx intr_idx)
 362 {
 363         struct dpu_encoder_irq *irq;
 364         int ret;
 365
 366         if (!phys_enc) {
 367                 DPU_ERROR("invalid encoder\n");
 368                 return -EINVAL;
 369         }
 370         irq = &phys_enc->irq[intr_idx];
 371
 372         /* silently skip irqs that weren't registered */
 373         if (irq->irq_idx < 0) {
 374                 DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
 375                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 376                           irq->irq_idx);
 377                 return 0;
 378         }
 379
 380         ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
 381         if (ret) {
 382                 DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
 383                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 384                           irq->irq_idx, ret);
 385         }
 386
 387         ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
 388                         &irq->cb);
 389         if (ret) {
 390                 DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
 391                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 392                           irq->irq_idx, ret);
 393         }
 394
 395         trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
 396                                              irq->hw_idx, irq->irq_idx);
 397
 398         irq->irq_idx = -EINVAL;
 399
 400         return 0;
 401 }
 402
 403 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
 404                                   struct dpu_encoder_hw_resources *hw_res)
 405 {
 406         struct dpu_encoder_virt *dpu_enc = NULL;
 407         int i = 0;
 408
 409         dpu_enc = to_dpu_encoder_virt(drm_enc);
 410         DPU_DEBUG_ENC(dpu_enc, "\n");
 411
 412         /* Query resources used by phys encs, expected to be without overlap */
 413         memset(hw_res, 0, sizeof(*hw_res));
 414
 415         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 416                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 417
 418                 if (phys && phys->ops.get_hw_resources)
 419                         phys->ops.get_hw_resources(phys, hw_res);
 420         }
 421 }
 422
 423 static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
 424 {
 425         struct dpu_encoder_virt *dpu_enc = NULL;
 426         int i = 0;
 427
 428         if (!drm_enc) {
 429                 DPU_ERROR("invalid encoder\n");
 430                 return;
 431         }
 432
 433         dpu_enc = to_dpu_encoder_virt(drm_enc);
 434         DPU_DEBUG_ENC(dpu_enc, "\n");
 435
 436         mutex_lock(&dpu_enc->enc_lock);
 437
 438         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 439                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 440
 441                 if (phys && phys->ops.destroy) {
 442                         phys->ops.destroy(phys);
 443                         --dpu_enc->num_phys_encs;
 444                         dpu_enc->phys_encs[i] = NULL;
 445                 }
 446         }
 447
 448         if (dpu_enc->num_phys_encs)
 449                 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n",
 450                                 dpu_enc->num_phys_encs);
 451         dpu_enc->num_phys_encs = 0;
 452         mutex_unlock(&dpu_enc->enc_lock);
 453
 454         drm_encoder_cleanup(drm_enc);
 455         mutex_destroy(&dpu_enc->enc_lock);
 456 }
 457
 458 void dpu_encoder_helper_split_config(
 459                 struct dpu_encoder_phys *phys_enc,
 460                 enum dpu_intf interface)
 461 {
 462         struct dpu_encoder_virt *dpu_enc;
 463         struct split_pipe_cfg cfg = { 0 };
 464         struct dpu_hw_mdp *hw_mdptop;
 465         struct msm_display_info *disp_info;
 466
 467         if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
 468                 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
 469                 return;
 470         }
 471
 472         dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
 473         hw_mdptop = phys_enc->hw_mdptop;
 474         disp_info = &dpu_enc->disp_info;
 475
 476         if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
 477                 return;
 478
 479         /**
 480          * disable split modes since encoder will be operating in as the only
 481          * encoder, either for the entire use case in the case of, for example,
 482          * single DSI, or for this frame in the case of left/right only partial
 483          * update.
 484          */
 485         if (phys_enc->split_role == ENC_ROLE_SOLO) {
 486                 if (hw_mdptop->ops.setup_split_pipe)
 487                         hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
 488                 return;
 489         }
 490
 491         cfg.en = true;
 492         cfg.mode = phys_enc->intf_mode;
 493         cfg.intf = interface;
 494
 495         if (cfg.en && phys_enc->ops.needs_single_flush &&
 496                         phys_enc->ops.needs_single_flush(phys_enc))
 497                 cfg.split_flush_en = true;
 498
 499         if (phys_enc->split_role == ENC_ROLE_MASTER) {
 500                 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
 501
 502                 if (hw_mdptop->ops.setup_split_pipe)
 503                         hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
 504         }
 505 }
 506
 507 static void _dpu_encoder_adjust_mode(struct drm_connector *connector,
 508                 struct drm_display_mode *adj_mode)
 509 {
 510         struct drm_display_mode *cur_mode;
 511
 512         if (!connector || !adj_mode)
 513                 return;
 514
 515         list_for_each_entry(cur_mode, &connector->modes, head) {
 516                 if (cur_mode->vdisplay == adj_mode->vdisplay &&
 517                     cur_mode->hdisplay == adj_mode->hdisplay &&
 518                     drm_mode_vrefresh(cur_mode) == drm_mode_vrefresh(adj_mode)) {
 519                         adj_mode->private_flags |= cur_mode->private_flags;
 520                 }
 521         }
 522 }
 523
 524 static struct msm_display_topology dpu_encoder_get_topology(
 525                         struct dpu_encoder_virt *dpu_enc,
 526                         struct dpu_kms *dpu_kms,
 527                         struct drm_display_mode *mode)
 528 {
 529         struct msm_display_topology topology;
 530         int i, intf_count = 0;
 531
 532         for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
 533                 if (dpu_enc->phys_encs[i])
 534                         intf_count++;
 535
 536         /* User split topology for width > 1080 */
 537         topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
 538         topology.num_enc = 0;
 539         topology.num_intf = intf_count;
 540
 541         return topology;
 542 }
 543 static int dpu_encoder_virt_atomic_check(
 544                 struct drm_encoder *drm_enc,
 545                 struct drm_crtc_state *crtc_state,
 546                 struct drm_connector_state *conn_state)
 547 {
 548         struct dpu_encoder_virt *dpu_enc;
 549         struct msm_drm_private *priv;
 550         struct dpu_kms *dpu_kms;
 551         const struct drm_display_mode *mode;
 552         struct drm_display_mode *adj_mode;
 553         struct msm_display_topology topology;
 554         int i = 0;
 555         int ret = 0;
 556
 557         if (!drm_enc || !crtc_state || !conn_state) {
 558                 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
 559                                 drm_enc != 0, crtc_state != 0, conn_state != 0);
 560                 return -EINVAL;
 561         }
 562
 563         dpu_enc = to_dpu_encoder_virt(drm_enc);
 564         DPU_DEBUG_ENC(dpu_enc, "\n");
 565
 566         priv = drm_enc->dev->dev_private;
 567         dpu_kms = to_dpu_kms(priv->kms);
 568         mode = &crtc_state->mode;
 569         adj_mode = &crtc_state->adjusted_mode;
 570         trace_dpu_enc_atomic_check(DRMID(drm_enc));
 571
 572         /*
 573          * display drivers may populate private fields of the drm display mode
 574          * structure while registering possible modes of a connector with DRM.
 575          * These private fields are not populated back while DRM invokes
 576          * the mode_set callbacks. This module retrieves and populates the
 577          * private fields of the given mode.
 578          */
 579         _dpu_encoder_adjust_mode(conn_state->connector, adj_mode);
 580
 581         /* perform atomic check on the first physical encoder (master) */
 582         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 583                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 584
 585                 if (phys && phys->ops.atomic_check)
 586                         ret = phys->ops.atomic_check(phys, crtc_state,
 587                                         conn_state);
 588                 else if (phys && phys->ops.mode_fixup)
 589                         if (!phys->ops.mode_fixup(phys, mode, adj_mode))
 590                                 ret = -EINVAL;
 591
 592                 if (ret) {
 593                         DPU_ERROR_ENC(dpu_enc,
 594                                         "mode unsupported, phys idx %d\n", i);
 595                         break;
 596                 }
 597         }
 598
 599         topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
 600
 601         /* Reserve dynamic resources now. Indicating AtomicTest phase */
 602         if (!ret) {
 603                 /*
 604                  * Avoid reserving resources when mode set is pending. Topology
 605                  * info may not be available to complete reservation.
 606                  */
 607                 if (drm_atomic_crtc_needs_modeset(crtc_state)
 608                                 && dpu_enc->mode_set_complete) {
 609                         ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
 610                                              topology, true);
 611                         dpu_enc->mode_set_complete = false;
 612                 }
 613         }
 614
 615         trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags,
 616                         adj_mode->private_flags);
 617
 618         return ret;
 619 }
 620
 621 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
 622                         struct msm_display_info *disp_info)
 623 {
 624         struct dpu_vsync_source_cfg vsync_cfg = { 0 };
 625         struct msm_drm_private *priv;
 626         struct dpu_kms *dpu_kms;
 627         struct dpu_hw_mdp *hw_mdptop;
 628         struct drm_encoder *drm_enc;
 629         int i;
 630
 631         if (!dpu_enc || !disp_info) {
 632                 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
 633                                         dpu_enc != NULL, disp_info != NULL);
 634                 return;
 635         } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
 636                 DPU_ERROR("invalid num phys enc %d/%d\n",
 637                                 dpu_enc->num_phys_encs,
 638                                 (int) ARRAY_SIZE(dpu_enc->hw_pp));
 639                 return;
 640         }
 641
 642         drm_enc = &dpu_enc->base;
 643         /* this pointers are checked in virt_enable_helper */
 644         priv = drm_enc->dev->dev_private;
 645
 646         dpu_kms = to_dpu_kms(priv->kms);
 647         hw_mdptop = dpu_kms->hw_mdp;
 648         if (!hw_mdptop) {
 649                 DPU_ERROR("invalid mdptop\n");
 650                 return;
 651         }
 652
 653         if (hw_mdptop->ops.setup_vsync_source &&
 654                         disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
 655                 for (i = 0; i < dpu_enc->num_phys_encs; i++)
 656                         vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
 657
 658                 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
 659                 if (disp_info->is_te_using_watchdog_timer)
 660                         vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
 661                 else
 662                         vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
 663
 664                 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
 665         }
 666 }
 667
 668 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
 669 {
 670         struct dpu_encoder_virt *dpu_enc;
 671         int i;
 672
 673         if (!drm_enc) {
 674                 DPU_ERROR("invalid encoder\n");
 675                 return;
 676         }
 677
 678         dpu_enc = to_dpu_encoder_virt(drm_enc);
 679
 680         DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
 681         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 682                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 683
 684                 if (phys && phys->ops.irq_control)
 685                         phys->ops.irq_control(phys, enable);
 686         }
 687
 688 }
 689
 690 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
 691                 bool enable)
 692 {
 693         struct msm_drm_private *priv;
 694         struct dpu_kms *dpu_kms;
 695         struct dpu_encoder_virt *dpu_enc;
 696
 697         dpu_enc = to_dpu_encoder_virt(drm_enc);
 698         priv = drm_enc->dev->dev_private;
 699         dpu_kms = to_dpu_kms(priv->kms);
 700
 701         trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
 702
 703         if (!dpu_enc->cur_master) {
 704                 DPU_ERROR("encoder master not set\n");
 705                 return;
 706         }
 707
 708         if (enable) {
 709                 /* enable DPU core clks */
 710                 pm_runtime_get_sync(&dpu_kms->pdev->dev);
 711
 712                 /* enable all the irq */
 713                 _dpu_encoder_irq_control(drm_enc, true);
 714
 715         } else {
 716                 /* disable all the irq */
 717                 _dpu_encoder_irq_control(drm_enc, false);
 718
 719                 /* disable DPU core clks */
 720                 pm_runtime_put_sync(&dpu_kms->pdev->dev);
 721         }
 722
 723 }
 724
 725 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 726                 u32 sw_event)
 727 {
 728         struct dpu_encoder_virt *dpu_enc;
 729         struct msm_drm_private *priv;
 730         bool is_vid_mode = false;
 731
 732         if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
 733                 DPU_ERROR("invalid parameters\n");
 734                 return -EINVAL;
 735         }
 736         dpu_enc = to_dpu_encoder_virt(drm_enc);
 737         priv = drm_enc->dev->dev_private;
 738         is_vid_mode = dpu_enc->disp_info.capabilities &
 739                                                 MSM_DISPLAY_CAP_VID_MODE;
 740
 741         /*
 742          * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
 743          * events and return early for other events (ie wb display).
 744          */
 745         if (!dpu_enc->idle_pc_supported &&
 746                         (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
 747                         sw_event != DPU_ENC_RC_EVENT_STOP &&
 748                         sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
 749                 return 0;
 750
 751         trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
 752                          dpu_enc->rc_state, "begin");
 753
 754         switch (sw_event) {
 755         case DPU_ENC_RC_EVENT_KICKOFF:
 756                 /* cancel delayed off work, if any */
 757                 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
 758                         DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
 759                                         sw_event);
 760
 761                 mutex_lock(&dpu_enc->rc_lock);
 762
 763                 /* return if the resource control is already in ON state */
 764                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
 765                         DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n",
 766                                       DRMID(drm_enc), sw_event);
 767                         mutex_unlock(&dpu_enc->rc_lock);
 768                         return 0;
 769                 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
 770                                 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
 771                         DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n",
 772                                       DRMID(drm_enc), sw_event,
 773                                       dpu_enc->rc_state);
 774                         mutex_unlock(&dpu_enc->rc_lock);
 775                         return -EINVAL;
 776                 }
 777
 778                 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
 779                         _dpu_encoder_irq_control(drm_enc, true);
 780                 else
 781                         _dpu_encoder_resource_control_helper(drm_enc, true);
 782
 783                 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
 784
 785                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 786                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 787                                  "kickoff");
 788
 789                 mutex_unlock(&dpu_enc->rc_lock);
 790                 break;
 791
 792         case DPU_ENC_RC_EVENT_FRAME_DONE:
 793                 /*
 794                  * mutex lock is not used as this event happens at interrupt
 795                  * context. And locking is not required as, the other events
 796                  * like KICKOFF and STOP does a wait-for-idle before executing
 797                  * the resource_control
 798                  */
 799                 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
 800                         DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
 801                                       DRMID(drm_enc), sw_event,
 802                                       dpu_enc->rc_state);
 803                         return -EINVAL;
 804                 }
 805
 806                 /*
 807                  * schedule off work item only when there are no
 808                  * frames pending
 809                  */
 810                 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
 811                         DRM_DEBUG_KMS("id:%d skip schedule work\n",
 812                                       DRMID(drm_enc));
 813                         return 0;
 814                 }
 815
 816                 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
 817                                    msecs_to_jiffies(dpu_enc->idle_timeout));
 818
 819                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 820                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 821                                  "frame done");
 822                 break;
 823
 824         case DPU_ENC_RC_EVENT_PRE_STOP:
 825                 /* cancel delayed off work, if any */
 826                 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
 827                         DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
 828                                         sw_event);
 829
 830                 mutex_lock(&dpu_enc->rc_lock);
 831
 832                 if (is_vid_mode &&
 833                           dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
 834                         _dpu_encoder_irq_control(drm_enc, true);
 835                 }
 836                 /* skip if is already OFF or IDLE, resources are off already */
 837                 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
 838                                 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
 839                         DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
 840                                       DRMID(drm_enc), sw_event,
 841                                       dpu_enc->rc_state);
 842                         mutex_unlock(&dpu_enc->rc_lock);
 843                         return 0;
 844                 }
 845
 846                 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
 847
 848                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 849                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 850                                  "pre stop");
 851
 852                 mutex_unlock(&dpu_enc->rc_lock);
 853                 break;
 854
 855         case DPU_ENC_RC_EVENT_STOP:
 856                 mutex_lock(&dpu_enc->rc_lock);
 857
 858                 /* return if the resource control is already in OFF state */
 859                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
 860                         DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
 861                                       DRMID(drm_enc), sw_event);
 862                         mutex_unlock(&dpu_enc->rc_lock);
 863                         return 0;
 864                 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
 865                         DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
 866                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 867                         mutex_unlock(&dpu_enc->rc_lock);
 868                         return -EINVAL;
 869                 }
 870
 871                 /**
 872                  * expect to arrive here only if in either idle state or pre-off
 873                  * and in IDLE state the resources are already disabled
 874                  */
 875                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
 876                         _dpu_encoder_resource_control_helper(drm_enc, false);
 877
 878                 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
 879
 880                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 881                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 882                                  "stop");
 883
 884                 mutex_unlock(&dpu_enc->rc_lock);
 885                 break;
 886
 887         case DPU_ENC_RC_EVENT_ENTER_IDLE:
 888                 mutex_lock(&dpu_enc->rc_lock);
 889
 890                 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
 891                         DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
 892                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 893                         mutex_unlock(&dpu_enc->rc_lock);
 894                         return 0;
 895                 }
 896
 897                 /*
 898                  * if we are in ON but a frame was just kicked off,
 899                  * ignore the IDLE event, it's probably a stale timer event
 900                  */
 901                 if (dpu_enc->frame_busy_mask[0]) {
 902                         DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
 903                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 904                         mutex_unlock(&dpu_enc->rc_lock);
 905                         return 0;
 906                 }
 907
 908                 if (is_vid_mode)
 909                         _dpu_encoder_irq_control(drm_enc, false);
 910                 else
 911                         _dpu_encoder_resource_control_helper(drm_enc, false);
 912
 913                 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
 914
 915                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 916                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 917                                  "idle");
 918
 919                 mutex_unlock(&dpu_enc->rc_lock);
 920                 break;
 921
 922         default:
 923                 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
 924                           sw_event);
 925                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 926                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 927                                  "error");
 928                 break;
 929         }
 930
 931         trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 932                          dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 933                          "end");
 934         return 0;
 935 }
 936
 937 static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 938                                       struct drm_display_mode *mode,
 939                                       struct drm_display_mode *adj_mode)
 940 {
 941         struct dpu_encoder_virt *dpu_enc;
 942         struct msm_drm_private *priv;
 943         struct dpu_kms *dpu_kms;
 944         struct list_head *connector_list;
 945         struct drm_connector *conn = NULL, *conn_iter;
 946         struct drm_crtc *drm_crtc;
 947         struct dpu_crtc_state *cstate;
 948         struct dpu_rm_hw_iter hw_iter;
 949         struct msm_display_topology topology;
 950         struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
 951         struct dpu_hw_mixer *hw_lm[MAX_CHANNELS_PER_ENC] = { NULL };
 952         int num_lm = 0, num_ctl = 0;
 953         int i, j, ret;
 954
 955         if (!drm_enc) {
 956                 DPU_ERROR("invalid encoder\n");
 957                 return;
 958         }
 959
 960         dpu_enc = to_dpu_encoder_virt(drm_enc);
 961         DPU_DEBUG_ENC(dpu_enc, "\n");
 962
 963         priv = drm_enc->dev->dev_private;
 964         dpu_kms = to_dpu_kms(priv->kms);
 965         connector_list = &dpu_kms->dev->mode_config.connector_list;
 966
 967         trace_dpu_enc_mode_set(DRMID(drm_enc));
 968
 969         list_for_each_entry(conn_iter, connector_list, head)
 970                 if (conn_iter->encoder == drm_enc)
 971                         conn = conn_iter;
 972
 973         if (!conn) {
 974                 DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n");
 975                 return;
 976         } else if (!conn->state) {
 977                 DPU_ERROR_ENC(dpu_enc, "invalid connector state\n");
 978                 return;
 979         }
 980
 981         drm_for_each_crtc(drm_crtc, drm_enc->dev)
 982                 if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc))
 983                         break;
 984
 985         topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
 986
 987         /* Reserve dynamic resources now. Indicating non-AtomicTest phase */
 988         ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, drm_crtc->state,
 989                              topology, false);
 990         if (ret) {
 991                 DPU_ERROR_ENC(dpu_enc,
 992                                 "failed to reserve hw resources, %d\n", ret);
 993                 return;
 994         }
 995
 996         dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_PINGPONG);
 997         for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
 998                 dpu_enc->hw_pp[i] = NULL;
 999                 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1000                         break;
1001                 dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) hw_iter.hw;
1002         }
1003
1004         dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
1005         for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1006                 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1007                         break;
1008                 hw_ctl[i] = (struct dpu_hw_ctl *)hw_iter.hw;
1009                 num_ctl++;
1010         }
1011
1012         dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_LM);
1013         for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1014                 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1015                         break;
1016                 hw_lm[i] = (struct dpu_hw_mixer *)hw_iter.hw;
1017                 num_lm++;
1018         }
1019
1020         cstate = to_dpu_crtc_state(drm_crtc->state);
1021
1022         for (i = 0; i < num_lm; i++) {
1023                 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1024
1025                 cstate->mixers[i].hw_lm = hw_lm[i];
1026                 cstate->mixers[i].lm_ctl = hw_ctl[ctl_idx];
1027         }
1028
1029         cstate->num_mixers = num_lm;
1030
1031         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1032                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1033
1034                 if (phys) {
1035                         if (!dpu_enc->hw_pp[i]) {
1036                                 DPU_ERROR_ENC(dpu_enc, "no pp block assigned"
1037                                              "at idx: %d\n", i);
1038                                 goto error;
1039                         }
1040
1041                         if (!hw_ctl[i]) {
1042                                 DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
1043                                              "at idx: %d\n", i);
1044                                 goto error;
1045                         }
1046
1047                         phys->hw_pp = dpu_enc->hw_pp[i];
1048                         phys->hw_ctl = hw_ctl[i];
1049
1050                         dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id,
1051                                             DPU_HW_BLK_INTF);
1052                         for (j = 0; j < MAX_CHANNELS_PER_ENC; j++) {
1053                                 struct dpu_hw_intf *hw_intf;
1054
1055                                 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1056                                         break;
1057
1058                                 hw_intf = (struct dpu_hw_intf *)hw_iter.hw;
1059                                 if (hw_intf->idx == phys->intf_idx)
1060                                         phys->hw_intf = hw_intf;
1061                         }
1062
1063                         if (!phys->hw_intf) {
1064                                 DPU_ERROR_ENC(dpu_enc,
1065                                               "no intf block assigned at idx: %d\n",
1066                                               i);
1067                                 goto error;
1068                         }
1069
1070                         phys->connector = conn->state->connector;
1071                         if (phys->ops.mode_set)
1072                                 phys->ops.mode_set(phys, mode, adj_mode);
1073                 }
1074         }
1075
1076         dpu_enc->mode_set_complete = true;
1077
1078 error:
1079         dpu_rm_release(&dpu_kms->rm, drm_enc);
1080 }
1081
1082 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1083 {
1084         struct dpu_encoder_virt *dpu_enc = NULL;
1085         struct msm_drm_private *priv;
1086         struct dpu_kms *dpu_kms;
1087
1088         if (!drm_enc || !drm_enc->dev) {
1089                 DPU_ERROR("invalid parameters\n");
1090                 return;
1091         }
1092
1093         priv = drm_enc->dev->dev_private;
1094         dpu_kms = to_dpu_kms(priv->kms);
1095
1096         dpu_enc = to_dpu_encoder_virt(drm_enc);
1097         if (!dpu_enc || !dpu_enc->cur_master) {
1098                 DPU_ERROR("invalid dpu encoder/master\n");
1099                 return;
1100         }
1101
1102         if (dpu_enc->cur_master->hw_mdptop &&
1103                         dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc)
1104                 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc(
1105                                 dpu_enc->cur_master->hw_mdptop,
1106                                 dpu_kms->catalog);
1107
1108         _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1109 }
1110
1111 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1112 {
1113         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1114
1115         mutex_lock(&dpu_enc->enc_lock);
1116
1117         if (!dpu_enc->enabled)
1118                 goto out;
1119
1120         if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1121                 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1122         if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1123                 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1124
1125         _dpu_encoder_virt_enable_helper(drm_enc);
1126
1127 out:
1128         mutex_unlock(&dpu_enc->enc_lock);
1129 }
1130
1131 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
1132 {
1133         struct dpu_encoder_virt *dpu_enc = NULL;
1134         int ret = 0;
1135         struct drm_display_mode *cur_mode = NULL;
1136
1137         if (!drm_enc) {
1138                 DPU_ERROR("invalid encoder\n");
1139                 return;
1140         }
1141         dpu_enc = to_dpu_encoder_virt(drm_enc);
1142
1143         mutex_lock(&dpu_enc->enc_lock);
1144         cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1145
1146         trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1147                              cur_mode->vdisplay);
1148
1149         /* always enable slave encoder before master */
1150         if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1151                 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1152
1153         if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1154                 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1155
1156         ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1157         if (ret) {
1158                 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1159                                 ret);
1160                 goto out;
1161         }
1162
1163         _dpu_encoder_virt_enable_helper(drm_enc);
1164
1165         dpu_enc->enabled = true;
1166
1167 out:
1168         mutex_unlock(&dpu_enc->enc_lock);
1169 }
1170
1171 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
1172 {
1173         struct dpu_encoder_virt *dpu_enc = NULL;
1174         struct msm_drm_private *priv;
1175         struct dpu_kms *dpu_kms;
1176         int i = 0;
1177
1178         if (!drm_enc) {
1179                 DPU_ERROR("invalid encoder\n");
1180                 return;
1181         } else if (!drm_enc->dev) {
1182                 DPU_ERROR("invalid dev\n");
1183                 return;
1184         }
1185
1186         dpu_enc = to_dpu_encoder_virt(drm_enc);
1187         DPU_DEBUG_ENC(dpu_enc, "\n");
1188
1189         mutex_lock(&dpu_enc->enc_lock);
1190         dpu_enc->enabled = false;
1191
1192         priv = drm_enc->dev->dev_private;
1193         dpu_kms = to_dpu_kms(priv->kms);
1194
1195         trace_dpu_enc_disable(DRMID(drm_enc));
1196
1197         /* wait for idle */
1198         dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
1199
1200         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1201
1202         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1203                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1204
1205                 if (phys && phys->ops.disable)
1206                         phys->ops.disable(phys);
1207         }
1208
1209         /* after phys waits for frame-done, should be no more frames pending */
1210         if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1211                 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1212                 del_timer_sync(&dpu_enc->frame_done_timer);
1213         }
1214
1215         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1216
1217         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1218                 if (dpu_enc->phys_encs[i])
1219                         dpu_enc->phys_encs[i]->connector = NULL;
1220         }
1221
1222         DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1223
1224         dpu_rm_release(&dpu_kms->rm, drm_enc);
1225
1226         mutex_unlock(&dpu_enc->enc_lock);
1227 }
1228
1229 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
1230                 enum dpu_intf_type type, u32 controller_id)
1231 {
1232         int i = 0;
1233
1234         for (i = 0; i < catalog->intf_count; i++) {
1235                 if (catalog->intf[i].type == type
1236                     && catalog->intf[i].controller_id == controller_id) {
1237                         return catalog->intf[i].id;
1238                 }
1239         }
1240
1241         return INTF_MAX;
1242 }
1243
1244 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1245                 struct dpu_encoder_phys *phy_enc)
1246 {
1247         struct dpu_encoder_virt *dpu_enc = NULL;
1248         unsigned long lock_flags;
1249
1250         if (!drm_enc || !phy_enc)
1251                 return;
1252
1253         DPU_ATRACE_BEGIN("encoder_vblank_callback");
1254         dpu_enc = to_dpu_encoder_virt(drm_enc);
1255
1256         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1257         if (dpu_enc->crtc)
1258                 dpu_crtc_vblank_callback(dpu_enc->crtc);
1259         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1260
1261         atomic_inc(&phy_enc->vsync_cnt);
1262         DPU_ATRACE_END("encoder_vblank_callback");
1263 }
1264
1265 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1266                 struct dpu_encoder_phys *phy_enc)
1267 {
1268         if (!phy_enc)
1269                 return;
1270
1271         DPU_ATRACE_BEGIN("encoder_underrun_callback");
1272         atomic_inc(&phy_enc->underrun_cnt);
1273         trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1274                                   atomic_read(&phy_enc->underrun_cnt));
1275         DPU_ATRACE_END("encoder_underrun_callback");
1276 }
1277
1278 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1279 {
1280         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1281         unsigned long lock_flags;
1282
1283         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1284         /* crtc should always be cleared before re-assigning */
1285         WARN_ON(crtc && dpu_enc->crtc);
1286         dpu_enc->crtc = crtc;
1287         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1288 }
1289
1290 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1291                                         struct drm_crtc *crtc, bool enable)
1292 {
1293         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1294         unsigned long lock_flags;
1295         int i;
1296
1297         trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1298
1299         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1300         if (dpu_enc->crtc != crtc) {
1301                 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1302                 return;
1303         }
1304         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1305
1306         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1307                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1308
1309                 if (phys && phys->ops.control_vblank_irq)
1310                         phys->ops.control_vblank_irq(phys, enable);
1311         }
1312 }
1313
1314 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
1315                 void (*frame_event_cb)(void *, u32 event),
1316                 void *frame_event_cb_data)
1317 {
1318         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1319         unsigned long lock_flags;
1320         bool enable;
1321
1322         enable = frame_event_cb ? true : false;
1323
1324         if (!drm_enc) {
1325                 DPU_ERROR("invalid encoder\n");
1326                 return;
1327         }
1328         trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable);
1329
1330         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1331         dpu_enc->crtc_frame_event_cb = frame_event_cb;
1332         dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data;
1333         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1334 }
1335
1336 static void dpu_encoder_frame_done_callback(
1337                 struct drm_encoder *drm_enc,
1338                 struct dpu_encoder_phys *ready_phys, u32 event)
1339 {
1340         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1341         unsigned int i;
1342
1343         if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1344                         | DPU_ENCODER_FRAME_EVENT_ERROR
1345                         | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1346
1347                 if (!dpu_enc->frame_busy_mask[0]) {
1348                         /**
1349                          * suppress frame_done without waiter,
1350                          * likely autorefresh
1351                          */
1352                         trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc),
1353                                         event, ready_phys->intf_idx);
1354                         return;
1355                 }
1356
1357                 /* One of the physical encoders has become idle */
1358                 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1359                         if (dpu_enc->phys_encs[i] == ready_phys) {
1360                                 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1361                                                 dpu_enc->frame_busy_mask[0]);
1362                                 clear_bit(i, dpu_enc->frame_busy_mask);
1363                         }
1364                 }
1365
1366                 if (!dpu_enc->frame_busy_mask[0]) {
1367                         atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1368                         del_timer(&dpu_enc->frame_done_timer);
1369
1370                         dpu_encoder_resource_control(drm_enc,
1371                                         DPU_ENC_RC_EVENT_FRAME_DONE);
1372
1373                         if (dpu_enc->crtc_frame_event_cb)
1374                                 dpu_enc->crtc_frame_event_cb(
1375                                         dpu_enc->crtc_frame_event_cb_data,
1376                                         event);
1377                 }
1378         } else {
1379                 if (dpu_enc->crtc_frame_event_cb)
1380                         dpu_enc->crtc_frame_event_cb(
1381                                 dpu_enc->crtc_frame_event_cb_data, event);
1382         }
1383 }
1384
1385 static void dpu_encoder_off_work(struct work_struct *work)
1386 {
1387         struct dpu_encoder_virt *dpu_enc = container_of(work,
1388                         struct dpu_encoder_virt, delayed_off_work.work);
1389
1390         if (!dpu_enc) {
1391                 DPU_ERROR("invalid dpu encoder\n");
1392                 return;
1393         }
1394
1395         dpu_encoder_resource_control(&dpu_enc->base,
1396                                                 DPU_ENC_RC_EVENT_ENTER_IDLE);
1397
1398         dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1399                                 DPU_ENCODER_FRAME_EVENT_IDLE);
1400 }
1401
1402 /**
1403  * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1404  * drm_enc: Pointer to drm encoder structure
1405  * phys: Pointer to physical encoder structure
1406  * extra_flush_bits: Additional bit mask to include in flush trigger
1407  */
1408 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1409                 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1410 {
1411         struct dpu_hw_ctl *ctl;
1412         int pending_kickoff_cnt;
1413         u32 ret = UINT_MAX;
1414
1415         if (!phys->hw_pp) {
1416                 DPU_ERROR("invalid pingpong hw\n");
1417                 return;
1418         }
1419
1420         ctl = phys->hw_ctl;
1421         if (!ctl || !ctl->ops.trigger_flush) {
1422                 DPU_ERROR("missing trigger cb\n");
1423                 return;
1424         }
1425
1426         pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1427
1428         if (extra_flush_bits && ctl->ops.update_pending_flush)
1429                 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1430
1431         ctl->ops.trigger_flush(ctl);
1432
1433         if (ctl->ops.get_pending_flush)
1434                 ret = ctl->ops.get_pending_flush(ctl);
1435
1436         trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
1437                                     pending_kickoff_cnt, ctl->idx,
1438                                     extra_flush_bits, ret);
1439 }
1440
1441 /**
1442  * _dpu_encoder_trigger_start - trigger start for a physical encoder
1443  * phys: Pointer to physical encoder structure
1444  */
1445 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1446 {
1447         if (!phys) {
1448                 DPU_ERROR("invalid argument(s)\n");
1449                 return;
1450         }
1451
1452         if (!phys->hw_pp) {
1453                 DPU_ERROR("invalid pingpong hw\n");
1454                 return;
1455         }
1456
1457         if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1458                 phys->ops.trigger_start(phys);
1459 }
1460
1461 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1462 {
1463         struct dpu_hw_ctl *ctl;
1464
1465         if (!phys_enc) {
1466                 DPU_ERROR("invalid encoder\n");
1467                 return;
1468         }
1469
1470         ctl = phys_enc->hw_ctl;
1471         if (ctl && ctl->ops.trigger_start) {
1472                 ctl->ops.trigger_start(ctl);
1473                 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1474         }
1475 }
1476
1477 static int dpu_encoder_helper_wait_event_timeout(
1478                 int32_t drm_id,
1479                 int32_t hw_id,
1480                 struct dpu_encoder_wait_info *info)
1481 {
1482         int rc = 0;
1483         s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1484         s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1485         s64 time;
1486
1487         do {
1488                 rc = wait_event_timeout(*(info->wq),
1489                                 atomic_read(info->atomic_cnt) == 0, jiffies);
1490                 time = ktime_to_ms(ktime_get());
1491
1492                 trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
1493                                                  expected_time,
1494                                                  atomic_read(info->atomic_cnt));
1495         /* If we timed out, counter is valid and time is less, wait again */
1496         } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1497                         (time < expected_time));
1498
1499         return rc;
1500 }
1501
1502 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1503 {
1504         struct dpu_encoder_virt *dpu_enc;
1505         struct dpu_hw_ctl *ctl;
1506         int rc;
1507
1508         if (!phys_enc) {
1509                 DPU_ERROR("invalid encoder\n");
1510                 return;
1511         }
1512         dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1513         ctl = phys_enc->hw_ctl;
1514
1515         if (!ctl || !ctl->ops.reset)
1516                 return;
1517
1518         DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
1519                       ctl->idx);
1520
1521         rc = ctl->ops.reset(ctl);
1522         if (rc)
1523                 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n",  ctl->idx);
1524
1525         phys_enc->enable_state = DPU_ENC_ENABLED;
1526 }
1527
1528 /**
1529  * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1530  *      Iterate through the physical encoders and perform consolidated flush
1531  *      and/or control start triggering as needed. This is done in the virtual
1532  *      encoder rather than the individual physical ones in order to handle
1533  *      use cases that require visibility into multiple physical encoders at
1534  *      a time.
1535  * dpu_enc: Pointer to virtual encoder structure
1536  */
1537 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1538 {
1539         struct dpu_hw_ctl *ctl;
1540         uint32_t i, pending_flush;
1541         unsigned long lock_flags;
1542
1543         pending_flush = 0x0;
1544
1545         /* update pending counts and trigger kickoff ctl flush atomically */
1546         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1547
1548         /* don't perform flush/start operations for slave encoders */
1549         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1550                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1551
1552                 if (!phys || phys->enable_state == DPU_ENC_DISABLED)
1553                         continue;
1554
1555                 ctl = phys->hw_ctl;
1556                 if (!ctl)
1557                         continue;
1558
1559                 /*
1560                  * This is cleared in frame_done worker, which isn't invoked
1561                  * for async commits. So don't set this for async, since it'll
1562                  * roll over to the next commit.
1563                  */
1564                 if (phys->split_role != ENC_ROLE_SLAVE)
1565                         set_bit(i, dpu_enc->frame_busy_mask);
1566
1567                 if (!phys->ops.needs_single_flush ||
1568                                 !phys->ops.needs_single_flush(phys))
1569                         _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1570                 else if (ctl->ops.get_pending_flush)
1571                         pending_flush |= ctl->ops.get_pending_flush(ctl);
1572         }
1573
1574         /* for split flush, combine pending flush masks and send to master */
1575         if (pending_flush && dpu_enc->cur_master) {
1576                 _dpu_encoder_trigger_flush(
1577                                 &dpu_enc->base,
1578                                 dpu_enc->cur_master,
1579                                 pending_flush);
1580         }
1581
1582         _dpu_encoder_trigger_start(dpu_enc->cur_master);
1583
1584         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1585 }
1586
1587 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1588 {
1589         struct dpu_encoder_virt *dpu_enc;
1590         struct dpu_encoder_phys *phys;
1591         unsigned int i;
1592         struct dpu_hw_ctl *ctl;
1593         struct msm_display_info *disp_info;
1594
1595         if (!drm_enc) {
1596                 DPU_ERROR("invalid encoder\n");
1597                 return;
1598         }
1599         dpu_enc = to_dpu_encoder_virt(drm_enc);
1600         disp_info = &dpu_enc->disp_info;
1601
1602         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1603                 phys = dpu_enc->phys_encs[i];
1604
1605                 if (phys && phys->hw_ctl) {
1606                         ctl = phys->hw_ctl;
1607                         if (ctl->ops.clear_pending_flush)
1608                                 ctl->ops.clear_pending_flush(ctl);
1609
1610                         /* update only for command mode primary ctl */
1611                         if ((phys == dpu_enc->cur_master) &&
1612                            (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
1613                             && ctl->ops.trigger_pending)
1614                                 ctl->ops.trigger_pending(ctl);
1615                 }
1616         }
1617 }
1618
1619 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1620                 struct drm_display_mode *mode)
1621 {
1622         u64 pclk_rate;
1623         u32 pclk_period;
1624         u32 line_time;
1625
1626         /*
1627          * For linetime calculation, only operate on master encoder.
1628          */
1629         if (!dpu_enc->cur_master)
1630                 return 0;
1631
1632         if (!dpu_enc->cur_master->ops.get_line_count) {
1633                 DPU_ERROR("get_line_count function not defined\n");
1634                 return 0;
1635         }
1636
1637         pclk_rate = mode->clock; /* pixel clock in kHz */
1638         if (pclk_rate == 0) {
1639                 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1640                 return 0;
1641         }
1642
1643         pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1644         if (pclk_period == 0) {
1645                 DPU_ERROR("pclk period is 0\n");
1646                 return 0;
1647         }
1648
1649         /*
1650          * Line time calculation based on Pixel clock and HTOTAL.
1651          * Final unit is in ns.
1652          */
1653         line_time = (pclk_period * mode->htotal) / 1000;
1654         if (line_time == 0) {
1655                 DPU_ERROR("line time calculation is 0\n");
1656                 return 0;
1657         }
1658
1659         DPU_DEBUG_ENC(dpu_enc,
1660                         "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1661                         pclk_rate, pclk_period, line_time);
1662
1663         return line_time;
1664 }
1665
1666 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1667 {
1668         struct drm_display_mode *mode;
1669         struct dpu_encoder_virt *dpu_enc;
1670         u32 cur_line;
1671         u32 line_time;
1672         u32 vtotal, time_to_vsync;
1673         ktime_t cur_time;
1674
1675         dpu_enc = to_dpu_encoder_virt(drm_enc);
1676
1677         if (!drm_enc->crtc || !drm_enc->crtc->state) {
1678                 DPU_ERROR("crtc/crtc state object is NULL\n");
1679                 return -EINVAL;
1680         }
1681         mode = &drm_enc->crtc->state->adjusted_mode;
1682
1683         line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1684         if (!line_time)
1685                 return -EINVAL;
1686
1687         cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1688
1689         vtotal = mode->vtotal;
1690         if (cur_line >= vtotal)
1691                 time_to_vsync = line_time * vtotal;
1692         else
1693                 time_to_vsync = line_time * (vtotal - cur_line);
1694
1695         if (time_to_vsync == 0) {
1696                 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1697                                 vtotal);
1698                 return -EINVAL;
1699         }
1700
1701         cur_time = ktime_get();
1702         *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1703
1704         DPU_DEBUG_ENC(dpu_enc,
1705                         "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1706                         cur_line, vtotal, time_to_vsync,
1707                         ktime_to_ms(cur_time),
1708                         ktime_to_ms(*wakeup_time));
1709         return 0;
1710 }
1711
1712 static void dpu_encoder_vsync_event_handler(struct timer_list *t)
1713 {
1714         struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
1715                         vsync_event_timer);
1716         struct drm_encoder *drm_enc = &dpu_enc->base;
1717         struct msm_drm_private *priv;
1718         struct msm_drm_thread *event_thread;
1719
1720         if (!drm_enc->dev || !drm_enc->crtc) {
1721                 DPU_ERROR("invalid parameters\n");
1722                 return;
1723         }
1724
1725         priv = drm_enc->dev->dev_private;
1726
1727         if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
1728                 DPU_ERROR("invalid crtc index\n");
1729                 return;
1730         }
1731         event_thread = &priv->event_thread[drm_enc->crtc->index];
1732         if (!event_thread) {
1733                 DPU_ERROR("event_thread not found for crtc:%d\n",
1734                                 drm_enc->crtc->index);
1735                 return;
1736         }
1737
1738         del_timer(&dpu_enc->vsync_event_timer);
1739 }
1740
1741 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
1742 {
1743         struct dpu_encoder_virt *dpu_enc = container_of(work,
1744                         struct dpu_encoder_virt, vsync_event_work);
1745         ktime_t wakeup_time;
1746
1747         if (!dpu_enc) {
1748                 DPU_ERROR("invalid dpu encoder\n");
1749                 return;
1750         }
1751
1752         if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
1753                 return;
1754
1755         trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
1756         mod_timer(&dpu_enc->vsync_event_timer,
1757                         nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1758 }
1759
1760 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
1761 {
1762         struct dpu_encoder_virt *dpu_enc;
1763         struct dpu_encoder_phys *phys;
1764         bool needs_hw_reset = false;
1765         unsigned int i;
1766
1767         dpu_enc = to_dpu_encoder_virt(drm_enc);
1768
1769         trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
1770
1771         /* prepare for next kickoff, may include waiting on previous kickoff */
1772         DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1773         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1774                 phys = dpu_enc->phys_encs[i];
1775                 if (phys) {
1776                         if (phys->ops.prepare_for_kickoff)
1777                                 phys->ops.prepare_for_kickoff(phys);
1778                         if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1779                                 needs_hw_reset = true;
1780                 }
1781         }
1782         DPU_ATRACE_END("enc_prepare_for_kickoff");
1783
1784         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1785
1786         /* if any phys needs reset, reset all phys, in-order */
1787         if (needs_hw_reset) {
1788                 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1789                 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1790                         dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1791                 }
1792         }
1793 }
1794
1795 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
1796 {
1797         struct dpu_encoder_virt *dpu_enc;
1798         struct dpu_encoder_phys *phys;
1799         ktime_t wakeup_time;
1800         unsigned long timeout_ms;
1801         unsigned int i;
1802
1803         DPU_ATRACE_BEGIN("encoder_kickoff");
1804         dpu_enc = to_dpu_encoder_virt(drm_enc);
1805
1806         trace_dpu_enc_kickoff(DRMID(drm_enc));
1807
1808         timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
1809                         drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
1810
1811         atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
1812         mod_timer(&dpu_enc->frame_done_timer,
1813                         jiffies + msecs_to_jiffies(timeout_ms));
1814
1815         /* All phys encs are ready to go, trigger the kickoff */
1816         _dpu_encoder_kickoff_phys(dpu_enc);
1817
1818         /* allow phys encs to handle any post-kickoff business */
1819         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1820                 phys = dpu_enc->phys_encs[i];
1821                 if (phys && phys->ops.handle_post_kickoff)
1822                         phys->ops.handle_post_kickoff(phys);
1823         }
1824
1825         if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1826                         !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) {
1827                 trace_dpu_enc_early_kickoff(DRMID(drm_enc),
1828                                             ktime_to_ms(wakeup_time));
1829                 mod_timer(&dpu_enc->vsync_event_timer,
1830                                 nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1831         }
1832
1833         DPU_ATRACE_END("encoder_kickoff");
1834 }
1835
1836 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
1837 {
1838         struct dpu_encoder_virt *dpu_enc;
1839         struct dpu_encoder_phys *phys;
1840         int i;
1841
1842         if (!drm_enc) {
1843                 DPU_ERROR("invalid encoder\n");
1844                 return;
1845         }
1846         dpu_enc = to_dpu_encoder_virt(drm_enc);
1847
1848         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1849                 phys = dpu_enc->phys_encs[i];
1850                 if (phys && phys->ops.prepare_commit)
1851                         phys->ops.prepare_commit(phys);
1852         }
1853 }
1854
1855 #ifdef CONFIG_DEBUG_FS
1856 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
1857 {
1858         struct dpu_encoder_virt *dpu_enc = s->private;
1859         int i;
1860
1861         mutex_lock(&dpu_enc->enc_lock);
1862         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1863                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1864
1865                 if (!phys)
1866                         continue;
1867
1868                 seq_printf(s, "intf:%d    vsync:%8d     underrun:%8d    ",
1869                                 phys->intf_idx - INTF_0,
1870                                 atomic_read(&phys->vsync_cnt),
1871                                 atomic_read(&phys->underrun_cnt));
1872
1873                 switch (phys->intf_mode) {
1874                 case INTF_MODE_VIDEO:
1875                         seq_puts(s, "mode: video\n");
1876                         break;
1877                 case INTF_MODE_CMD:
1878                         seq_puts(s, "mode: command\n");
1879                         break;
1880                 default:
1881                         seq_puts(s, "mode: ???\n");
1882                         break;
1883                 }
1884         }
1885         mutex_unlock(&dpu_enc->enc_lock);
1886
1887         return 0;
1888 }
1889
1890 static int _dpu_encoder_debugfs_status_open(struct inode *inode,
1891                 struct file *file)
1892 {
1893         return single_open(file, _dpu_encoder_status_show, inode->i_private);
1894 }
1895
1896 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1897 {
1898         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1899         int i;
1900
1901         static const struct file_operations debugfs_status_fops = {
1902                 .open =         _dpu_encoder_debugfs_status_open,
1903                 .read =         seq_read,
1904                 .llseek =       seq_lseek,
1905                 .release =      single_release,
1906         };
1907
1908         char name[DPU_NAME_SIZE];
1909
1910         if (!drm_enc->dev) {
1911                 DPU_ERROR("invalid encoder or kms\n");
1912                 return -EINVAL;
1913         }
1914
1915         snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id);
1916
1917         /* create overall sub-directory for the encoder */
1918         dpu_enc->debugfs_root = debugfs_create_dir(name,
1919                         drm_enc->dev->primary->debugfs_root);
1920
1921         /* don't error check these */
1922         debugfs_create_file("status", 0600,
1923                 dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops);
1924
1925         for (i = 0; i < dpu_enc->num_phys_encs; i++)
1926                 if (dpu_enc->phys_encs[i] &&
1927                                 dpu_enc->phys_encs[i]->ops.late_register)
1928                         dpu_enc->phys_encs[i]->ops.late_register(
1929                                         dpu_enc->phys_encs[i],
1930                                         dpu_enc->debugfs_root);
1931
1932         return 0;
1933 }
1934 #else
1935 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1936 {
1937         return 0;
1938 }
1939 #endif
1940
1941 static int dpu_encoder_late_register(struct drm_encoder *encoder)
1942 {
1943         return _dpu_encoder_init_debugfs(encoder);
1944 }
1945
1946 static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
1947 {
1948         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
1949
1950         debugfs_remove_recursive(dpu_enc->debugfs_root);
1951 }
1952
1953 static int dpu_encoder_virt_add_phys_encs(
1954                 u32 display_caps,
1955                 struct dpu_encoder_virt *dpu_enc,
1956                 struct dpu_enc_phys_init_params *params)
1957 {
1958         struct dpu_encoder_phys *enc = NULL;
1959
1960         DPU_DEBUG_ENC(dpu_enc, "\n");
1961
1962         /*
1963          * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
1964          * in this function, check up-front.
1965          */
1966         if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
1967                         ARRAY_SIZE(dpu_enc->phys_encs)) {
1968                 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
1969                           dpu_enc->num_phys_encs);
1970                 return -EINVAL;
1971         }
1972
1973         if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
1974                 enc = dpu_encoder_phys_vid_init(params);
1975
1976                 if (IS_ERR_OR_NULL(enc)) {
1977                         DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
1978                                 PTR_ERR(enc));
1979                         return enc == 0 ? -EINVAL : PTR_ERR(enc);
1980                 }
1981
1982                 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
1983                 ++dpu_enc->num_phys_encs;
1984         }
1985
1986         if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
1987                 enc = dpu_encoder_phys_cmd_init(params);
1988
1989                 if (IS_ERR_OR_NULL(enc)) {
1990                         DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
1991                                 PTR_ERR(enc));
1992                         return enc == 0 ? -EINVAL : PTR_ERR(enc);
1993                 }
1994
1995                 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
1996                 ++dpu_enc->num_phys_encs;
1997         }
1998
1999         if (params->split_role == ENC_ROLE_SLAVE)
2000                 dpu_enc->cur_slave = enc;
2001         else
2002                 dpu_enc->cur_master = enc;
2003
2004         return 0;
2005 }
2006
2007 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = {
2008         .handle_vblank_virt = dpu_encoder_vblank_callback,
2009         .handle_underrun_virt = dpu_encoder_underrun_callback,
2010         .handle_frame_done = dpu_encoder_frame_done_callback,
2011 };
2012
2013 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2014                                  struct dpu_kms *dpu_kms,
2015                                  struct msm_display_info *disp_info)
2016 {
2017         int ret = 0;
2018         int i = 0;
2019         enum dpu_intf_type intf_type;
2020         struct dpu_enc_phys_init_params phys_params;
2021
2022         if (!dpu_enc) {
2023                 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != 0);
2024                 return -EINVAL;
2025         }
2026
2027         dpu_enc->cur_master = NULL;
2028
2029         memset(&phys_params, 0, sizeof(phys_params));
2030         phys_params.dpu_kms = dpu_kms;
2031         phys_params.parent = &dpu_enc->base;
2032         phys_params.parent_ops = &dpu_encoder_parent_ops;
2033         phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2034
2035         DPU_DEBUG("\n");
2036
2037         switch (disp_info->intf_type) {
2038         case DRM_MODE_ENCODER_DSI:
2039                 intf_type = INTF_DSI;
2040                 break;
2041         default:
2042                 DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n");
2043                 return -EINVAL;
2044         }
2045
2046         WARN_ON(disp_info->num_of_h_tiles < 1);
2047
2048         DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2049
2050         if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
2051             (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
2052                 dpu_enc->idle_pc_supported =
2053                                 dpu_kms->catalog->caps->has_idle_pc;
2054
2055         mutex_lock(&dpu_enc->enc_lock);
2056         for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2057                 /*
2058                  * Left-most tile is at index 0, content is controller id
2059                  * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2060                  * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2061                  */
2062                 u32 controller_id = disp_info->h_tile_instance[i];
2063
2064                 if (disp_info->num_of_h_tiles > 1) {
2065                         if (i == 0)
2066                                 phys_params.split_role = ENC_ROLE_MASTER;
2067                         else
2068                                 phys_params.split_role = ENC_ROLE_SLAVE;
2069                 } else {
2070                         phys_params.split_role = ENC_ROLE_SOLO;
2071                 }
2072
2073                 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2074                                 i, controller_id, phys_params.split_role);
2075
2076                 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
2077                                                                                                         intf_type,
2078                                                                                                         controller_id);
2079                 if (phys_params.intf_idx == INTF_MAX) {
2080                         DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n",
2081                                                   intf_type, controller_id);
2082                         ret = -EINVAL;
2083                 }
2084
2085                 if (!ret) {
2086                         ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities,
2087                                                                                                  dpu_enc,
2088                                                                                                  &phys_params);
2089                         if (ret)
2090                                 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2091                 }
2092         }
2093
2094         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2095                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2096
2097                 if (phys) {
2098                         atomic_set(&phys->vsync_cnt, 0);
2099                         atomic_set(&phys->underrun_cnt, 0);
2100                 }
2101         }
2102         mutex_unlock(&dpu_enc->enc_lock);
2103
2104         return ret;
2105 }
2106
2107 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2108 {
2109         struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2110                         frame_done_timer);
2111         struct drm_encoder *drm_enc = &dpu_enc->base;
2112         u32 event;
2113
2114         if (!drm_enc->dev) {
2115                 DPU_ERROR("invalid parameters\n");
2116                 return;
2117         }
2118
2119         if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
2120                 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2121                               DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2122                 return;
2123         } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2124                 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2125                 return;
2126         }
2127
2128         DPU_ERROR_ENC(dpu_enc, "frame done timeout\n");
2129
2130         event = DPU_ENCODER_FRAME_EVENT_ERROR;
2131         trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2132         dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
2133 }
2134
2135 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2136         .mode_set = dpu_encoder_virt_mode_set,
2137         .disable = dpu_encoder_virt_disable,
2138         .enable = dpu_kms_encoder_enable,
2139         .atomic_check = dpu_encoder_virt_atomic_check,
2140
2141         /* This is called by dpu_kms_encoder_enable */
2142         .commit = dpu_encoder_virt_enable,
2143 };
2144
2145 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2146                 .destroy = dpu_encoder_destroy,
2147                 .late_register = dpu_encoder_late_register,
2148                 .early_unregister = dpu_encoder_early_unregister,
2149 };
2150
2151 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
2152                 struct msm_display_info *disp_info)
2153 {
2154         struct msm_drm_private *priv = dev->dev_private;
2155         struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2156         struct drm_encoder *drm_enc = NULL;
2157         struct dpu_encoder_virt *dpu_enc = NULL;
2158         int ret = 0;
2159
2160         dpu_enc = to_dpu_encoder_virt(enc);
2161
2162         mutex_init(&dpu_enc->enc_lock);
2163         ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2164         if (ret)
2165                 goto fail;
2166
2167         atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2168         timer_setup(&dpu_enc->frame_done_timer,
2169                         dpu_encoder_frame_done_timeout, 0);
2170
2171         if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
2172                 timer_setup(&dpu_enc->vsync_event_timer,
2173                                 dpu_encoder_vsync_event_handler,
2174                                 0);
2175
2176
2177         mutex_init(&dpu_enc->rc_lock);
2178         INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2179                         dpu_encoder_off_work);
2180         dpu_enc->idle_timeout = IDLE_TIMEOUT;
2181
2182         kthread_init_work(&dpu_enc->vsync_event_work,
2183                         dpu_encoder_vsync_event_work_handler);
2184
2185         memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2186
2187         DPU_DEBUG_ENC(dpu_enc, "created\n");
2188
2189         return ret;
2190
2191 fail:
2192         DPU_ERROR("failed to create encoder\n");
2193         if (drm_enc)
2194                 dpu_encoder_destroy(drm_enc);
2195
2196         return ret;
2197
2198
2199 }
2200
2201 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2202                 int drm_enc_mode)
2203 {
2204         struct dpu_encoder_virt *dpu_enc = NULL;
2205         int rc = 0;
2206
2207         dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL);
2208         if (!dpu_enc)
2209                 return ERR_PTR(ENOMEM);
2210
2211         rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs,
2212                         drm_enc_mode, NULL);
2213         if (rc) {
2214                 devm_kfree(dev->dev, dpu_enc);
2215                 return ERR_PTR(rc);
2216         }
2217
2218         drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2219
2220         spin_lock_init(&dpu_enc->enc_spinlock);
2221         dpu_enc->enabled = false;
2222
2223         return &dpu_enc->base;
2224 }
2225
2226 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
2227         enum msm_event_wait event)
2228 {
2229         int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL;
2230         struct dpu_encoder_virt *dpu_enc = NULL;
2231         int i, ret = 0;
2232
2233         if (!drm_enc) {
2234                 DPU_ERROR("invalid encoder\n");
2235                 return -EINVAL;
2236         }
2237         dpu_enc = to_dpu_encoder_virt(drm_enc);
2238         DPU_DEBUG_ENC(dpu_enc, "\n");
2239
2240         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2241                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2242                 if (!phys)
2243                         continue;
2244
2245                 switch (event) {
2246                 case MSM_ENC_COMMIT_DONE:
2247                         fn_wait = phys->ops.wait_for_commit_done;
2248                         break;
2249                 case MSM_ENC_TX_COMPLETE:
2250                         fn_wait = phys->ops.wait_for_tx_complete;
2251                         break;
2252                 case MSM_ENC_VBLANK:
2253                         fn_wait = phys->ops.wait_for_vblank;
2254                         break;
2255                 default:
2256                         DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
2257                                         event);
2258                         return -EINVAL;
2259                 };
2260
2261                 if (fn_wait) {
2262                         DPU_ATRACE_BEGIN("wait_for_completion_event");
2263                         ret = fn_wait(phys);
2264                         DPU_ATRACE_END("wait_for_completion_event");
2265                         if (ret)
2266                                 return ret;
2267                 }
2268         }
2269
2270         return ret;
2271 }
2272
2273 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2274 {
2275         struct dpu_encoder_virt *dpu_enc = NULL;
2276         int i;
2277
2278         if (!encoder) {
2279                 DPU_ERROR("invalid encoder\n");
2280                 return INTF_MODE_NONE;
2281         }
2282         dpu_enc = to_dpu_encoder_virt(encoder);
2283
2284         if (dpu_enc->cur_master)
2285                 return dpu_enc->cur_master->intf_mode;
2286
2287         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2288                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2289
2290                 if (phys)
2291                         return phys->intf_mode;
2292         }
2293
2294         return INTF_MODE_NONE;
2295 }