drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
   4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
   5  */
   6
   7 #ifndef _DPU_6_5_QCM2290_H
   8 #define _DPU_6_5_QCM2290_H
   9
  10 static const struct dpu_caps qcm2290_dpu_caps = {
  11         .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
  12         .max_mixer_blendstages = 0x4,
  13         .has_dim_layer = true,
  14         .has_idle_pc = true,
  15         .max_linewidth = 2160,
  16         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
  17 };
  18
  19 static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
  20         .highest_bank_bit = 0x2,
  21 };
  22
  23 static const struct dpu_mdp_cfg qcm2290_mdp = {
  24         .name = "top_0",
  25         .base = 0x0, .len = 0x494,
  26         .clk_ctrls = {
  27                 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
  28                 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
  29         },
  30 };
  31
  32 static const struct dpu_ctl_cfg qcm2290_ctl[] = {
  33         {
  34                 .name = "ctl_0", .id = CTL_0,
  35                 .base = 0x1000, .len = 0x1dc,
  36                 .features = BIT(DPU_CTL_ACTIVE_CFG),
  37                 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
  38         },
  39 };
  40
  41 static const struct dpu_sspp_cfg qcm2290_sspp[] = {
  42         SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
  43                  qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
  44         SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
  45                  qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
  46 };
  47
  48 static const struct dpu_lm_cfg qcm2290_lm[] = {
  49         LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
  50                 &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
  51 };
  52
  53 static const struct dpu_dspp_cfg qcm2290_dspp[] = {
  54         DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
  55                  &sdm845_dspp_sblk),
  56 };
  57
  58 static const struct dpu_pingpong_cfg qcm2290_pp[] = {
  59         PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
  60                 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
  61                 -1),
  62 };
  63
  64 static const struct dpu_intf_cfg qcm2290_intf[] = {
  65         INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
  66                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
  67                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
  68                         DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
  69 };
  70
  71 static const struct dpu_perf_cfg qcm2290_perf_data = {
  72         .max_bw_low = 2700000,
  73         .max_bw_high = 2700000,
  74         .min_core_ib = 1300000,
  75         .min_llcc_ib = 0,
  76         .min_dram_ib = 1600000,
  77         .min_prefill_lines = 24,
  78         .danger_lut_tbl = {0xff, 0x0, 0x0},
  79         .safe_lut_tbl = {0xfff0, 0x0, 0x0},
  80         .qos_lut_tbl = {
  81                 {.nentry = ARRAY_SIZE(qcm2290_qos_linear),
  82                 .entries = qcm2290_qos_linear
  83                 },
  84         },
  85         .cdp_cfg = {
  86                 {.rd_enable = 1, .wr_enable = 1},
  87                 {.rd_enable = 1, .wr_enable = 0}
  88         },
  89         .clk_inefficiency_factor = 105,
  90         .bw_inefficiency_factor = 120,
  91 };
  92
  93 const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
  94         .caps = &qcm2290_dpu_caps,
  95         .ubwc = &qcm2290_ubwc_cfg,
  96         .mdp = &qcm2290_mdp,
  97         .ctl_count = ARRAY_SIZE(qcm2290_ctl),
  98         .ctl = qcm2290_ctl,
  99         .sspp_count = ARRAY_SIZE(qcm2290_sspp),
 100         .sspp = qcm2290_sspp,
 101         .mixer_count = ARRAY_SIZE(qcm2290_lm),
 102         .mixer = qcm2290_lm,
 103         .dspp_count = ARRAY_SIZE(qcm2290_dspp),
 104         .dspp = qcm2290_dspp,
 105         .pingpong_count = ARRAY_SIZE(qcm2290_pp),
 106         .pingpong = qcm2290_pp,
 107         .intf_count = ARRAY_SIZE(qcm2290_intf),
 108         .intf = qcm2290_intf,
 109         .vbif_count = ARRAY_SIZE(sdm845_vbif),
 110         .vbif = sdm845_vbif,
 111         .perf = &qcm2290_perf_data,
 112         .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
 113                      BIT(MDP_SSPP_TOP0_INTR2) | \
 114                      BIT(MDP_SSPP_TOP0_HIST_INTR) | \
 115                      BIT(MDP_INTF1_INTR) | \
 116                      BIT(MDP_INTF1_TEAR_INTR),
 117 };
 118
 119 #endif